12 Commits

Author	SHA1	Message	Date
marqs	9d496383c3	optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl	2019-10-06 23:54:32 +03:00
marqs	6266976114	first OSD implementation	2019-10-03 02:03:43 +03:00
marqs	c7fc62c038	use symlinks for SW IP BSP files	2019-09-30 18:56:27 +03:00
marqs	5e0277fb48	add Panasonic hack for improving line count tolerance with line2x	2019-07-01 19:15:57 +03:00
marqs	9e81fb5922	Scanline updates and fixes ... * Enable overlay pattern customization * Fix non-alternating mode with line4x interlace sources * Add alternate interval option for pre-linedoubled sources	2019-03-23 00:09:46 +02:00
marqs	055a794b5e	move bitswap inside epcq_controller driver	2018-10-09 23:16:37 +03:00
marqs	e8d5097ecb	replace nios crcCI with hw_crc32 qsys module	2018-10-07 23:38:26 +03:00
marqs	0a747cbce6	i2c_opencores: fix compilation warnings	2018-10-07 23:34:29 +03:00
marqs	4676cbd2f0	integrate zero-riscy	2018-10-06 13:19:12 +03:00
marqs	e1d8446752	BSP and sw modifications	2018-09-26 00:19:24 +03:00
marqs	f55e9a877e	SD SPI implementation finished	2016-10-21 01:19:53 +03:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00