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9d496383c3
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl |
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altera_epcq_controller_mod | ||
altera_jtag_avalon_master_mod | ||
hw_crc32_qsys | ||
i2c_opencores | ||
osd_generator | ||
pll_reconfig | ||
pulpino_qsys@b11dd7718e | ||
sc_config |