When describing the CPU's reset pin, the W65C02S data sheet says:
> All Registers are initialized by software except the Decimal and Interrupt
> disable mode select bits of the Processor Status Register (P) are initialized
> by hardware.
It then has a diagram of the power-on state of the processor status register:
> 7 6 5 4 3 2 1 0
> * * 1 1 0 1 * *
> N V - B D I Z C
>
> * = software initialized
Confusingly the text indicates that only the D and I flags are initialised by
hardware, while the diagram indicates that the B flag is initialised too.
Meanwhile, https://www.nesdev.org/wiki/CPU_power_up_state says that
the power-on state of the NES CPU is $34 (exactly matching the diagram above)
but https://www.nesdev.org/wiki/Status_flags#The_B_flag says that the B flag
does not physically exist within P register, it's only relevant in the copy
of P that gets pushed to the stack by BRK (set), PHP (set), or an interrupt
signal (cleared).
As a result, the most sensible power-on state for the processor status register
is with the "interrupt disable" flag set and everything else cleared.
- IR field in status panel now correctly displays the next instruction
to be executed, instead of the instruction that was just executed.
- Switched from built-in Java util logger to Logback
- Updated all copyright strings to 2016
The simulator now passes Klaus Dormann's 6502 Functional Test suite for
the first time.
Bug Fixes:
- PHP was not correctly setting the Break bit on the stack copy of the
processor status, so subsequent PLA's would not set the Break status
flag.
- The CPU had swapped NMI and IRQ reset vectors, so RTI was failing.
- BRK was pushing PC + 2 onto the stack, instead of PC + 1
- (Zero Page,X) addressing mode did not correctly wrap on zero page
boundaries.
- The instruction table used for disassembly had addressing modes
of LDA $B9 and $BD reversed. This did not affect behavior, only
disassembly of these instructions.
Other:
- Updated copyright date for 2013.
- Started migrating old JUnit 3 style tests to JUnit 4 annotations.
I was alarmed to discover just how slow `String.format()` is for doing
integer to hex conversions. Now that a trace window has been added to
Symon, it became especially clear that I needed a more efficient way to
handle it.
I looked into using `Integer.toHexString()`, but I would have had to
wrap it to do zero-padding, so I decided to just bite the bullet and do
my own with a lookup table. The implementation in `HexUtil` is just as
fast as `Integer.toHexString()`, but also zero-pads appropriately.
Combined with Java's `+` String concatenation, it seems perfectly
adequate.
For yet better performance with the trace window, it would make a lot of
sense to special-case stepping so that it just pops the top line off the
log, and appends to the bottom, rather than re-stringifying the entire
trace log each time. This will be a future enhancement.
Introduces an execution trace window that will keep track of the most
recent 10000 execution steps. I'm not entirely happy with the
implementation, yet.
This is something of a "Work in Progress" checkpoint of several features
that are all half baked:
1. Allow loading of 16KB ROM files at address $C000 at run-time, not
just at startup. See the "Load ROM..." File menu item.
2. Introduces the notion of "CPU Behaviors", so the core 6502 CPU
implementation can match the behavior of either an early NMOS 6502, late
NMOS 6502, or CMOS 65C02. Very little of this is actually implemented so
far.
3. Adds a completely bogus implementation of the 6522 VIA (it
does absolutely nothing right now).
4. Changes the address of the ACIA in the simulated system to match a
real hardware implementation I put together.
Bug Fixes:
- Fixed several bugs in the CPU that caused processor status flags to
be set incorrectly. Instructions affected were: STA, STX, STY, CMP,
CPX, CPY, BIT.
- Made some internal-use-only methods on the CPU class private.
- Fixed incorrect disassembly of (Indirect,X) and (Indirect),Y
instructions. Although this didn't affect behavior, it certainly
caused me some confusion in debugging.
- Added missing "BCS" instruction to instruction table.
Enhancements:
- Now includes a full version of Lee Davison's Enhanced 6502 BASIC
bundled as source code and a ROM image. Get that REAL COMPUTER
EXPERIENCE!(tm)
- If a file named "rom.bin" exists in the same directory where the
simulator is executed, it will be loaded at addresses $d000-$ffff.
- Gave the CPU an idle loop to make simulated timing a little more
realistic (but this is still an area needing major improvement)
- Changed the CPU's toString() method to give better debugging output.
- Added a small typeahead buffer to the Console.
- Better exception messaging.
Misc:
- Bumped version to 0.5, updated README.
This change introduces simulated baud rates in the ACIA. Baud rate is controlled just as in the real 6551, by writing to the ACIA's control register. Baud rates between 50 and 19,200 baud are selectable. A baud rate of 0 has special meaning, and turns off all simulated baud rate delays (on a real 6551, this means to use an external clock instead of the internal baud rate generator)
A busy-wait loop between steps in the simulator control program has also been added. This uses the high-resolution 'System.nanoTime()' call to wait a specific number of nanoseconds before continuing. Symon now waits at least 1uS between clock cycles, trying to approach a real 1MHz 6502 in performance. It is far from perfect, but it's better than it was.
Also refactored the status panel to use a BoxLayout, and DRY-up some of the code.
- Added ability to change inner border width of console window.
- Fixed a nasty bug that prevented key press handling.
- Reset now clears the accumulator and index registers.
MOS6551 ACIA at address $C000 which does buffered input and output via the
console. Updated the README with a bit more documentation, and bumped the
version number to 0.1 because I'm impatient.
