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Apple1_MiST
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compare: Apple-1-HW:c80b372ef2bd02670f0da12229d511e4ac715c28
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16 Commits
33433c5722 ... c80b372ef2

Author SHA1 Message Date
nino-porcino c80b372ef2 put display din as dout as in the real PIA 2022-05-21 21:17:25 +02:00
nino-porcino ac99eaff41 release 2022.05.21 2022-05-21 15:09:55 +02:00
nino-porcino c28860cf3c add Sidi project 2022-05-21 15:08:45 +02:00
nino-porcino 587d2fd886 add global clock to make it Sidi-complaint 2022-05-21 15:08:36 +02:00
nino-porcino 14464df7bc reduce block RAM size when using TMS & SID 2022-05-21 15:05:45 +02:00
nino-porcino e365dc059d support CTRL keys; add ESC and other missing keys 2022-05-21 12:50:55 +02:00
nino-porcino 3542d776f2 attempt to use another clock source for SDRAM 2022-05-21 12:50:02 +02:00
nino-porcino aa6042cabd rename sdram_* into bus_*; use assign instead of always block; optional SDRAM at $4000 2022-05-21 12:48:14 +02:00
nino-porcino 5dfe5a041c update TODO and format code 2022-05-07 11:41:49 +02:00
nino-porcino 0164f7da54 add PIA 6821 to project (not connected) 2022-05-07 11:41:22 +02:00
nino-porcino 18a124383f copy pin assigments from VIC20_MiST 2022-05-07 11:40:27 +02:00
nino-porcino a41bb35646 do not use system reset for display 2022-05-07 11:39:28 +02:00
nino-porcino 6c292189f9 remove Arlet's CPU reference 2022-05-07 11:38:37 +02:00
nino-porcino e8b3a6fdc3 replace Arlet Ottens's 6502 with T65 2022-05-04 14:16:18 +02:00
nino-porcino abfe99721e code format 2022-05-04 14:15:09 +02:00
nino-porcino 44398c6668 fix typo in comment 2022-05-04 14:14:42 +02:00
24 changed files with 3886 additions and 1658 deletions
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158
apple-one.qsf
View File

@ -118,7 +118,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
@ -148,6 +147,7 @@ set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
@ -190,11 +190,145 @@ set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
set_instance_assignment -name FAST_INPUT_REGISTER ON -to UART_RX
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
@ -202,6 +336,12 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# end ENTITY(apple1_mist)
# -----------------------
set_global_assignment -name VHDL_FILE rtl/pia6821/pia6821.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
set_global_assignment -name QIP_FILE rtl/T65/T65.qip
set_global_assignment -name VHDL_FILE rtl/sid/wave_map.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_top.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_regs.vhd
@ -236,9 +376,6 @@ set_global_assignment -name VERILOG_FILE "rtl/mist-modules/data_io.v"
set_global_assignment -name VHDL_FILE "rtl/mist-modules/dac.vhd"
set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mist-modules/cofi.sv"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/arcade_inputs.v"
set_global_assignment -name VERILOG_FILE rtl/arlet_6502/cpu.v
set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v
set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v
set_global_assignment -name VERILOG_FILE rtl/apple1.v
set_global_assignment -name VERILOG_FILE rtl/clock.v
set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
@ -269,4 +406,7 @@ set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_clk_gen-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_clk_gen.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_addr_mux-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_addr_mux.vhd
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_55 -to CLOCK_27_1
set_instance_assignment -name FAST_INPUT_REGISTER ON -to CLOCK_27
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

30
apple-one_Sidi.qpf Normal file
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@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 21:11:27 January 26, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:11:27 January 26, 2018"
# Revisions
PROJECT_REVISION = "apple-one_Sidi"

383
apple-one_Sidi.qsf Normal file
View File

@ -0,0 +1,383 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 11:23:36 April 10, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# apple-one_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:11:27 JANUARY 26, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY apple1_mist
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP4CE22F17C8
set_global_assignment -name FAMILY "Cyclone IV"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_G1 -to LED
set_location_assignment PIN_P16 -to VGA_R[5]
set_location_assignment PIN_P15 -to VGA_R[4]
set_location_assignment PIN_R16 -to VGA_R[3]
set_location_assignment PIN_R14 -to VGA_R[2]
set_location_assignment PIN_T15 -to VGA_R[1]
set_location_assignment PIN_T14 -to VGA_R[0]
set_location_assignment PIN_J16 -to VGA_B[5]
set_location_assignment PIN_J15 -to VGA_B[4]
set_location_assignment PIN_J14 -to VGA_B[3]
set_location_assignment PIN_K16 -to VGA_B[2]
set_location_assignment PIN_K15 -to VGA_B[1]
set_location_assignment PIN_J13 -to VGA_B[0]
set_location_assignment PIN_F16 -to VGA_G[5]
set_location_assignment PIN_F15 -to VGA_G[4]
set_location_assignment PIN_L16 -to VGA_G[3]
set_location_assignment PIN_L15 -to VGA_G[2]
set_location_assignment PIN_N15 -to VGA_G[1]
set_location_assignment PIN_N16 -to VGA_G[0]
set_location_assignment PIN_T10 -to VGA_VS
set_location_assignment PIN_T11 -to VGA_HS
set_location_assignment PIN_T12 -to AUDIO_L
set_location_assignment PIN_T13 -to AUDIO_R
set_location_assignment PIN_D1 -to UART_TX
set_location_assignment PIN_B1 -to UART_RX
set_location_assignment PIN_T2 -to SPI_DO
set_location_assignment PIN_R1 -to SPI_DI
set_location_assignment PIN_T3 -to SPI_SCK
set_location_assignment PIN_T4 -to SPI_SS2
set_location_assignment PIN_G15 -to SPI_SS3
set_location_assignment PIN_G16 -to SPI_SS4
set_location_assignment PIN_H2 -to CONF_DATA0
set_location_assignment PIN_B14 -to SDRAM_A[0]
set_location_assignment PIN_C14 -to SDRAM_A[1]
set_location_assignment PIN_C15 -to SDRAM_A[2]
set_location_assignment PIN_C16 -to SDRAM_A[3]
set_location_assignment PIN_B16 -to SDRAM_A[4]
set_location_assignment PIN_A15 -to SDRAM_A[5]
set_location_assignment PIN_A14 -to SDRAM_A[6]
set_location_assignment PIN_A13 -to SDRAM_A[7]
set_location_assignment PIN_A12 -to SDRAM_A[8]
set_location_assignment PIN_D16 -to SDRAM_A[9]
set_location_assignment PIN_B13 -to SDRAM_A[10]
set_location_assignment PIN_D15 -to SDRAM_A[11]
set_location_assignment PIN_D14 -to SDRAM_A[12]
set_location_assignment PIN_C3 -to SDRAM_DQ[0]
set_location_assignment PIN_C2 -to SDRAM_DQ[1]
set_location_assignment PIN_A4 -to SDRAM_DQ[2]
set_location_assignment PIN_B4 -to SDRAM_DQ[3]
set_location_assignment PIN_A6 -to SDRAM_DQ[4]
set_location_assignment PIN_D6 -to SDRAM_DQ[5]
set_location_assignment PIN_A7 -to SDRAM_DQ[6]
set_location_assignment PIN_B7 -to SDRAM_DQ[7]
set_location_assignment PIN_E6 -to SDRAM_DQ[8]
set_location_assignment PIN_C6 -to SDRAM_DQ[9]
set_location_assignment PIN_B6 -to SDRAM_DQ[10]
set_location_assignment PIN_B5 -to SDRAM_DQ[11]
set_location_assignment PIN_A5 -to SDRAM_DQ[12]
set_location_assignment PIN_B3 -to SDRAM_DQ[13]
set_location_assignment PIN_A3 -to SDRAM_DQ[14]
set_location_assignment PIN_A2 -to SDRAM_DQ[15]
set_location_assignment PIN_A11 -to SDRAM_BA[0]
set_location_assignment PIN_B12 -to SDRAM_BA[1]
set_location_assignment PIN_C9 -to SDRAM_DQMH
set_location_assignment PIN_C8 -to SDRAM_DQML
set_location_assignment PIN_A10 -to SDRAM_nRAS
set_location_assignment PIN_B10 -to SDRAM_nCAS
set_location_assignment PIN_D8 -to SDRAM_nWE
set_location_assignment PIN_B11 -to SDRAM_nCS
set_location_assignment PIN_C11 -to SDRAM_CKE
set_location_assignment PIN_R4 -to SDRAM_CLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
set_instance_assignment -name FAST_INPUT_REGISTER ON -to UART_RX
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# end ENTITY(apple1_mist)
# -----------------------
set_global_assignment -name VHDL_FILE rtl/pia6821/pia6821.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
set_global_assignment -name QIP_FILE rtl/T65/T65.qip
set_global_assignment -name VHDL_FILE rtl/sid/wave_map.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_top.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_regs.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_mixer.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_filter.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_debug_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/sid/sid_ctrl.vhd
set_global_assignment -name VHDL_FILE rtl/sid/Q_table.vhd
set_global_assignment -name VHDL_FILE rtl/sid/oscillator.vhd
set_global_assignment -name VHDL_FILE rtl/sid/my_math_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/sid/mult_acc.vhd
set_global_assignment -name VHDL_FILE rtl/sid/adsr_multi.vhd
set_global_assignment -name VERILOG_FILE rtl/aci.v
set_global_assignment -name VERILOG_FILE rtl/display_ram.v
set_global_assignment -name VERILOG_FILE rtl/tms9918/vram.v
set_global_assignment -name VERILOG_FILE rtl/tms9918/tms9918_async.v
set_global_assignment -name VERILOG_FILE rtl/tms9918/tms9918.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/downloader.sv
set_global_assignment -name VERILOG_FILE rtl/display.v
set_global_assignment -name VERILOG_FILE rtl/sdram.v
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/user_io.v"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/sd_card.v"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/scandoubler.v"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/rgb2ypbpr.v"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/osd.v"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/mist_video.v"
set_global_assignment -name QIP_FILE "rtl/mist-modules/mist_core.qip"
set_global_assignment -name VHDL_FILE "rtl/mist-modules/mist.vhd"
set_global_assignment -name QIP_FILE "rtl/mist-modules/mist.qip"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/data_io.v"
set_global_assignment -name VHDL_FILE "rtl/mist-modules/dac.vhd"
set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mist-modules/cofi.sv"
set_global_assignment -name VERILOG_FILE "rtl/mist-modules/arcade_inputs.v"
set_global_assignment -name VERILOG_FILE rtl/apple1.v
set_global_assignment -name VERILOG_FILE rtl/clock.v
set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v
set_global_assignment -name VERILOG_FILE rtl/ps2keyboard.v
set_global_assignment -name VERILOG_FILE rtl/font_rom.v
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/apple1_mist.sv
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_sprite-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_sprite.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_pattern-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_pattern.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_pack-p.vhd"
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_hor_vert-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_hor_vert.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_ctrl-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_ctrl.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_cpuio-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_cpuio.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_core-c.vhd"
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_core_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_core.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_col_pack-p.vhd"
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_col_mux-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_col_mux.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_clk_gen-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_clk_gen.vhd
set_global_assignment -name VHDL_FILE "rtl/tms9918/vdp18/vdp18_addr_mux-c.vhd"
set_global_assignment -name VHDL_FILE rtl/tms9918/vdp18/vdp18_addr_mux.vhd
set_location_assignment PIN_E1 -to CLOCK_27
set_location_assignment PIN_M2 -to CLOCK_27_1
set_instance_assignment -name FAST_INPUT_REGISTER ON -to CLOCK_27
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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rtl/T65/README Normal file
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@ -0,0 +1,68 @@
-- 65xx compatible microprocessor core
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- ----- IMPORTANT NOTES -----
--
-- Limitations:
-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
-- 65C02 supported : inc, dec, phx, plx, phy, ply
-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
-- Some interface signals behave incorrect
-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
--
-- Usage:
-- The enable signal allows clock gating / throttling without using the ready signal.
-- Set it to constant '1' when using the Clk input as the CPU clock directly.
--
-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
-- otherwise some undocumented opcodes won't work correctly.
-- EXAMPLE:
-- CPU : entity work.T65
-- port map (
-- R_W_n => cpu_rwn_s,
-- [....all other ports....]
-- DI => cpu_din_s,
-- DO => cpu_dout_s
-- );
-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
-- [....other sources from peripherals and memories...]
--
-- ----- IMPORTANT NOTES -----
--

4
rtl/T65/T65.qip Normal file
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@ -0,0 +1,4 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_Pack.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_ALU.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65_MCode.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T65.vhd]

707
rtl/T65/T65.vhd Normal file
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@ -0,0 +1,707 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 315 SzGy April 2020
-- Reduced the IRQ detection delay when RDY is not asserted (NMI?)
-- Undocumented opcodes behavior change during not RDY and page boundary crossing (VICE tests - cpu/sha, cpu/shs, cpu/shxy)
--
-- Ver 313 WoS January 2015
-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
-- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
--
-- Ver 312 WoS January 2015
-- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
-- Added comments in MCode section to find handling of individual opcodes more easily
-- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with
-- actual FPGAARCADE C64 core (sources used: SVN version 1021).
--
-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
-- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
-- SAX opcode
-- SHA opcode
-- SHX opcode
-- SHY opcode
-- SHS opcode
-- LAS opcode
-- alternate SBC opcode
-- fixed NOP with immediate param (caused Lorenz trap test to fail)
-- IRQ and NMI timing fixes (in conjuction with branches)
--
-- Ver 304 WoS December 2014
-- Undoc opcode fixes:
-- ARR opcode
-- ANE/XAA opcode
-- Corrected issue with NMI/IRQ prio (when asserted the same time)
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
-- Not correct opcodes acc. to Lorenz tests (incomplete list):
-- NOPN (nop)
-- NOPZX (nop + byte 172)
-- NOPAX (nop + word da ... da: byte 0)
-- ASOZ (byte $07 + byte 172)
--
-- Ver 303,302 WoS April 2014
-- Bugfixes for NMI from foft
-- Bugfix for BRK command (and its special flag)
--
-- Ver 300,301 WoS January 2014
-- More merging
-- Bugfixes by ehenciak added, started tidyup *bust*
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
-- ****
--
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- ----- IMPORTANT NOTES -----
--
-- Limitations:
-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
-- 65C02 supported : inc, dec, phx, plx, phy, ply
-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
-- Some interface signals behave incorrect
-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
--
-- Usage:
-- The enable signal allows clock gating / throttling without using the ready signal.
-- Set it to constant '1' when using the Clk input as the CPU clock directly.
--
-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
-- otherwise some undocumented opcodes won't work correctly.
-- EXAMPLE:
-- CPU : entity work.T65
-- port map (
-- R_W_n => cpu_rwn_s,
-- [....all other ports....]
-- DI => cpu_din_s,
-- DO => cpu_dout_s
-- );
-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
-- [....other sources from peripherals and memories...]
--
-- ----- IMPORTANT NOTES -----
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
BCD_en : in std_logic := '1'; -- '0' => 2A03/2A07, '1' => others
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic := '1';
Abort_n : in std_logic := '1';
IRQ_n : in std_logic := '1';
NMI_n : in std_logic := '1';
SO_n : in std_logic := '1';
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg;
NMI_ack : out std_logic
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal DO_r : std_logic_vector(7 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal BCD_en_r : std_logic;
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal BusB_r : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : T_ALU_Op;
signal Set_BusA_To : T_Set_BusA_To;
signal Set_Addr_To : T_Set_Addr_To;
signal Write_Data : T_Write_Data;
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BAQuirk : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal Res_n_i : std_logic;
signal Res_n_d : std_logic;
signal rdy_mod : std_logic; -- RDY signal turned off during the instruction
signal really_rdy : std_logic;
signal WRn_i : std_logic;
signal NMI_entered : std_logic;
begin
NMI_ack <= NMIAct;
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
R_W_n <= WRn_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
VPA <= '1' when Jump(1) = '0' else '0';
-- debugging signals
DEBUG.I <= IR;
DEBUG.A <= ABC(7 downto 0);
DEBUG.X <= X(7 downto 0);
DEBUG.Y <= Y(7 downto 0);
DEBUG.S <= std_logic_vector(S(7 downto 0));
DEBUG.P <= P;
Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
mcode : entity work.T65_MCode
port map(
--inputs
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
Rdy_mod => rdy_mod,
--outputs
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BAQuirk => BAQuirk,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : entity work.T65_ALU
port map(
Mode => Mode_r,
BCD_en => BCD_en_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
-- the 65xx design requires at least two clock cycles before
-- starting its reset sequence (according to datasheet)
process (Res_n, Clk)
begin
if Res_n = '0' then
Res_n_i <= '0';
Res_n_d <= '0';
elsif Clk'event and Clk = '1' then
Res_n_i <= Res_n_d;
Res_n_d <= '1';
end if;
end process;
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
BCD_en_r <= '1';
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
WRn_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
-- some instructions behavior changed by the Rdy line. Detect this at the correct cycles.
if MCycle = "000" then
rdy_mod <= '0';
elsif ((MCycle = "011" and IR /= x"93") or (MCycle = "100" and IR = x"93")) and Rdy = '0' then
rdy_mod <= '1';
end if;
if (really_rdy = '1') then
WRn_i <= not Write or RstCycle;
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
BCD_en_r <= BCD_en;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
S(7 downto 0) <= unsigned(ALU_Q);
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= Set_Addr_To_PBR;
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and (RstCycle = '0' or Mode = "00") then -- Decrement during reset - 6502 only?
S <= S - 1;
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Res_n_i, Clk)
variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
begin
if Res_n_i = '0' then
P <= x"00"; -- ensure we have nothing set on reset
elsif Clk'event and Clk = '1' then
tmpP:=P;
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
tmpP:=P_Out;
end if;
end if;
if SaveP = '1' then
tmpP:=P_Out;
end if;
if LDP = '1' then
tmpP:=ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>--0x18(clc)
tmpP(Flag_C) := '0';
when "001" =>--0x38(sec)
tmpP(Flag_C) := '1';
when "010" =>--0x58(cli)
tmpP(Flag_I) := '0';
when "011" =>--0x78(sei)
tmpP(Flag_I) := '1';
when "101" =>--0xb8(clv)
tmpP(Flag_V) := '0';
when "110" =>--0xd8(cld)
tmpP(Flag_D) := '0';
when "111" =>--0xf8(sed)
tmpP(Flag_D) := '1';
when others =>
end case;
end if;
tmpP(Flag_B) := '1';
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
--This should happen after P has been pushed to stack
tmpP(Flag_I) := '1';
end if;
if RstCycle = '1' then
tmpP(Flag_I) := '1';
tmpP(Flag_D) := '0';
end if;
tmpP(Flag_1) := '1';
P<=tmpP;--new way
end if;
-- detect irq even if not rdy
if IR(4 downto 0)/="10000" or Jump/="01" or really_rdy = '0' then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
IRQ_n_o <= IRQ_n;
end if;
-- detect nmi even if not rdy
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
NMI_n_o <= NMI_n;
end if;
end if;
-- act immediately on SO pin change
-- The signal is sampled on the trailing edge of phi1 and must be externally synchronized (from datasheet)
SO_n_o <= SO_n;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
BusB_r <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
NMI_entered <= '0';
BusA_r <= BusA;
BusB <= DI;
-- not really nice, but no better way found yet !
if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
end if;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
-- Handle quirks with some undocumented opcodes crossing page boundary
case BAQuirk is
when "00" => BAH <= std_logic_vector(unsigned(BAH) + 1); -- no quirk
when "01" => BAH <= std_logic_vector(unsigned(BAH) + 1) and DO_r;
when "10" => BAH <= DO_r;
when others => null;
end case;
end if;
when others =>
end case;
-- modified to use Y register as well
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
BAL(2 downto 0) <= "010";
if MCycle="100" then
NMI_entered <= '1';
end if;
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = Set_Addr_To_BA then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <=
DI when Set_BusA_To_DI,
ABC(7 downto 0) when Set_BusA_To_ABC,
X(7 downto 0) when Set_BusA_To_X,
Y(7 downto 0) when Set_BusA_To_Y,
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
P when Set_BusA_To_P,
ABC(7 downto 0) and DI when Set_BusA_To_DA,
(ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
(ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
with Set_Addr_To_r select
A <=
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP,
DBR & "00000000" & AD when Set_Addr_To_ZPG,
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
-- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
DO <= DO_r;
with Write_Data_r select
DO_r <=
DL when Write_Data_DL,
ABC(7 downto 0) when Write_Data_ABC,
X(7 downto 0) when Write_Data_X,
Y(7 downto 0) when Write_Data_Y,
std_logic_vector(S(7 downto 0)) when Write_Data_S,
PwithB when Write_Data_P,
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX,
ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n_i, Clk)
begin
if Res_n_i = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
NMICycle <= '1';
NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
--detect NMI even if not rdy
if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
NMIAct <= '1';
end if;
-- we entered NMI during BRK instruction
if NMI_entered='1' then
NMIAct <= '0';
end if;
end if;
end if;
end process;
end;

294
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@ -0,0 +1,294 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_ALU.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
BCD_en : in std_logic;
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
signal SBX_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
variable CT : std_logic;
begin
CT:='0';
if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set
Op=ALU_OP_ADC or --"0011"
Op=ALU_OP_EQ2 or --"0101"
Op=ALU_OP_SBC or --"0111"
Op=ALU_OP_ROL or --"1001"
Op=ALU_OP_ROR or --"1011"
-- Op=ALU_OP_EQ3 or --"1101"
Op=ALU_OP_INC --"1111"
) then
CT:='1';
end if;
C := P_In(Flag_C) or not CT;--was: or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
if P_In(Flag_D) = '1' and BCD_en = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q, BCD_en)
variable Q_t : std_logic_vector(7 downto 0);
variable Q2_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
Q_t := BusA or BusB;
when ALU_OP_AND=>
Q_t := BusA and BusB;
when ALU_OP_EOR=>
Q_t := BusA xor BusB;
when ALU_OP_ADC=>
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when ALU_OP_CMP=>
P_Out(Flag_C) <= SBC_C;
when ALU_OP_SAX=>
P_Out(Flag_C) <= SBC_C;
Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate)
when ALU_OP_SBC=>
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction
when ALU_OP_ASL=>
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when ALU_OP_ROL=>
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when ALU_OP_LSR=>
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ROR=>
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ARR=>
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
Q2_t := Q_t;
if P_In(Flag_D)='1' and BCD_en = '1' then
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
end if;
if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
P_Out(Flag_C) <= '1';
else
P_Out(Flag_C) <= '0';
end if;
else
P_Out(Flag_C) <= Q_t(6);
end if;
when ALU_OP_BIT=>
P_Out(Flag_V) <= BusB(6);
when ALU_OP_DEC=>
Q_t := std_logic_vector(unsigned(BusA) - 1);
when ALU_OP_INC=>
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
null;
--EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
end case;
case Op is
when ALU_OP_ADC=>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when ALU_OP_EQ1=>--dont touch P
when ALU_OP_BIT=>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when ALU_OP_ANC=>
P_Out(Flag_N) <= Q_t(7);
P_Out(Flag_C) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
if Op=ALU_OP_ARR then
-- handled above in ARR code
Q <= Q2_t;
else
Q <= Q_t;
end if;
end process;
end;

1265
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rtl/T65/T65_Pack.vhd Normal file
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@ -0,0 +1,180 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
subtype T_Lcycle is std_logic_vector(2 downto 0);
constant Cycle_sync :T_Lcycle:="000";
constant Cycle_1 :T_Lcycle:="001";
constant Cycle_2 :T_Lcycle:="010";
constant Cycle_3 :T_Lcycle:="011";
constant Cycle_4 :T_Lcycle:="100";
constant Cycle_5 :T_Lcycle:="101";
constant Cycle_6 :T_Lcycle:="110";
constant Cycle_7 :T_Lcycle:="111";
function CycleNext(c:T_Lcycle) return T_Lcycle;
type T_Set_BusA_To is
(
Set_BusA_To_DI,
Set_BusA_To_ABC,
Set_BusA_To_X,
Set_BusA_To_Y,
Set_BusA_To_S,
Set_BusA_To_P,
Set_BusA_To_DA,
Set_BusA_To_DAO,
Set_BusA_To_DAX,
Set_BusA_To_AAX,
Set_BusA_To_DONTCARE
);
type T_Set_Addr_To is
(
Set_Addr_To_PBR,
Set_Addr_To_SP,
Set_Addr_To_ZPG,
Set_Addr_To_BA
);
type T_Write_Data is
(
Write_Data_DL,
Write_Data_ABC,
Write_Data_X,
Write_Data_Y,
Write_Data_S,
Write_Data_P,
Write_Data_PCL,
Write_Data_PCH,
Write_Data_AX,
Write_Data_AXB,
Write_Data_XB,
Write_Data_YB,
Write_Data_DONTCARE
);
type T_ALU_OP is
(
ALU_OP_OR, --"0000"
ALU_OP_AND, --"0001"
ALU_OP_EOR, --"0010"
ALU_OP_ADC, --"0011"
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
ALU_OP_CMP, --"0110"
ALU_OP_SBC, --"0111"
ALU_OP_ASL, --"1000"
ALU_OP_ROL, --"1001"
ALU_OP_LSR, --"1010"
ALU_OP_ROR, --"1011"
ALU_OP_BIT, --"1100"
-- ALU_OP_EQ3, --"1101"
ALU_OP_DEC, --"1110"
ALU_OP_INC, --"1111"
ALU_OP_ARR,
ALU_OP_ANC,
ALU_OP_SAX,
ALU_OP_XAA
-- ALU_OP_UNDEF--"----"--may be replaced with any?
);
type T_t65_dbg is record
I : std_logic_vector(7 downto 0); -- instruction
A : std_logic_vector(7 downto 0); -- A reg
X : std_logic_vector(7 downto 0); -- X reg
Y : std_logic_vector(7 downto 0); -- Y reg
S : std_logic_vector(7 downto 0); -- stack pointer
P : std_logic_vector(7 downto 0); -- processor flags
end record;
end;
package body T65_Pack is
function CycleNext(c:T_Lcycle) return T_Lcycle is
begin
case(c) is
when Cycle_sync=>
return Cycle_1;
when Cycle_1=>
return Cycle_2;
when Cycle_2=>
return Cycle_3;
when Cycle_3=>
return Cycle_4;
when Cycle_4=>
return Cycle_5;
when Cycle_5=>
return Cycle_6;
when Cycle_6=>
return Cycle_7;
when Cycle_7=>
return Cycle_sync;
when others=>
return Cycle_sync;
end case;
end CycleNext;
end T65_Pack;

111
rtl/apple1.v
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@ -24,6 +24,7 @@
module apple1(
input reset, // reset
input fpga_reset, // fpga reset for one-time reset of display and keyboard
input sys_clock, // system clock
input pixel_clken, // 7 MHz pixel clock
@ -40,7 +41,7 @@ module apple1(
input ps2_clk, // PS/2 keyboard serial clock input
input ps2_din, // PS/2 keyboard serial data input
// interrupt signa
// interrupt signal
input INT_n,
// video outputs
@ -48,7 +49,7 @@ module apple1(
output vga_v_sync, // vertical sync pulse
output [5:0] vga_red, // red signal
output [5:0] vga_grn, // green signal
output [5:0] vga_blu, // blue signal
output [5:0] vga_blu, // blue signal
output reset_key, // keyboard shortcut for reset
output poweroff_key // keyboard shortcut for poweroff/on
@ -69,30 +70,55 @@ module apple1(
//////////////////////////////////////////////////////////////////////////
// 6502
arlet_6502 arlet_6502(
.clk (sys_clock),
.enable (cpu_clken),
.rst (reset),
.ab (addr),
.dbi (cpu_din),
.dbo (cpu_dout),
.we (we),
.irq_n (INT_n),
.nmi_n (1'b1),
.ready (cpu_clken)
);
wire R_W_n; // 1=read, 0=write
assign we = ~R_W_n;
// for debugging T65
wire [63:0] T65_regs;
wire [15:0] T65_A = T65_regs[ 7: 0];
wire [15:0] T65_X = T65_regs[15: 8];
wire [15:0] T65_Y = T65_regs[23:16];
wire [15:0] T65_P = T65_regs[31:24];
wire [15:0] T65_SP = T65_regs[39:32];
wire [23:0] T65_PC = T65_regs[63:40];
T65 T65(
.Mode(2'b00), // "00" => 6502, "01" => 65C02, "10" => 65C816
.Res_n(~reset),
.Enable(cpu_clken),
.Clk(sys_clock),
.Rdy(cpu_clken),
.IRQ_n(INT_n),
.NMI_n(1'b1),
.R_W_n(R_W_n),
.A(addr),
.DI(R_W_n == 0 ? cpu_dout : cpu_din), // T65 requires cpu_dout feed back in
.DO(cpu_dout),
.Regs(T65_regs)
);
//////////////////////////////////////////////////////////////////////////
// Address Decoding
wire keyboard_cs = (addr[15:1] == 15'b110100000001000); // 0xD010 -> 0xD011
wire display_cs = (addr[15:1] == 15'b110100000001001); // 0xD012 -> 0xD013
wire ram_cs = !keyboard_cs & !display_cs;
wire debug_cs = addr >= 16'hF000 && addr <= 16'hF007;
wire [7:0] debug_dout = addr[7:0] == 0 ? T65_A : // A regs[ 7: 0]
addr[7:0] == 1 ? T65_X : // X regs[15: 8]
addr[7:0] == 2 ? T65_Y : // Y regs[23:16]
addr[7:0] == 3 ? T65_P : // P regs[31:24]
addr[7:0] == 4 ? T65_SP : // SP regs[39:32]
addr[7:0] == 5 ? T65_PC[ 7: 0] : // PC regs[47:40]
addr[7:0] == 6 ? T65_PC[15: 8] : // PC regs[55:48]
addr[7:0] == 7 ? T65_PC[23:16] : 8'hAA; // PC regs[63:56]
// byte returned from display out
wire [7:0] display_dout = { ~PB7, 7'b0 };
wire [6:0] dsp_dout;
wire [7:0] display_dout = { ~PB7, dsp_dout };
//////////////////////////////////////////////////////////////////////////
// Peripherals
@ -101,7 +127,7 @@ module apple1(
wire cls_key;
ps2keyboard keyboard(
.clk(sys_clock),
.rst(reset),
.rst(fpga_reset),
.key_clk(ps2_clk),
.key_din(ps2_din),
.cs(keyboard_cs),
@ -114,7 +140,7 @@ module apple1(
wire PB7; // (negated) display ready (PB7 of CIA)
display display(
.reset(reset),
.reset(fpga_reset),
.sys_clock(sys_clock),
.pixel_clken(pixel_clken),
@ -128,7 +154,8 @@ module apple1(
.address(addr[0]),
.w_en(we & display_cs),
.din(cpu_dout),
.din(cpu_dout),
.dout(dsp_dout),
.clr_screen(cls_key),
.ready(PB7)
);
@ -137,8 +164,44 @@ module apple1(
// CPU Data In MUX
// link up chip selected device to cpu input
assign cpu_din = display_cs ? display_dout :
assign cpu_din = debug_cs ? debug_dout :
display_cs ? display_dout :
keyboard_cs ? ps2_dout :
ram_cs ? ram_dout :
ram_cs ? ram_dout :
8'hFF;
/*
wire pia_cs = cpu_clken & keyboard_cs;
wire [7:0] pia_dout;
wire kbd_strobe;
pia6821 pia6821(
.clk(sys_clock), // : in std_logic;
.rst(reset), // : in std_logic;
.cs(pia_cs), // : in std_logic;
.rw(R_W_n), // : in std_logic; 1=read, 0=write
.addr(addr[1:0]), // : in std_logic_vector(1 downto 0);
.data_in(cpu_dout), // : in std_logic_vector(7 downto 0);
.data_out(pia_dout), // : out std_logic_vector(7 downto 0);
//.irqa // : out std_logic;
//.irqb // : out std_logic;
.pa_i(ps2_dout), // : in std_logic_vector(7 downto 0);
//.pa_o // : out std_logic_vector(7 downto 0);
//.pa_oe // : out std_logic_vector(7 downto 0);
.ca1(kbd_strobe) // : in std_logic;
//.ca2_i // : in std_logic;
//.ca2_o // : out std_logic;
//.ca2_oe // : out std_logic;
//pb_i : in std_logic_vector(7 downto 0);
//pb_o : out std_logic_vector(7 downto 0);
//pb_oe : out std_logic_vector(7 downto 0);
//cb1 : in std_logic;
//cb2_i : in std_logic;
//cb2_o : out std_logic;
//cb2_oe : out std_logic
);
*/
endmodule

158
rtl/apple1_mist.sv
View File

@ -4,13 +4,13 @@
//
// TODO make roms loadable
// TODO use a CPU that allows illegal instructions
// TODO sdram downloader error
// TODO power on-off key ? init ram with values
// TODO ram powerup initial values
// TODO reorganize file structure
// TODO A-F chip selection banks?
// TODO check diff with updated data_io.v and other modules
// TODO keyboard: use a PIA
// TODO keyboard: implement PIA 6820(1)
// TODO keyboard: isolate ps2 keyboard from apple1
// TODO keyboard: check ps2 clock
// TODO keyboard: make a true ascii keyboard
@ -19,7 +19,7 @@
// TODO display: check NTSC AD724 hsync problem (yellow menu doesn't work)
// TODO display: reduce to 512 bytes font
// TODO display: check parameters vs real apple1
// TODO display: emulate PIA registers
// TODO display: implement PIA 6820(1)
// TODO tms9918: fix video sync on composite and mist_video
// TODO tms9918: make it selectable via keyboard
// TODO sid: unsigned vs signed dac ?
@ -81,6 +81,7 @@ localparam CONF_STR = {
"O2,TMS9918 output,Off,On;",
`endif
"O3,Audio monitor,tape in,tape out;",
"O4,SDRAM at $4000,off,on;",
"T6,Reset;",
"V,",`BUILD_DATE
`ifdef USE_SID
@ -91,6 +92,12 @@ localparam CONF_STR = {
`endif
};
`ifdef USE_TMS
localparam BLOCKRAM_SIZE = 'h7000;
`else
localparam BLOCKRAM_SIZE = 'hC000;
`endif
localparam conf_str_len = $size(CONF_STR)>>3;
wire st_reset_switch = buttons[1];
@ -102,6 +109,7 @@ wire [1:0] switches;
wire st_tms9918_output = status[2];
wire st_audio_mon_tape_in = ~status[3];
wire st_menu_reset = status[6];
wire st_sdram_expansion = status[4];
wire scandoubler_disable;
wire ypbpr;
@ -110,7 +118,7 @@ wire no_csync;
wire ps2_kbd_clk;
wire ps2_kbd_data;
wire reset_button = status[0] | st_menu_reset | st_reset_switch | reset_key_edge |!pll_locked;
wire reset_button = status[0] | st_menu_reset | st_reset_switch | reset_key_edge | !pll_locked;
/******************************************************************************************/
/******************************************************************************************/
@ -119,10 +127,17 @@ wire reset_button = status[0] | st_menu_reset | st_reset_switch | reset_key_edge
/******************************************************************************************/
wire pll_locked;
wire fpga_reset = ~pll_locked;
wire sys_clock; // cpu x 7 x 8 system clock (sdram.v)
wire osd_clock; // cpu x 7 x 2 for the OSD menu
//wire F7M_clock; // cpu x 7 (SDRAM/8) for downloader
`ifdef USE_TMS
wire vdp_clock; // tms9918 x 2 for osd menu
`endif
assign SDRAM_CLK = sys_clock;
pll pll
(
@ -130,9 +145,12 @@ pll pll
.locked(pll_locked),
.c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu
//.c1( F7M_clock ), // cpu x 7 (SDRAM/8) for downloader
.c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v)
.c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns
// .c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns
`ifdef USE_TMS
.c4( vdp_clock ) // tms9918 x 2 for osd menu (10.738635 x 2 = 21.47727)
`endif
);
/******************************************************************************************/
@ -185,12 +203,12 @@ downloader
wire [7:0] ram_dout;
// low system RAM
ram #(.SIZE(16384)) ram(
// low system RAM
ram #(.SIZE(BLOCKRAM_SIZE)) ram(
.clk (sys_clock ),
.address(sdram_addr[15:0]),
.w_en (sdram_wr & ram_cs),
.din (sdram_din ),
.address(bus_addr[15:0]),
.w_en (bus_wr & ram_cs),
.din (bus_din ),
.dout (ram_dout )
);
@ -207,9 +225,9 @@ rom_wozmon rom_wozmon(
wire [7:0] basic_dout;
ram #(.SIZE(4096)) rom_basic(
.clk(sys_clock),
.address({4'b000, sdram_addr[11:0]}),
.w_en (sdram_wr & basic_cs),
.din (sdram_din ),
.address({4'b000, bus_addr[11:0]}),
.w_en (bus_wr & basic_cs),
.din (bus_din ),
.dout (basic_dout)
);
@ -224,10 +242,10 @@ wire CASOUT;
ACI ACI(
.clk(sys_clock),
.cpu_clken(cpu_clken),
.addr(sdram_addr[15:0]),
.addr(bus_addr[15:0]),
.dout(aci_dout),
.tape_in(CASIN),
.tape_out(CASOUT),
.tape_out(CASOUT)
);
// latches cassette audio input
@ -265,52 +283,31 @@ end
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @apple1 ****************************************/
/***************************************** @bus *******************************************/
/******************************************************************************************/
/******************************************************************************************/
// SDRAM control signals
// bus control signals
wire [24:0] sdram_addr;
wire [7:0] sdram_din;
wire sdram_wr;
wire sdram_rd;
wire [7:0] sdram_dout;
wire [24:0] bus_addr;
wire [7:0] bus_din;
wire bus_wr;
wire bus_rd;
always @(posedge sys_clock) begin
if(is_downloading && download_wr) begin
sdram_addr <= download_addr;
sdram_din <= download_data;
sdram_wr <= download_wr;
sdram_rd <= 1'b1;
end
else begin
sdram_addr <= { 9'b0, cpu_addr[15:0] };
sdram_din <= cpu_dout;
sdram_wr <= cpu_wr;
sdram_rd <= 1'b1;
end
end
assign bus_addr = (is_downloading && download_wr) ? download_addr : { 9'b0, cpu_addr[15:0] };
assign bus_din = (is_downloading && download_wr) ? download_data : cpu_dout;
assign bus_wr = (is_downloading && download_wr) ? download_wr : cpu_wr;
assign bus_rd = (is_downloading && download_wr) ? 1'b1 : 1'b1; // TODO provare !wr ??
wire dummy = is_downloading && download_wr;
assign LED = ~dummy;
// ram interface
wire [15:0] cpu_addr;
wire [7:0] cpu_dout;
wire cpu_rd;
wire cpu_wr;
wire ram_cs = sdram_addr < 'h4000; // 0x0000 -> 0x3FFF
wire sdram_cs = sdram_addr >= 'h4000 && sdram_addr <= 'hBFFF; // 0x4000 -> 0xBFFF
wire aci_cs = sdram_addr >= 'hC000 && sdram_addr <= 'hC1FF; // 0xC000 -> 0xC1FF
wire basic_cs = sdram_addr >= 'hE000 && sdram_addr <= 'hEFFF; // 0xE000 -> 0xEFFF
wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFFF
wire ram_cs = bus_addr <= st_sdram_expansion ? 'h3FFF : 'hBFFF ;
wire sdram_cs = st_sdram_expansion ? bus_addr >= 'h4000 && bus_addr <= 'hBFFF : 0;
wire aci_cs = bus_addr >= 'hC000 && bus_addr <= 'hC1FF;
wire basic_cs = bus_addr >= 'hE000 && bus_addr <= 'hEFFF;
wire rom_cs = bus_addr >= 'hFF00;
// experimental SID 6561
`ifdef USE_SID
wire sid_cs = sdram_addr >= 'hC800 && sdram_addr <= 'hC8FF; // 0xC800 -> 0xC8FF
wire sid_cs = bus_addr >= 'hC800 && bus_addr <= 'hC8FF; // 0xC800 -> 0xC8FF
`else
wire sid_cs = 0;
wire sid_dout = 0;
@ -318,7 +315,7 @@ wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFF
// experimental TMS9918
`ifdef USE_TMS
wire tms_cs = sdram_addr >= 'hCC00 && sdram_addr <= 'hCC01; // 0xCC00 -> 0xCC01
wire tms_cs = bus_addr >= 'hCC00 && bus_addr <= 'hCC01; // 0xCC00 -> 0xCC01
`else
wire tms_cs = 0;
wire vdp_dout = 0;
@ -332,6 +329,12 @@ wire [7:0] bus_dout = rom_cs ? rom_dout :
sdram_cs ? sdram_dout :
ram_cs ? ram_dout :
8'b0;
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @apple1 ****************************************/
/******************************************************************************************/
/******************************************************************************************/
wire reset_key;
wire poweroff_key;
@ -348,10 +351,16 @@ reg reset_key_old = 0;
always @(posedge sys_clock) begin
reset_key_old <= reset_key;
end
wire [15:0] cpu_addr;
wire [7:0] cpu_dout;
wire cpu_rd;
wire cpu_wr;
apple1 apple1
(
.reset(reset_button),
.fpga_reset(fpga_reset),
.sys_clock ( sys_clock ), // system clock
.cpu_clken ( cpu_clken & ~is_downloading ), // CPU clock enable
@ -381,8 +390,8 @@ apple1 apple1
.vga_grn(g),
.vga_blu(b),
.vga_cls(), // clear screen button (not connected yet)
.vga_cls(), // clear screen button (not connected yet)
.reset_key(reset_key), // keyboard shortcut for reset
.poweroff_key(poweroff_key) // keyboard shortcut for power off/on
);
@ -546,6 +555,8 @@ user_io (
/***************************************** @sdram *****************************************/
/******************************************************************************************/
/******************************************************************************************/
wire [7:0] sdram_dout;
// SDRAM control signals
assign SDRAM_CKE = 1'b1;
@ -567,11 +578,11 @@ sdram sdram (
.init ( !pll_locked ),
// cpu interface
.din ( sdram_din ),
.addr ( sdram_addr ),
.we ( sdram_wr ),
.oe ( sdram_rd ),
.dout ( sdram_dout )
.din ( bus_din ),
.addr ( bus_addr ),
.we ( bus_wr ),
.oe ( bus_rd ),
.dout ( sdram_dout )
);
/******************************************************************************************/
@ -587,7 +598,7 @@ wire cpu_clock; // cpu clock for the sdram controller sync
clock clock(
.sys_clock ( sys_clock ), // input: main clock
.reset ( reset_button ), // input: reset signal
.reset ( fpga_reset ), // input: reset signal
.cpu_clock ( cpu_clock ),
.cpu_clken ( cpu_clken ), // output: cpu clock enable (phi2)
@ -595,6 +606,17 @@ clock clock(
.pixel_clken ( pixel_clken ) // output: pixel clock enable
);
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @led *******************************************/
/******************************************************************************************/
/******************************************************************************************/
wire dummy = is_downloading && download_wr;
assign LED = ~dummy;
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @vdp *******************************************/
@ -625,8 +647,8 @@ always @(posedge vdp_clock) begin
vdp_ena <= ~vdp_ena;
end
wire csr = tms_cs & sdram_rd;
wire csw = tms_cs & sdram_wr;
wire csr = tms_cs & bus_rd;
wire csw = tms_cs & bus_wr;
wire tms_HS;
wire tms_VS;
@ -654,11 +676,11 @@ tms9918
// control signals
.csr_n ( ~csr ),
.csw_n ( ~csw ),
.mode ( sdram_addr[0] ),
.mode ( bus_addr[0] ),
.int_n ( VDP_INT_n ),
// cpu I/O
.cd_i ( sdram_din ),
.cd_i ( bus_din ),
.cd_o ( vdp_dout ),
// vram
@ -693,9 +715,9 @@ sid_top sid_top
.clock(sys_clock),
.reset(reset_button),
.addr(sdram_addr[7:0]),
.addr(bus_addr[7:0]),
.wren(cpu_wr & sid_cs),
.wdata(sdram_din),
.wdata(bus_din),
.rdata(sid_dout),
.potx(0),

108
rtl/arlet_6502/ALU.v
View File

@ -1,108 +0,0 @@
/*
* ALU.
*
* AI and BI are 8 bit inputs. Result in OUT.
* CI is Carry In.
* CO is Carry Out.
*
* op[3:0] is defined as follows:
*
* 0011 AI + BI
* 0111 AI - BI
* 1011 AI + AI
* 1100 AI | BI
* 1101 AI & BI
* 1110 AI ^ BI
* 1111 AI
*
*/
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule

72
rtl/arlet_6502/arlet_6502.v
View File

@ -1,72 +0,0 @@
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//
// Description: A wrapper for Arlet Ottens 6502 CPU core
//
// Author.....: Alan Garfield
// Niels A. Moseley
// Date.......: 26-1-2018
//
module arlet_6502(
input clk, // clock signal
input enable, // clock enable strobe
input rst, // active high reset signal
output reg [15:0] ab, // address bus
input [7:0] dbi, // 8-bit data bus (input)
output reg [7:0] dbo, // 8-bit data bus (output)
output reg we, // active high write enable strobe
input irq_n, // active low interrupt request
input nmi_n, // active low non-maskable interrupt
input ready, // CPU updates when ready = 1
output [15:0] pc_monitor // program counter monitor signal for debugging
);
wire [7:0] dbo_c;
wire [15:0] ab_c;
wire we_c;
cpu arlet_cpu(
.clk(clk),
.reset(rst),
.AB(ab_c),
.DI(dbi),
.DO(dbo_c),
.WE(we_c),
.IRQ(~irq_n),
.NMI(~nmi_n),
.RDY(ready),
.PC_MONITOR(pc_monitor)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
ab <= 16'd0;
dbo <= 8'd0;
we <= 1'b0;
end
else
if (enable)
begin
ab <= ab_c;
dbo <= dbo_c;
we <= we_c;
end
end
endmodule

66
rtl/arlet_6502/chip_6502.v
View File

@ -1,66 +0,0 @@
`include "../rtl/cpu/aholme/chip_6502_nodes.inc"
module LOGIC (
input [`NUM_NODES-1:0] i,
output [`NUM_NODES-1:0] o);
`include "chip_6502_logic.inc"
endmodule
module chip_6502 (
input clk, // FPGA clock
input phi, // 6502 clock
input res,
input so,
input rdy,
input nmi,
input irq,
input [7:0] dbi,
output [7:0] dbo,
output rw,
output sync,
output [15:0] ab);
// Node states
wire [`NUM_NODES-1:0] no;
reg [`NUM_NODES-1:0] ni;
reg [`NUM_NODES-1:0] q = 0;
LOGIC logic_00 (.i(ni), .o(no));
always @ (posedge clk)
q <= no;
always @* begin
ni = q;
ni[`NODE_vcc ] = 1'b1;
ni[`NODE_vss ] = 1'b0;
ni[`NODE_res ] = res;
ni[`NODE_clk0] = phi;
ni[`NODE_so ] = so;
ni[`NODE_rdy ] = rdy;
ni[`NODE_nmi ] = nmi;
ni[`NODE_irq ] = irq;
{ni[`NODE_db7],ni[`NODE_db6],ni[`NODE_db5],ni[`NODE_db4],
ni[`NODE_db3],ni[`NODE_db2],ni[`NODE_db1],ni[`NODE_db0]} = dbi[7:0];
end
assign dbo[7:0] = {
no[`NODE_db7],no[`NODE_db6],no[`NODE_db5],no[`NODE_db4],
no[`NODE_db3],no[`NODE_db2],no[`NODE_db1],no[`NODE_db0]
};
assign ab[15:0] = {
no[`NODE_ab15], no[`NODE_ab14], no[`NODE_ab13], no[`NODE_ab12],
no[`NODE_ab11], no[`NODE_ab10], no[`NODE_ab9], no[`NODE_ab8],
no[`NODE_ab7], no[`NODE_ab6], no[`NODE_ab5], no[`NODE_ab4],
no[`NODE_ab3], no[`NODE_ab2], no[`NODE_ab1], no[`NODE_ab0]
};
assign rw = no[`NODE_rw];
assign sync = no[`NODE_sync];
endmodule

10
rtl/arlet_6502/chip_6502_mux.v
View File

@ -1,10 +0,0 @@
module MUX #(
parameter N=1
) (
output wire o,
input wire i,
input wire [N-1:0] s,
input wire [N-1:0] d);
assign o = (|s) ? &(d|(~s)) : i;
endmodule

1244
rtl/arlet_6502/cpu.v
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File diff suppressed because it is too large Load Diff

6
rtl/display.v
View File

@ -19,7 +19,8 @@ module display (
// cpu interface
input address, // address bus
input w_en, // active high write enable strobe
input [7:0] din // 8-bit data bus (input)
input [7:0] din, // 8-bit data bus (input)
output reg [6:0] dout // input data is also seen as output
);
//////////////////////////////////////////////////////////////////////////
@ -254,7 +255,8 @@ module display (
if (address == 1'b0) begin
if (cpu_clken & w_en & ready) begin
// incoming character
ready <= 0;
ready <= 0;
dout[6:0] <= din[6:0];
if(din[6:0]=='h0D) begin
// handle carriage return

553
rtl/pia6821/pia6821.vhd Normal file
View File

@ -0,0 +1,553 @@
--===========================================================================--
--
-- S Y N T H E Z I A B L E I/O Port C O R E
--
-- www.OpenCores.Org - May 2004
-- This core adheres to the GNU public license
--
-- File name : pia6821.vhd
--
-- Purpose : Implements 2 x 8 bit parallel I/O ports
-- with programmable data direction registers
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 1 May 2004 0.0 John Kent
-- Initial version developed from ioport.vhd
--
--
-- Unkown date 0.0.1 found at Pacedev repository
-- remove High Z output and and oe signal
--
-- 18 October 2017 0.0.2 DarFpga
-- Set output to low level when in data is in input mode
-- (to avoid infered latch warning)
--
--===========================================================================----
--
-- Memory Map
--
-- IO + $00 - Port A Data & Direction register
-- IO + $01 - Port A Control register
-- IO + $02 - Port B Data & Direction Direction Register
-- IO + $03 - Port B Control Register
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pia6821 is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irqa : out std_logic;
irqb : out std_logic;
pa_i : in std_logic_vector(7 downto 0);
pa_o : out std_logic_vector(7 downto 0);
pa_oe : out std_logic_vector(7 downto 0);
ca1 : in std_logic;
ca2_i : in std_logic;
ca2_o : out std_logic;
ca2_oe : out std_logic;
pb_i : in std_logic_vector(7 downto 0);
pb_o : out std_logic_vector(7 downto 0);
pb_oe : out std_logic_vector(7 downto 0);
cb1 : in std_logic;
cb2_i : in std_logic;
cb2_o : out std_logic;
cb2_oe : out std_logic
);
end;
architecture pia_arch of pia6821 is
signal porta_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal porta_ctrl : std_logic_vector(5 downto 0);
signal porta_read : std_logic;
signal portb_ddr : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
signal portb_ctrl : std_logic_vector(5 downto 0);
signal portb_read : std_logic;
signal portb_write : std_logic;
signal ca1_del : std_logic;
signal ca1_rise : std_logic;
signal ca1_fall : std_logic;
signal ca1_edge : std_logic;
signal irqa1 : std_logic;
signal ca2_del : std_logic;
signal ca2_rise : std_logic;
signal ca2_fall : std_logic;
signal ca2_edge : std_logic;
signal irqa2 : std_logic;
signal ca2_out : std_logic;
signal cb1_del : std_logic;
signal cb1_rise : std_logic;
signal cb1_fall : std_logic;
signal cb1_edge : std_logic;
signal irqb1 : std_logic;
signal cb2_del : std_logic;
signal cb2_rise : std_logic;
signal cb2_fall : std_logic;
signal cb2_edge : std_logic;
signal irqb2 : std_logic;
signal cb2_out : std_logic;
begin
--------------------------------
--
-- read I/O port
--
--------------------------------
pia_read : process( addr, cs,
irqa1, irqa2, irqb1, irqb2,
porta_ddr, portb_ddr,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
pa_i, pb_i )
variable count : integer;
begin
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ctrl(2) = '0' then
data_out(count) <= porta_ddr(count);
porta_read <= '0';
else
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= pa_i(count);
end if;
porta_read <= cs;
end if;
end loop;
portb_read <= '0';
when "01" =>
data_out <= irqa1 & irqa2 & porta_ctrl;
porta_read <= '0';
portb_read <= '0';
when "10" =>
for count in 0 to 7 loop
if portb_ctrl(2) = '0' then
data_out(count) <= portb_ddr(count);
portb_read <= '0';
else
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= pb_i(count);
end if;
portb_read <= cs;
end if;
end loop;
porta_read <= '0';
when "11" =>
data_out <= irqb1 & irqb2 & portb_ctrl;
porta_read <= '0';
portb_read <= '0';
when others =>
data_out <= "00000000";
porta_read <= '0';
portb_read <= '0';
end case;
end process;
---------------------------------
--
-- Write I/O ports
--
---------------------------------
pia_write : process( clk, rst, addr, cs, rw, data_in,
porta_ctrl, portb_ctrl,
porta_data, portb_data,
porta_ddr, portb_ddr )
begin
if rst = '1' then
porta_ddr <= "00000000";
porta_data <= "00000000";
porta_ctrl <= "000000";
portb_ddr <= "00000000";
portb_data <= "00000000";
portb_ctrl <= "000000";
portb_write <= '0';
elsif clk'event and clk = '1' then
if cs = '1' and rw = '0' then
case addr is
when "00" =>
if porta_ctrl(2) = '0' then
porta_ddr <= data_in;
porta_data <= porta_data;
else
porta_ddr <= porta_ddr;
porta_data <= data_in;
end if;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "01" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= data_in(5 downto 0);
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "10" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
if portb_ctrl(2) = '0' then
portb_ddr <= data_in;
portb_data <= portb_data;
portb_write <= '0';
else
portb_ddr <= portb_ddr;
portb_data <= data_in;
portb_write <= '1';
end if;
portb_ctrl <= portb_ctrl;
when "11" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= data_in(5 downto 0);
portb_write <= '0';
when others =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end case;
else
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_data <= portb_data;
portb_ddr <= portb_ddr;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end if;
end if;
end process;
---------------------------------
--
-- direction control port a
--
---------------------------------
porta_direction : process ( porta_data, porta_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
pa_o(count) <= porta_data(count);
pa_oe(count) <= '1';
else
pa_o(count) <= '0';
pa_oe(count) <= '0';
end if;
end loop;
end process;
---------------------------------
--
-- CA1 Edge detect
--
---------------------------------
ca1_input : process( clk, rst, ca1, ca1_del,
ca1_rise, ca1_fall, ca1_edge,
irqa1, porta_ctrl, porta_read )
begin
if rst = '1' then
ca1_del <= '0';
ca1_rise <= '0';
ca1_fall <= '0';
ca1_edge <= '0';
irqa1 <= '0';
elsif clk'event and clk = '0' then
ca1_del <= ca1;
ca1_rise <= (not ca1_del) and ca1;
ca1_fall <= ca1_del and (not ca1);
if ca1_edge = '1' then
irqa1 <= '1';
elsif porta_read = '1' then
irqa1 <= '0';
else
irqa1 <= irqa1;
end if;
end if;
if porta_ctrl(1) = '0' then
ca1_edge <= ca1_fall;
else
ca1_edge <= ca1_rise;
end if;
end process;
---------------------------------
--
-- CA2 Edge detect
--
---------------------------------
ca2_input : process( clk, rst, ca2_i, ca2_del,
ca2_rise, ca2_fall, ca2_edge,
irqa2, porta_ctrl, porta_read )
begin
if rst = '1' then
ca2_del <= '0';
ca2_rise <= '0';
ca2_fall <= '0';
ca2_edge <= '0';
irqa2 <= '0';
elsif clk'event and clk = '0' then
ca2_del <= ca2_i;
ca2_rise <= (not ca2_del) and ca2_i;
ca2_fall <= ca2_del and (not ca2_i);
if porta_ctrl(5) = '0' and ca2_edge = '1' then
irqa2 <= '1';
elsif porta_read = '1' then
irqa2 <= '0';
else
irqa2 <= irqa2;
end if;
end if;
if porta_ctrl(4) = '0' then
ca2_edge <= ca2_fall;
else
ca2_edge <= ca2_rise;
end if;
end process;
---------------------------------
--
-- CA2 output control
--
---------------------------------
ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
begin
if rst='1' then
ca2_out <= '0';
elsif clk'event and clk='0' then
case porta_ctrl(5 downto 3) is
when "100" => -- read PA clears, CA1 edge sets
if porta_read = '1' then
ca2_out <= '0';
elsif ca1_edge = '1' then
ca2_out <= '1';
else
ca2_out <= ca2_out;
end if;
when "101" => -- read PA clears, E sets
ca2_out <= not porta_read;
when "110" => -- set low
ca2_out <= '0';
when "111" => -- set high
ca2_out <= '1';
when others => -- no change
ca2_out <= ca2_out;
end case;
end if;
end process;
---------------------------------
--
-- CA2 direction control
--
---------------------------------
ca2_direction : process( porta_ctrl, ca2_out )
begin
if porta_ctrl(5) = '0' then
ca2_oe <= '0';
ca2_o <= '0';
else
ca2_o <= ca2_out;
ca2_oe <= '1';
end if;
end process;
---------------------------------
--
-- direction control port b
--
---------------------------------
portb_direction : process ( portb_data, portb_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
pb_o(count) <= portb_data(count);
pb_oe(count) <= '1';
else
pb_o(count) <= '0';
pb_oe(count) <= '0';
end if;
end loop;
end process;
---------------------------------
--
-- CB1 Edge detect
--
---------------------------------
cb1_input : process( clk, rst, cb1, cb1_del,
cb1_rise, cb1_fall, cb1_edge,
irqb1, portb_ctrl, portb_read )
begin
if rst = '1' then
cb1_del <= '0';
cb1_rise <= '0';
cb1_fall <= '0';
cb1_edge <= '0';
irqb1 <= '0';
elsif clk'event and clk = '0' then
cb1_del <= cb1;
cb1_rise <= (not cb1_del) and cb1;
cb1_fall <= cb1_del and (not cb1);
if cb1_edge = '1' then
irqb1 <= '1';
elsif portb_read = '1' then
irqb1 <= '0';
else
irqb1 <= irqb1;
end if;
end if;
if portb_ctrl(1) = '0' then
cb1_edge <= cb1_fall;
else
cb1_edge <= cb1_rise;
end if;
end process;
---------------------------------
--
-- CB2 Edge detect
--
---------------------------------
cb2_input : process( clk, rst, cb2_i, cb2_del,
cb2_rise, cb2_fall, cb2_edge,
irqb2, portb_ctrl, portb_read )
begin
if rst = '1' then
cb2_del <= '0';
cb2_rise <= '0';
cb2_fall <= '0';
cb2_edge <= '0';
irqb2 <= '0';
elsif clk'event and clk = '0' then
cb2_del <= cb2_i;
cb2_rise <= (not cb2_del) and cb2_i;
cb2_fall <= cb2_del and (not cb2_i);
if portb_ctrl(5) = '0' and cb2_edge = '1' then
irqb2 <= '1';
elsif portb_read = '1' then
irqb2 <= '0';
else
irqb2 <= irqb2;
end if;
end if;
if portb_ctrl(4) = '0' then
cb2_edge <= cb2_fall;
else
cb2_edge <= cb2_rise;
end if;
end process;
---------------------------------
--
-- CB2 output control
--
---------------------------------
cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
begin
if rst='1' then
cb2_out <= '0';
elsif clk'event and clk='0' then
case portb_ctrl(5 downto 3) is
when "100" => -- write PB clears, CA1 edge sets
if portb_write = '1' then
cb2_out <= '0';
elsif cb1_edge = '1' then
cb2_out <= '1';
else
cb2_out <= cb2_out;
end if;
when "101" => -- write PB clears, E sets
cb2_out <= not portb_write;
when "110" => -- set low
cb2_out <= '0';
when "111" => -- set high
cb2_out <= '1';
when others => -- no change
cb2_out <= cb2_out;
end case;
end if;
end process;
---------------------------------
--
-- CB2 direction control
--
---------------------------------
cb2_direction : process( portb_ctrl, cb2_out )
begin
if portb_ctrl(5) = '0' then
cb2_oe <= '0';
cb2_o <= '0';
else
cb2_o <= cb2_out;
cb2_oe <= '1';
end if;
end process;
---------------------------------
--
-- IRQ control
--
---------------------------------
pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
begin
irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
end process;
end pia_arch;

62
rtl/pll.v
View File

@ -40,7 +40,6 @@ module pll (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4,
@ -49,7 +48,6 @@ module pll (
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
@ -63,27 +61,25 @@ module pll (
`endif
wire [4:0] sub_wire0;
wire sub_wire6;
wire [0:0] sub_wire9 = 1'h0;
wire [3:3] sub_wire5 = sub_wire0[3:3];
wire [4:4] sub_wire4 = sub_wire0[4:4];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [0:0] sub_wire2 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire c4 = sub_wire4;
wire c3 = sub_wire5;
wire locked = sub_wire6;
wire sub_wire7 = inclk0;
wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
wire sub_wire2;
wire [0:0] sub_wire8 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [3:3] sub_wire1 = sub_wire0[3:3];
wire c3 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c4 = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire8),
.inclk (sub_wire7),
.clk (sub_wire0),
.locked (sub_wire6),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
@ -123,10 +119,6 @@ module pll (
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 715909,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 2700000,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 715909,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 337500,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 715909,
@ -172,7 +164,7 @@ module pll (
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
@ -213,17 +205,14 @@ endmodule
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "108"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318180"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.159090"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.272720"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "57.272720"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "21.477270"
@ -247,47 +236,39 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.31818000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.15909000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.27272000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "57.27272000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "21.47727000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-2500.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
@ -313,7 +294,6 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
@ -321,12 +301,10 @@ endmodule
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
@ -338,10 +316,6 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "715909"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2700000"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "715909"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "337500"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "715909"
@ -386,7 +360,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
@ -406,7 +380,6 @@ endmodule
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
@ -416,7 +389,6 @@ endmodule
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4

65
rtl/ps2keyboard.v
View File

@ -53,6 +53,7 @@ module ps2keyboard (
reg [7:0] ascii; // ASCII code of received character
reg ascii_rdy; // new ASCII character received
reg shift; // state of the shift key
reg control; // state of the control key
reg [2:0] cur_state;
reg [2:0] next_state;
@ -123,6 +124,7 @@ module ps2keyboard (
rx <= 0;
ascii_rdy <= 0;
shift <= 0;
control <= 0;
cur_state <= S_KEYNORMAL;
/*
@ -180,18 +182,52 @@ module ps2keyboard (
//end
// check for a SHIFT key
if ((rx == 8'h59) || (rx == 8'h12))
begin
if ((rx == 8'h59) || (rx == 8'h12)) begin
shift <= 1'b1;
ascii_rdy <= 1'b0; // shift is not a key!
end
else if(rx == 8'h14) begin
control <= 1'b1;
ascii_rdy <= 1'b0; // control is not a key!
end
else begin
if (!shift)
if(control) begin
case(rx)
8'h45: ascii <= 0; // ctrl+0 = NULL
8'h1C: ascii <= 1;
8'h32: ascii <= 2;
8'h21: ascii <= 3;
8'h23: ascii <= 4;
8'h24: ascii <= 5;
8'h2B: ascii <= 6;
8'h34: ascii <= 7;
8'h33: ascii <= 8;
8'h43: ascii <= 9;
8'h3B: ascii <= 10;
8'h42: ascii <= 11;
8'h4B: ascii <= 12;
8'h3A: ascii <= 13;
8'h31: ascii <= 14;
8'h44: ascii <= 15;
8'h4D: ascii <= 16;
8'h15: ascii <= 17;
8'h2D: ascii <= 18;
8'h1B: ascii <= 19;
8'h2C: ascii <= 20;
8'h3C: ascii <= 21;
8'h2A: ascii <= 22;
8'h1D: ascii <= 23;
8'h22: ascii <= 24;
8'h35: ascii <= 25;
8'h1A: ascii <= 26;
endcase
end
else if (!shift)
case(rx)
8'h05: cls_key <= 1;
8'h03: reset_key <= 1;
8'h01: poweroff_key <= 1;
8'h1C: ascii <= "A";
8'h1C: ascii <= "A"; // TODO wozmon does not handle lowercases?
8'h32: ascii <= "B";
8'h21: ascii <= "C";
8'h23: ascii <= "D";
@ -231,11 +267,16 @@ module ps2keyboard (
8'h4E: ascii <= "-";
8'h55: ascii <= "=";
8'h5D: ascii <= 8'h34; // backslash
8'h66: ascii <= 8'd8; // backspace
8'h29: ascii <= " ";
8'h29: ascii <= " ";
8'h5D: ascii <= 8'd92; // backslash
8'h66: ascii <= 8'd8; // backspace
8'h5A: ascii <= 8'd13; // enter
8'h76: ascii <= 8'd27; // esc
8'h0d: ascii <= 8'd9; // tab
8'h0e: ascii <= 8'd96; // backtick
8'h54: ascii <= "[";
8'h5B: ascii <= "]";
8'h4C: ascii <= ";";
@ -294,10 +335,14 @@ module ps2keyboard (
8'h4E: ascii <= "_";
8'h55: ascii <= "+";
8'h5D: ascii <= "|";
8'h66: ascii <= 8'd8; // backspace
8'h29: ascii <= " ";
8'h66: ascii <= 8'd8; // backspace
8'h5A: ascii <= 8'd13; // enter
8'h76: ascii <= 8'd27; // esc
8'h0d: ascii <= 8'd9; // tab
8'h0e: ascii <= "~";
8'h54: ascii <= "{";
8'h5B: ascii <= "}";
8'h4C: ascii <= ":";
@ -319,8 +364,8 @@ module ps2keyboard (
// when we end up here, a 0xF0 byte was received
// which usually means a key release event
begin
if ((rx == 8'h59) || (rx == 8'h12))
shift <= 1'b0;
if ((rx == 8'h59) || (rx == 8'h12)) shift <= 1'b0;
if (rx == 8'h14) control <= 1'b0;
next_state = S_KEYNORMAL;
cls_key <= 0;
reset_key <= 0;