Commit Graph

168 Commits

Author SHA1 Message Date
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ec44df8d12 Added picture note, used gallery image is from previous revision. 2019-01-14 20:58:16 +01:00
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f269a2c9d0 Added reset circuit README 2019-01-14 20:55:02 +01:00
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b2ce8d5264 Added CPU README 2019-01-14 19:50:23 +01:00
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6a9603348a ... 2019-01-14 18:19:07 +01:00
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3d65f3716b Added ROM notice to get new RAM module instead 2019-01-14 18:17:11 +01:00
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6ea246326b Added ROM README 2019-01-14 17:49:59 +01:00
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42978a98ed Added memory maps 2019-01-14 16:42:40 +01:00
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dc223af12c Fixed typo, added BOM notes. 2019-01-14 15:04:31 +01:00
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bae1e34bf1 Updated Serial IO README 2019-01-14 14:50:37 +01:00
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6a4e16d951 Updated SBC README 2019-01-14 14:13:52 +01:00
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d8ac461620 Renamed ROM file extensions to bin to reflect content 2019-01-14 14:09:26 +01:00
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5273a9874b Changed schematic symbol for capacitor on serial output line 2019-01-14 14:08:34 +01:00
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10f21e5f85 Updated README 2019-01-13 16:30:29 +01:00
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356b47df30 Updated README 2019-01-13 16:22:42 +01:00
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3d5630a6b8 Added RAM enable jumper to SBC 2019-01-13 15:57:03 +01:00
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9f4a9bc07a Added ROM enable jumper to SBC 2019-01-13 14:15:39 +01:00
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c9be70cc0e Added resistor values to SBC silkscreen 2019-01-13 13:58:38 +01:00
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0958bd1aa5 Updated README 2019-01-13 02:31:54 +01:00
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b9e476a961 Updated README 2019-01-13 00:53:04 +01:00
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310acfa9c5 mmm 2019-01-13 00:16:51 +01:00
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2dcf69024f VDU amplifier layout done 2019-01-13 00:05:35 +01:00
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1b9981e258 VDU amplifier schematic done 2019-01-12 23:14:17 +01:00
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7c961c43e7 Backplane gerber export 2019-01-07 16:06:57 +01:00
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595a49bf7e Backplane layout done 2019-01-07 16:04:42 +01:00
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f83c7435b7 Added backplane schematic 2019-01-04 12:44:00 +01:00
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10a50b9e11 SBC uses new oscillator footprint 2019-01-02 15:30:34 +01:00
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b9a62e1dc7 Exported gerber files for VDU 2018-12-31 15:03:23 +01:00
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2e8cf266c5 Tried to increase ground plane flow 2018-12-30 21:08:53 +01:00
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1b400da7ee Cleaned up silkscreen 2018-12-30 12:40:21 +01:00
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4580e78f18 VDU PCB layout done 2018-12-30 11:16:17 +01:00
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5e270f1e1e Assigned new footprints 2018-12-29 14:07:32 +01:00
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d0f6b369fd Changed VDU CS logic ins schematic 2018-12-29 13:56:20 +01:00
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06fb25636e PSG gerber export 2018-12-28 17:54:54 +01:00
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19ec39a9d8 PSG sound card layout 2018-12-28 17:49:03 +01:00
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3129dca1b8 PSG sound card schematic added 2018-12-26 14:40:45 +01:00
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abe6294f0e Exported schematic to pdf 2018-12-25 17:19:18 +01:00
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8ffd6cb400 Added schematic for a bus monitor and single stepping card. 2018-12-23 01:12:41 +01:00
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f36f8700e3 Flipped decoder inputs, added details to silkscreen. 2018-12-23 01:12:14 +01:00
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6fd7df5eb0 Enhanced RAM/ROM board, routing done 2018-12-22 17:09:04 +01:00
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7dbb3f715b Schematic done for enhanced RAM/ROM board 2018-12-21 19:00:00 +01:00
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6f96621835 Moved incomplete add-on cards to abandoned. 2018-12-19 18:21:55 +01:00
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387ae4d119 Forced KiCad to actually use GND as ground name 2018-12-04 21:47:30 +01:00
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294df9eda7 Fixed footprint error 2018-12-04 21:36:13 +01:00
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77ffaff523 Assigned footprints 2018-12-04 21:24:15 +01:00
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4991b9cc4c Added description 2018-12-04 21:03:44 +01:00
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3f523c1871 Added analog circuit 2018-12-04 20:54:18 +01:00
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f7b1b1b4cd Digital logic added to schematic 2018-12-04 20:29:43 +01:00
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119308b48a Initial simulation of chip selects 2018-12-04 19:28:12 +01:00
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f480eb7541 VDU basic IO mapping start 2018-12-02 20:17:55 +01:00
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8bf93db474 Show R10, don't just link it! 2018-03-11 00:19:04 +01:00