Commit Graph

13 Commits

Author SHA1 Message Date
Olof Kindgren
7a7b165888 Add preliminary FuseSoC support
This adds support for simulating the two testbenches. Tested  with
icarus, modelsim, isim or xsim. Default is icarus

fusesoc run --target=$target --tool=$tool apple-one

where $target is apple1_tb or vga_tb and $tool is icarus,isim,modelsim or xsim
It also adds targets for building for the de0 and tinyfpga_b2 boards

fusesoc build --target={de0,tinyfpga_b2} apple-one

All ROM and ROM files can be overriden on the command-line, e.g.

fusesoc build --target=de0 apple-one --BASIC_FILENAME=/path/to/file.hex

Use fusesoc build --target=$target apple-one --help to see all
parameters
2018-02-12 15:19:40 +01:00
Niels Moseley
61f9fc4937 Updated Terasic DE0 target to new dir format 2018-02-11 22:48:00 +01:00
Niels Moseley
96061a7fa9 Added README.md for Terasic DE0 board. 2018-02-11 17:55:13 +01:00
Niels Moseley
894c50ff4e Added debounced PS/2 keyboard interface and A1 top-level selection between keyboard and UART RX 2018-02-08 23:47:09 +01:00
Niels Moseley
dd2c480675 Fixed reg/wire problems for Quartus. 2018-02-07 17:12:27 +01:00
Niels Moseley
c1942d5d14 new VGA 2018-02-05 14:43:46 +01:00
Niels Moseley
fe05766894 Fixed address lines of Basic ROM 2018-01-28 20:18:56 +01:00
Niels Moseley
d280d2abaa Added basic ps2 keyboard interface block 2018-01-28 02:00:21 +01:00
Niels Moseley
fba6bda601 Adding missing DE0 timing constraints file 2018-01-27 23:02:05 +01:00
Niels Moseley
6823d0e3f9 Added 6502 PC monitoring 2018-01-27 18:11:33 +01:00
Niels Moseley
0527dbb999 Updated DE0 top level and Quartus DE0 project to new directory layout 2018-01-27 16:01:27 +01:00
Niels Moseley
f067774293 Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal. 2018-01-26 22:38:46 +01:00
Niels Moseley
9beb3e5f5e Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00