folder structure added
This commit is contained in:
freitz85
parent
50d903c980
commit
30a026b18a
|
|
@ -1,4 +1,97 @@
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|||
#Gitignore for files generated by Xilinx ISE
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||||
#ignore OS noise
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||||
|
||||
Thumbs.db
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||||
.DS_Store
|
||||
|
||||
# Ignore list for Eagle, a PCB layout tool
|
||||
|
||||
# Backup files
|
||||
*.s#?
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||||
*.b#?
|
||||
*.l#?
|
||||
|
||||
# Eagle project file
|
||||
# It contains a serial number and references to the file structure
|
||||
# on your computer.
|
||||
# comment the following line if you want to have your project file included.
|
||||
eagle.epf
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||||
|
||||
# Autorouter files
|
||||
*.pro
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||||
*.job
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||||
|
||||
# CAM files
|
||||
*.$$$
|
||||
*.cmp
|
||||
*.ly2
|
||||
*.l15
|
||||
*.sol
|
||||
*.plc
|
||||
*.stc
|
||||
*.sts
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||||
*.crc
|
||||
*.crs
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||||
|
||||
*.dri
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||||
*.drl
|
||||
*.gpi
|
||||
*.pls
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||||
|
||||
*.drd
|
||||
*.drd.*
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||||
|
||||
*.info
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||||
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||||
*.eps
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||||
|
||||
# file locks introduced since 7.x
|
||||
*.lck
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||||
|
||||
# Xilinx ISE
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||||
# intermediate build files
|
||||
*.bgn
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||||
*.bit
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||||
*.bld
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||||
*.cmd_log
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||||
*.drc
|
||||
*.ll
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||||
*.lso
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||||
*.msd
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||||
*.msk
|
||||
*.ncd
|
||||
*.ngc
|
||||
*.ngd
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||||
*.ngr
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||||
*.pad
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||||
*.par
|
||||
*.pcf
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||||
*.prj
|
||||
*.ptwx
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||||
*.rbb
|
||||
*.rbd
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||||
*.stx
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||||
*.syr
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||||
*.twr
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||||
*.twx
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||||
*.unroutes
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||||
*.ut
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||||
*.xpi
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||||
*.xst
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||||
*_bitgen.xwbt
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||||
*_envsettings.html
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||||
*_map.map
|
||||
*_map.mrp
|
||||
*_map.ngm
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||||
*_map.xrpt
|
||||
*_ngdbuild.xrpt
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||||
*_pad.csv
|
||||
*_pad.txt
|
||||
*_par.xrpt
|
||||
*_summary.html
|
||||
*_summary.xml
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||||
*_usage.xml
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||||
*_xst.xrpt
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||||
|
||||
|
||||
*.log
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||||
*.svf
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||||
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|
@ -38,7 +131,26 @@ impact_impact.xwbt
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spi6502b_html*/
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__projnav*/
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||||
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||||
#ignore OS noise
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||||
# iMPACT generated files
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||||
_impactbatch.log
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||||
impact.xsl
|
||||
impact_impact.xwbt
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||||
ise_impact.cmd
|
||||
webtalk_impact.xml
|
||||
|
||||
Thumbs.db
|
||||
.DS_Store
|
||||
# Core Generator generated files
|
||||
xaw2verilog.log
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||||
|
||||
# project-wide generated files
|
||||
*.gise
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||||
par_usage_statistics.html
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||||
usage_statistics_webtalk.html
|
||||
webtalk.log
|
||||
webtalk_pn.xml
|
||||
|
||||
# generated folders
|
||||
iseconfig/
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||||
xlnx_auto_0_xdb/
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xst/
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_ngo/
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_xmsgs/
|
||||
|
|
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@ -0,0 +1,670 @@
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1 ********************************
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2 *
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3 * Initialize SD card
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4 *
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5 ********************************
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||||
6
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7 XC
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||||
8 ORG $8000
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9
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||||
10 SLOT = $04 ; slot 4
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11 DATA = $C0C0 ; slot 4
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||||
12 CTRL = DATA+1
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||||
13 DIV = DATA+2
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||||
14 SS = DATA+3
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15 R30 = $0478
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||||
16 R31 = $04F8
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||||
17 R32 = $0578
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||||
18 R33 = $05F8
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19 CMDLO = $FA
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||||
20 CMDHI = $FB
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||||
21 *
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22 FROM = $FA ; + $fb
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||||
23 TO = $FC ; + $fd
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||||
24 SIZE = $FE ; + $ff
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||||
25 *
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||||
26 SSNONE = $0F
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||||
27 SS0 = $0E
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||||
28 TC = $80
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||||
29 DUMMY = $FF
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||||
30
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||||
31
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||||
32 ********************************
|
||||
33 *
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||||
34 * Install SD card driver
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35 *
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36 ********************************
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||||
37
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||||
38 * make room for the driver
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||||
39
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||||
8000: A9 04 40 GETBUF LDA #4 ; allocate 4 pages
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8002: 20 F5 BE 41 JSR $BEF5 ; call GETBUFR
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||||
8005: B0 59 42 BCS ERROR ; did an error occur?
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||||
8007: 85 FD 43 STA TO+1 ; store buffer addr msb
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||||
8009: 8D 84 80 44 STA BUFMSB
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800C: 64 FC 45 STZ TO ; store buffer addr lsb
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800E: 9C 85 80 46 STZ BUFLSB
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8011: A9 80 47 LDA #>DRIVER1
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8013: 85 FB 48 STA FROM+1 ; store from addr msb
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8015: A9 8C 49 LDA #<DRIVER1
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8017: 85 FA 50 STA FROM ; store from addr lsb
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8019: A9 02 51 LDA #>DRIVEND-DRIVER
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801B: 85 FF 52 STA SIZE+1 ; store size msb
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801D: A9 E4 53 LDA #<DRIVEND-DRIVER
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801F: 85 FE 54 STA SIZE ; store size lsb
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55
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56 * move driver to new address
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57
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8021: A6 FF 58 MOVEUP LDX SIZE+1 ; the last byte must be
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8023: 18 59 CLC ; moved first, start at
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===== Page 2 =====
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8024: 8A 60 TXA ; the final pages of FROM
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8025: 65 FB 61 ADC FROM+1 ; and TO
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8027: 85 FB 62 STA FROM+1
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8029: 18 63 CLC
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802A: 8A 64 TXA
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802B: 65 FD 65 ADC TO+1
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802D: 85 FD 66 STA TO+1
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802F: E8 67 INX ; allows the use of
|
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8030: A4 FE 68 LDY SIZE ; BNE after DEX below
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8032: F0 0E 69 BEQ MU3
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8034: 88 70 DEY ; move bytes on the last
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8035: F0 07 71 BEQ MU2 ; page first
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8037: B1 FA 72 MU1 LDA (FROM),Y
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8039: 91 FC 73 STA (TO),Y
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803B: 88 74 DEY
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803C: D0 F9 75 BNE MU1
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803E: B1 FA 76 MU2 LDA (FROM),Y ; handle Y=0 separately
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8040: 91 FC 77 STA (TO),Y
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||||
8042: 88 78 MU3 DEY
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||||
8043: C6 FB 79 DEC FROM+1 ; move the next page
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||||
8045: C6 FD 80 DEC TO+1 ; (if any)
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||||
8047: CA 81 DEX
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||||
8048: D0 ED 82 BNE MU1
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||||
83
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||||
84 * see if slot 4 has a driver already
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||||
85
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||||
804A: AE 31 BF 86 INSTALL LDX $BF31 ; get devcnt
|
||||
804D: BD 32 BF 87 INSLP LDA $BF32,X ; get a devnum
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||||
8050: 29 70 88 AND #$70 ; isolate slot
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||||
8052: C9 40 89 CMP #$40 ; slot 4?
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||||
8054: F0 2D 90 BEQ INSOUT ; yes, skip it
|
||||
8056: CA 91 DEX
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||||
8057: 10 F4 92 BPL INSLP ; keep up the search
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||||
93
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||||
94 * restore the devnum to the list
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||||
95
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8059: AE 31 BF 96 LDX $BF31 ; get devcnt again
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805C: E0 0D 97 CPX #$0D device table full?
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805E: D0 03 98 BNE INSLP2
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99
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8060: 4C 83 80 100 ERROR JMP INSOUT ; do something!
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101
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8063: BD 31 BF 102 INSLP2 LDA $BF32-1,X ; move all entries down
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8066: 9D 32 BF 103 STA $BF32,X ; to make room at front
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8069: CA 104 DEX ; for a new entry
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||||
806A: D0 F7 105 BNE INSLP2
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806C: A9 44 106 LDA #$44
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806E: 8D 32 BF 107 STA $BF32 ; slot 4, drive 1 at top of list
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8071: EE 31 BF 108 INC $BF31 ; update devcnt
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109
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110 * now insert the device driver vector
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111
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8074: AD 85 80 112 LDA BUFLSB
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8077: 8D 18 BF 113 STA $BF18
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807A: AD 84 80 114 LDA BUFMSB
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807D: 8D 19 BF 115 STA $BF19
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||||
8080: 20 26 96 116 JSR INIT ; init card
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===== Page 3 =====
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||||
117
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||||
8083: 60 118 INSOUT RTS
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119
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||||
8084: 00 120 BUFMSB DB #0
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||||
8085: 00 121 BUFLSB DB #0
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||||
122
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||||
123 ********************************
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||||
124 *
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125 * Jump table
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126 *
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127 ********************************
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128
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8086: 2C FF CF 129 BIT $CFFF
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8089: 4C 26 96 130 JMP INIT
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||||
131
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||||
132 DRIVER1 = *
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||||
133 ORG $9600
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||||
134
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||||
9600: D8 135 DRIVER CLD
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||||
9601: 2C FF CF 136 BIT $CFFF
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||||
9604: A5 42 137 LDA $42
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||||
9606: C9 00 138 CMP #$00
|
||||
9608: F0 10 139 BEQ :STATUS
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||||
960A: C9 01 140 CMP #$01
|
||||
960C: F0 0F 141 BEQ :READ
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||||
960E: C9 02 142 CMP #$02
|
||||
9610: F0 0E 143 BEQ :WRITE
|
||||
9612: C9 03 144 CMP #$03
|
||||
9614: F0 0D 145 BEQ :FORMAT
|
||||
9616: 38 146 SEC ; unknown command
|
||||
9617: A9 01 147 LDA #$01
|
||||
9619: 60 148 RTS
|
||||
149
|
||||
961A: 4C 5C 97 150 :STATUS JMP STATUS
|
||||
961D: 4C 64 97 151 :READ JMP READ
|
||||
9620: 4C 0F 98 152 :WRITE JMP WRITE
|
||||
9623: 4C B6 98 153 :FORMAT JMP FORMAT
|
||||
154
|
||||
155
|
||||
156 ********************************
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||||
157 *
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||||
158 * Initialize SD card
|
||||
159 *
|
||||
160 * C Clear - No error
|
||||
161 * Set - Error
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||||
162 * A $00 - No error
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||||
163 * $27 - I/O error - Init failed
|
||||
164 * $28 - No card inserted
|
||||
165 *
|
||||
166 ********************************
|
||||
167
|
||||
9626: D8 168 INIT CLD
|
||||
9627: A9 03 169 LDA #$03 ; set SPI mode 3
|
||||
9629: 8D C1 C0 170 STA CTRL
|
||||
962C: A9 0F 171 LDA #SSNONE
|
||||
962E: 8D C3 C0 172 STA SS
|
||||
9631: A9 07 173 LDA #7
|
||||
===== Page 4 =====
|
||||
|
||||
9633: 8D C2 C0 174 STA DIV
|
||||
9636: A2 0A 175 LDX #10
|
||||
9638: A9 FF 176 LDA #DUMMY
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||||
177
|
||||
963A: 8D C0 C0 178 :LOOP STA DATA
|
||||
963D: 2C C1 C0 179 :WAIT BIT CTRL
|
||||
9640: 10 FB 180 BPL :WAIT
|
||||
9642: CA 181 DEX
|
||||
9643: D0 F5 182 BNE :LOOP ; do 10 times
|
||||
9645: A9 0E 183 LDA #SS0 ; set CS low
|
||||
9647: 8D C3 C0 184 STA SS
|
||||
185
|
||||
964A: A9 BA 186 LDA #<CMD0 ; send CMD0
|
||||
964C: 85 FA 187 STA CMDLO
|
||||
964E: A9 98 188 LDA #>CMD0
|
||||
9650: 85 FB 189 STA CMDHI
|
||||
9652: 20 FD 96 190 JSR CMD
|
||||
9655: 20 0F 97 191 JSR GETR1 ; get response
|
||||
9658: C9 01 192 CMP #$01
|
||||
965A: D0 39 193 BNE ERROR1 ; error!
|
||||
194
|
||||
965C: A9 C6 195 LDA #<CMD8 ; send CMD8
|
||||
965E: 85 FA 196 STA CMDLO
|
||||
9660: A9 98 197 LDA #>CMD8
|
||||
9662: 85 FB 198 STA CMDHI
|
||||
9664: 20 FD 96 199 JSR CMD
|
||||
9667: 20 2C 97 200 JSR GETR3
|
||||
966A: C9 01 201 CMP #$01
|
||||
966C: D0 2A 202 BNE SDV1 ; may be SD Ver. 1
|
||||
203
|
||||
204 * check for $01aa match!
|
||||
966E: A9 D2 205 SDV2 LDA #<CMD55
|
||||
9670: 85 FA 206 STA CMDLO
|
||||
9672: A9 98 207 LDA #>CMD55
|
||||
9674: 85 FB 208 STA CMDHI
|
||||
9676: 20 FD 96 209 JSR CMD
|
||||
9679: 20 0F 97 210 JSR GETR1
|
||||
967C: A9 D8 211 LDA #<ACMD41_40
|
||||
967E: 85 FA 212 STA CMDLO
|
||||
9680: A9 98 213 LDA #>ACMD41_40
|
||||
9682: 85 FB 214 STA CMDHI
|
||||
9684: 20 FD 96 215 JSR CMD
|
||||
9687: 20 0F 97 216 JSR GETR1
|
||||
968A: C9 01 217 CMP #$01
|
||||
968C: F0 E0 218 BEQ SDV2 ; wait for ready
|
||||
968E: C9 00 219 CMP #$00
|
||||
9690: D0 03 220 BNE ERROR1 ; error!
|
||||
221 * send CMD58
|
||||
222 * SD Ver. 2 initialized!
|
||||
9692: 4C D2 96 223 JMP BLOCKSZ
|
||||
224
|
||||
9695: 4C EE 96 225 ERROR1 JMP IOERROR ; needed for far jump
|
||||
226
|
||||
9698: A9 D2 227 SDV1 LDA #<CMD55
|
||||
969A: 85 FA 228 STA CMDLO
|
||||
969C: A9 98 229 LDA #>CMD55
|
||||
969E: 85 FB 230 STA CMDHI
|
||||
===== Page 5 =====
|
||||
|
||||
96A0: 20 FD 96 231 JSR CMD ; ignore response
|
||||
96A3: A9 DE 232 LDA #<ACMD41_0
|
||||
96A5: 85 FA 233 STA CMDLO
|
||||
96A7: A9 98 234 LDA #>ACMD41_0
|
||||
96A9: 85 FB 235 STA CMDHI
|
||||
96AB: 20 FD 96 236 JSR CMD
|
||||
96AE: 20 0F 97 237 JSR GETR1
|
||||
96B1: C9 01 238 CMP #$01
|
||||
96B3: F0 E3 239 BEQ SDV1 ; wait for ready
|
||||
96B5: C9 00 240 CMP #$00
|
||||
96B7: D0 03 241 BNE MMC ; may be MMC card
|
||||
242 * SD Ver. 1 initialized!
|
||||
96B9: 4C D2 96 243 JMP BLOCKSZ
|
||||
244
|
||||
96BC: A9 C0 245 MMC LDA #<CMD1
|
||||
96BE: 85 FA 246 STA CMDLO
|
||||
96C0: A9 98 247 LDA #>CMD1
|
||||
96C2: 85 FB 248 STA CMDHI
|
||||
96C4: 20 FD 96 249 :LOOP JSR CMD
|
||||
96C7: 20 0F 97 250 JSR GETR1
|
||||
96CA: C9 01 251 CMP #$01
|
||||
96CC: F0 F6 252 BEQ :LOOP ; wait for ready
|
||||
96CE: C9 00 253 CMP #$00
|
||||
96D0: D0 1C 254 BNE IOERROR ; error!
|
||||
255 * MMC Ver. 3 initialized!
|
||||
256
|
||||
96D2: A9 CC 257 BLOCKSZ LDA #<CMD16
|
||||
96D4: 85 FA 258 STA CMDLO
|
||||
96D6: A9 98 259 LDA #>CMD16
|
||||
96D8: 85 FB 260 STA CMDHI
|
||||
96DA: 20 FD 96 261 JSR CMD
|
||||
96DD: 20 0F 97 262 JSR GETR1
|
||||
96E0: C9 00 263 CMP #$00
|
||||
96E2: D0 0A 264 BNE IOERROR ; error!
|
||||
265
|
||||
96E4: 18 266 END CLC ; all ok
|
||||
96E5: A0 00 267 LDY #0
|
||||
96E7: 90 08 268 BCC END1
|
||||
96E9: 38 269 CDERROR SEC
|
||||
96EA: A0 28 270 LDY #$28 ; no card error
|
||||
96EC: B0 03 271 BCS END1
|
||||
96EE: 38 272 IOERROR SEC
|
||||
96EF: A0 27 273 LDY #$27 ; init error
|
||||
96F1: A9 0F 274 END1 LDA #SSNONE ; deselect card
|
||||
96F3: 8D C3 C0 275 STA SS
|
||||
96F6: A9 00 276 LDA #0
|
||||
96F8: 8D C2 C0 277 STA DIV
|
||||
96FB: 98 278 TYA ; retval in A
|
||||
96FC: 60 279 RTS
|
||||
280
|
||||
281
|
||||
282 ********************************
|
||||
283 *
|
||||
284 * Send SD command
|
||||
285 * Call with command in CMDHI and CMDLO
|
||||
286 *
|
||||
287 ********************************
|
||||
===== Page 6 =====
|
||||
|
||||
288
|
||||
96FD: A0 00 289 CMD LDY #0
|
||||
96FF: B1 FA 290 :LOOP LDA (CMDLO),Y
|
||||
9701: 8D C0 C0 291 STA DATA
|
||||
9704: 2C C1 C0 292 :WAIT BIT CTRL ; TC is in N
|
||||
9707: 10 FB 293 BPL :WAIT
|
||||
9709: C8 294 INY
|
||||
970A: C0 06 295 CPY #6
|
||||
970C: 90 F1 296 BCC :LOOP
|
||||
970E: 60 297 RTS
|
||||
298
|
||||
299
|
||||
300 ********************************
|
||||
301 *
|
||||
302 * Get R1
|
||||
303 * R1 is in A
|
||||
304 *
|
||||
305 ********************************
|
||||
306
|
||||
970F: A9 FF 307 GETR1 LDA #DUMMY
|
||||
9711: 8D C0 C0 308 STA DATA
|
||||
9714: 2C C1 C0 309 :WAIT BIT CTRL
|
||||
9717: 10 FB 310 BPL :WAIT
|
||||
9719: AD C0 C0 311 LDA DATA ; get response
|
||||
971C: 8D 7C 04 312 STA R30+SLOT ; save R1
|
||||
971F: 29 80 313 AND #$80
|
||||
9721: D0 EC 314 BNE GETR1 ; wait for MSB=0
|
||||
9723: A9 FF 315 LDA #DUMMY
|
||||
9725: 8D C0 C0 316 STA DATA ; send another dummy
|
||||
9728: AD 7C 04 317 LDA R30+SLOT ; restore R1
|
||||
972B: 60 318 RTS
|
||||
319
|
||||
320
|
||||
321 ********************************
|
||||
322 *
|
||||
323 * Get R3
|
||||
324 * R1 is in A
|
||||
325 * R3 is in scratchpad ram
|
||||
326 *
|
||||
327 ********************************
|
||||
328
|
||||
972C: 20 0F 97 329 GETR3 JSR GETR1 ; get R1 first
|
||||
972F: 48 330 PHA ; save R1
|
||||
9730: 5A 331 PHY ; save Y
|
||||
9731: A0 04 332 LDY #04
|
||||
9733: A9 FF 333 :LOOP LDA #DUMMY ; send dummy
|
||||
9735: 8D C0 C0 334 STA DATA
|
||||
9738: 2C C1 C0 335 :WAIT BIT CTRL
|
||||
973B: 10 FB 336 BPL :WAIT
|
||||
973D: AD C0 C0 337 LDA DATA
|
||||
9740: 48 338 PHA
|
||||
9741: 88 339 DEY
|
||||
9742: D0 EF 340 BNE :LOOP ; do 4 times
|
||||
9744: 68 341 PLA
|
||||
9745: 8D FC 05 342 STA R33+SLOT ; save R3
|
||||
9748: 68 343 PLA
|
||||
9749: 8D 7C 05 344 STA R32+SLOT
|
||||
===== Page 7 =====
|
||||
|
||||
974C: 68 345 PLA
|
||||
974D: 8D FC 04 346 STA R31+SLOT
|
||||
9750: 68 347 PLA
|
||||
9751: 8D 7C 04 348 STA R30+SLOT
|
||||
9754: 7A 349 PLY ; restore Y
|
||||
9755: A9 FF 350 LDA #DUMMY
|
||||
9757: 8D C0 C0 351 STA DATA ; send another dummy
|
||||
975A: 68 352 PLA ; restore R1
|
||||
975B: 60 353 RTS
|
||||
354
|
||||
355
|
||||
356 ********************************
|
||||
357 *
|
||||
358 * Status request
|
||||
359 * $43 Unt number DSSS000
|
||||
360 * $44-45 Unused
|
||||
361 * $46-47 Unused
|
||||
362 *
|
||||
363 * C Clear - No error
|
||||
364 * Set - Error
|
||||
365 * A $00 - No error
|
||||
366 * $27 - I/O error
|
||||
367 * $28 - No card inserted / no init
|
||||
368 * $2B - Card write protected
|
||||
369 * X - Blocks avail (low byte)
|
||||
370 * Y - Blocks avail (high byte)
|
||||
371 *
|
||||
372 ********************************
|
||||
373
|
||||
975C: 18 374 STATUS CLC ; no error
|
||||
975D: A9 00 375 LDA #0
|
||||
975F: A2 FF 376 LDX #$FF ; 32 MB partition
|
||||
9761: A0 FF 377 LDY #$FF
|
||||
9763: 60 378 RTS
|
||||
379
|
||||
380 * TODO: check for card detect and write protect!
|
||||
381
|
||||
382
|
||||
383 ********************************
|
||||
384 *
|
||||
385 * Read 512 byte block
|
||||
386 * $43 Unit number DSSS0000
|
||||
387 * $44-45 Address (LO/HI) of buffer
|
||||
388 * $46-47 Block number (LO/HI)
|
||||
389 *
|
||||
390 * C Clear - No error
|
||||
391 * Set - Error
|
||||
392 * A $00 - No error
|
||||
393 * $27 - Bad block number
|
||||
394 * $28 - No card inserted
|
||||
395 *
|
||||
396 ********************************
|
||||
397
|
||||
398 * TODO: check for card detect!
|
||||
399
|
||||
9764: A9 0E 400 READ LDA #SS0 ; enable /CS
|
||||
9766: 8D C3 C0 401 STA SS
|
||||
===== Page 8 =====
|
||||
|
||||
402
|
||||
9769: A5 46 403 LDA $46 ; store block num
|
||||
976B: 8D FC 05 404 STA R33+SLOT ; in R30-R33
|
||||
976E: A5 47 405 LDA $47
|
||||
9770: 8D 7C 05 406 STA R32+SLOT
|
||||
9773: 9C FC 04 407 STZ R31+SLOT
|
||||
9776: 9C 7C 04 408 STZ R30+SLOT
|
||||
9779: A0 09 409 LDY #9
|
||||
977B: 0E FC 05 410 :LOOP ASL R33+SLOT ; mul block num
|
||||
977E: 2E 7C 05 411 ROL R32+SLOT ; by 512 to get
|
||||
9781: 2E FC 04 412 ROL R31+SLOT ; real address
|
||||
9784: 2E 7C 04 413 ROL R30+SLOT
|
||||
9787: 88 414 DEY
|
||||
9788: D0 F1 415 BNE :LOOP
|
||||
416
|
||||
978A: A9 51 417 LDA #$51 ; send CMD17
|
||||
978C: 8D C0 C0 418 STA DATA
|
||||
978F: 2C C1 C0 419 :WAIT BIT CTRL
|
||||
9792: 10 FB 420 BPL :WAIT
|
||||
9794: AD 7C 04 421 :ARG LDA R30+SLOT ; get arg from R30 on
|
||||
9797: 8D C0 C0 422 STA DATA
|
||||
979A: 2C C1 C0 423 :WAIT1 BIT CTRL
|
||||
979D: 10 FB 424 BPL :WAIT1
|
||||
979F: AD FC 04 425 LDA R31+SLOT
|
||||
97A2: 8D C0 C0 426 STA DATA
|
||||
97A5: 2C C1 C0 427 :WAIT11 BIT CTRL
|
||||
97A8: 10 FB 428 BPL :WAIT11
|
||||
97AA: AD 7C 05 429 LDA R32+SLOT
|
||||
97AD: 8D C0 C0 430 STA DATA
|
||||
97B0: 2C C1 C0 431 :WAIT12 BIT CTRL
|
||||
97B3: 10 FB 432 BPL :WAIT12
|
||||
97B5: AD FC 05 433 LDA R33+SLOT
|
||||
97B8: 8D C0 C0 434 STA DATA
|
||||
97BB: 2C C1 C0 435 :WAIT13 BIT CTRL
|
||||
97BE: 10 FB 436 BPL :WAIT13
|
||||
97C0: A9 FF 437 LDA #DUMMY
|
||||
97C2: 8D C0 C0 438 STA DATA ; dummy crc
|
||||
97C5: 2C C1 C0 439 :WAIT2 BIT CTRL
|
||||
97C8: 10 FB 440 BPL :WAIT2
|
||||
97CA: A9 FF 441 :GETR1 LDA #DUMMY
|
||||
97CC: 8D C0 C0 442 STA DATA ; get R1
|
||||
97CF: 2C C1 C0 443 :WAIT3 BIT CTRL
|
||||
97D2: 10 FB 444 BPL :WAIT3
|
||||
97D4: AD C0 C0 445 LDA DATA ; get response
|
||||
446 *
|
||||
447 * TODO: check for error!
|
||||
448 *
|
||||
97D7: C9 FE 449 CMP #$FE
|
||||
97D9: D0 EF 450 BNE :GETR1 ; wait for $FE
|
||||
451
|
||||
97DB: A2 02 452 LDX #2 ; read data from card
|
||||
97DD: A0 00 453 :LOOPX LDY #0
|
||||
97DF: A9 FF 454 :LOOPY LDA #DUMMY
|
||||
97E1: 8D C0 C0 455 STA DATA
|
||||
97E4: 2C C1 C0 456 :WAIT4 BIT CTRL
|
||||
97E7: 10 FB 457 BPL :WAIT4
|
||||
97E9: AD C0 C0 458 LDA DATA
|
||||
===== Page 9 =====
|
||||
|
||||
97EC: 92 44 459 STA ($44)
|
||||
97EE: E6 44 460 INC $44
|
||||
97F0: D0 02 461 BNE :INY
|
||||
97F2: E6 45 462 INC $45 ; inc msb on page boundary
|
||||
97F4: C8 463 :INY INY
|
||||
97F5: D0 E8 464 BNE :LOOPY
|
||||
97F7: CA 465 DEX
|
||||
97F8: D0 E3 466 BNE :LOOPX
|
||||
467
|
||||
97FA: 20 2C 97 468 :OK JSR GETR3 ; read 2 bytes crc
|
||||
97FD: A9 0F 469 LDA #SSNONE
|
||||
97FF: 8D C3 C0 470 STA SS ; disable /CS
|
||||
9802: 18 471 CLC ; no error
|
||||
9803: A9 00 472 LDA #$00
|
||||
9805: 60 473 RTS
|
||||
474
|
||||
9806: A9 0F 475 :ERROR LDA #SSNONE
|
||||
9808: 8D C3 C0 476 STA SS ; disable /CS
|
||||
980B: 38 477 SEC ; an error occured
|
||||
980C: A9 27 478 LDA #$27
|
||||
980E: 60 479 RTS
|
||||
480
|
||||
481
|
||||
482 ********************************
|
||||
483 *
|
||||
484 * Write 512 byte block
|
||||
485 * $43 Unit number DSSS000
|
||||
486 * $44-45 Address (LO/HI) of buffer
|
||||
487 * $46-47 Block number (LO/HI)
|
||||
488 *
|
||||
489 * C Clear - No error
|
||||
490 * Set - Error
|
||||
491 * A $00 - No error
|
||||
492 * $27 - Bad block number
|
||||
493 * $28 - No card inserted
|
||||
494 *
|
||||
495 ********************************
|
||||
496
|
||||
497 * TODO: check for card detect and write protect!
|
||||
498
|
||||
980F: A9 0E 499 WRITE LDA #SS0 ; enable /CS
|
||||
9811: 8D C3 C0 500 STA SS
|
||||
501
|
||||
9814: A5 46 502 LDA $46 ; store block num
|
||||
9816: 8D FC 05 503 STA R33+SLOT
|
||||
9819: A5 47 504 LDA $47
|
||||
981B: 8D 7C 05 505 STA R32+SLOT
|
||||
981E: 9C FC 04 506 STZ R31+SLOT
|
||||
9821: 9C 7C 04 507 STZ R30+SLOT
|
||||
9824: A0 09 508 LDY #9
|
||||
9826: 0E FC 05 509 :LOOP ASL R33+SLOT ; mul block num
|
||||
9829: 2E 7C 05 510 ROL R32+SLOT ; by 512 to get
|
||||
982C: 2E FC 04 511 ROL R31+SLOT ; real address
|
||||
982F: 2E 7C 04 512 ROL R30+SLOT
|
||||
9832: 88 513 DEY
|
||||
9833: D0 F1 514 BNE :LOOP
|
||||
515
|
||||
===== Page 10 =====
|
||||
|
||||
9835: A9 58 516 LDA #$58 ; send CMD24
|
||||
9837: 8D C0 C0 517 STA DATA
|
||||
983A: 2C C1 C0 518 :WAIT BIT CTRL
|
||||
983D: 10 FB 519 BPL :WAIT
|
||||
983F: AD 7C 04 520 :ARG LDA R30+SLOT ; get arg from R30 on
|
||||
9842: 8D C0 C0 521 STA DATA
|
||||
9845: 2C C1 C0 522 :WAIT1 BIT CTRL
|
||||
9848: 10 FB 523 BPL :WAIT1
|
||||
984A: AD FC 04 524 LDA R31+SLOT
|
||||
984D: 8D C0 C0 525 STA DATA
|
||||
9850: 2C C1 C0 526 :WAIT11 BIT CTRL
|
||||
9853: 10 FB 527 BPL :WAIT11
|
||||
9855: AD 7C 05 528 LDA R32+SLOT
|
||||
9858: 8D C0 C0 529 STA DATA
|
||||
985B: 2C C1 C0 530 :WAIT12 BIT CTRL
|
||||
985E: 10 FB 531 BPL :WAIT12
|
||||
9860: AD FC 05 532 LDA R33+SLOT
|
||||
9863: 8D C0 C0 533 STA DATA
|
||||
9866: 2C C1 C0 534 :WAIT13 BIT CTRL
|
||||
9869: 10 FB 535 BPL :WAIT13
|
||||
986B: A9 FF 536 LDA #DUMMY
|
||||
986D: 8D C0 C0 537 STA DATA ; dummy crc
|
||||
9870: 2C C1 C0 538 :WAIT2 BIT CTRL
|
||||
9873: 10 FB 539 BPL :WAIT2
|
||||
9875: A9 FF 540 :GETR1 LDA #DUMMY
|
||||
9877: 8D C0 C0 541 STA DATA ; get R1
|
||||
987A: 2C C1 C0 542 :WAIT3 BIT CTRL
|
||||
987D: 10 FB 543 BPL :WAIT3
|
||||
987F: AD C0 C0 544 LDA DATA : get response
|
||||
545 *
|
||||
546 * TODO: check for error!
|
||||
547 *
|
||||
9882: C9 FE 548 CMP #$FE
|
||||
9884: D0 EF 549 BNE :GETR1 ; wait for $FE
|
||||
9886: A2 02 550 LDX #2 ; send data to card
|
||||
9888: A0 00 551 :LOOPX LDY #0
|
||||
988A: B2 44 552 :LOOPY LDA ($44)
|
||||
988C: 8D C0 C0 553 STA DATA
|
||||
988F: 2C C1 C0 554 :WAIT4 BIT CTRL
|
||||
9892: 10 FB 555 BPL :WAIT4
|
||||
9894: E6 44 556 INC $44
|
||||
9896: D0 02 557 BNE :INY
|
||||
9898: E6 45 558 INC $45 ; inc msbon page boundary
|
||||
989A: C8 559 :INY INY
|
||||
989B: D0 ED 560 BNE :LOOPY
|
||||
989D: CA 561 DEX
|
||||
989E: D0 E8 562 BNE :LOOPX
|
||||
563
|
||||
98A0: A0 02 564 LDY #2 ; send 2 dummy crc bytes
|
||||
98A2: 8D C0 C0 565 :CRC STA DATA
|
||||
98A5: 2C C1 C0 566 :WAIT5 BIT CTRL
|
||||
98A8: 10 FB 567 BPL :WAIT5
|
||||
98AA: 88 568 DEY
|
||||
98AB: D0 F5 569 BNE :CRC
|
||||
570
|
||||
98AD: A9 0F 571 :OK LDA #SSNONE ; disable /CS
|
||||
98AF: 8D C3 C0 572 STA SS
|
||||
===== Page 11 =====
|
||||
|
||||
98B2: 18 573 CLC ; no error
|
||||
98B3: A9 00 574 LDA #0
|
||||
98B5: 60 575 RTS
|
||||
576
|
||||
577
|
||||
578 ********************************
|
||||
579 *
|
||||
580 * Format
|
||||
581 * not supported!
|
||||
582 *
|
||||
583 ********************************
|
||||
584
|
||||
98B6: 38 585 FORMAT SEC
|
||||
98B7: A9 01 586 LDA #$01 ; invalid command
|
||||
98B9: 60 587 RTS
|
||||
588
|
||||
589
|
||||
590
|
||||
98BA: 40 00 00 591 CMD0 HEX 400000000095
|
||||
98BD: 00 00 95
|
||||
98C0: 41 00 00 592 CMD1 HEX 4100000000F9
|
||||
98C3: 00 00 F9
|
||||
98C6: 48 00 00 593 CMD8 HEX 48000001AA87
|
||||
98C9: 01 AA 87
|
||||
98CC: 50 00 00 594 CMD16 HEX 5000000200FF
|
||||
98CF: 02 00 FF
|
||||
98D2: 77 00 00 595 CMD55 HEX 770000000065
|
||||
98D5: 00 00 65
|
||||
98D8: 69 40 00 596 ACMD41_40 HEX 694000000077
|
||||
98DB: 00 00 77
|
||||
98DE: 69 00 00 597 ACMD41_0 HEX 6900000000FF
|
||||
98E1: 00 00 FF
|
||||
598
|
||||
599 DRIVEND = *
|
||||
|
||||
|
||||
--End assembly, 880 bytes, Errors: 0
|
||||
|
||||
|
||||
Symbol table - alphabetical order:
|
||||
|
||||
ACMD41_0=$98DE ACMD41_40=$98D8 BLOCKSZ =$96D2 BUFLSB =$8085
|
||||
BUFMSB =$8084 ? CDERROR =$96E9 CMD =$96FD CMD0 =$98BA
|
||||
CMD1 =$98C0 CMD16 =$98CC CMD55 =$98D2 CMD8 =$98C6
|
||||
CMDHI =$FB CMDLO =$FA CTRL =$C0C1 DATA =$C0C0
|
||||
DIV =$C0C2 DRIVEND =$98E4 DRIVER =$9600 DRIVER1 =$808C
|
||||
DUMMY =$FF ? END =$96E4 END1 =$96F1 ERROR =$8060
|
||||
ERROR1 =$9695 FORMAT =$98B6 FROM =$FA ? GETBUF =$8000
|
||||
GETR1 =$970F GETR3 =$972C INIT =$9626 INSLP =$804D
|
||||
INSLP2 =$8063 INSOUT =$8083 ? INSTALL =$804A IOERROR =$96EE
|
||||
MMC =$96BC ? MOVEUP =$8021 MU1 =$8037 MU2 =$803E
|
||||
MU3 =$8042 R30 =$0478 R31 =$04F8 R32 =$0578
|
||||
R33 =$05F8 READ =$9764 SDV1 =$9698 SDV2 =$966E
|
||||
SIZE =$FE SLOT =$04 SS =$C0C3 SS0 =$0E
|
||||
SSNONE =$0F STATUS =$975C ? TC =$80 TO =$FC
|
||||
WRITE =$980F
|
||||
|
||||
===== Page 12 =====
|
||||
|
||||
|
||||
Symbol table - numerical order:
|
||||
|
||||
SLOT =$04 SS0 =$0E SSNONE =$0F ? TC =$80
|
||||
CMDLO =$FA FROM =$FA CMDHI =$FB TO =$FC
|
||||
SIZE =$FE DUMMY =$FF R30 =$0478 R31 =$04F8
|
||||
R32 =$0578 R33 =$05F8 ? GETBUF =$8000 ? MOVEUP =$8021
|
||||
MU1 =$8037 MU2 =$803E MU3 =$8042 ? INSTALL =$804A
|
||||
INSLP =$804D ERROR =$8060 INSLP2 =$8063 INSOUT =$8083
|
||||
BUFMSB =$8084 BUFLSB =$8085 DRIVER1 =$808C DRIVER =$9600
|
||||
INIT =$9626 SDV2 =$966E ERROR1 =$9695 SDV1 =$9698
|
||||
MMC =$96BC BLOCKSZ =$96D2 ? END =$96E4 ? CDERROR =$96E9
|
||||
IOERROR =$96EE END1 =$96F1 CMD =$96FD GETR1 =$970F
|
||||
GETR3 =$972C STATUS =$975C READ =$9764 WRITE =$980F
|
||||
FORMAT =$98B6 CMD0 =$98BA CMD1 =$98C0 CMD8 =$98C6
|
||||
CMD16 =$98CC CMD55 =$98D2 ACMD41_40=$98D8 ACMD41_0=$98DE
|
||||
DRIVEND =$98E4 DATA =$C0C0 CTRL =$C0C1 DIV =$C0C2
|
||||
SS =$C0C3
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,771 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="7.2.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<description><b>Apple ][ Expansion Card Templates</b>
|
||||
<br />
|
||||
Dimensions are taken from the Apple IIgs Tech Note #28</description>
|
||||
<packages>
|
||||
<package name="A2-50PIN-SL1-3">
|
||||
<description><B>Apple ][ Peripheral Card</B>
|
||||
<br />
|
||||
Standard 50-pin edge connector for Apple ][ systems
|
||||
<br />
|
||||
Dimensions for slot #1 to #3
|
||||
<br />
|
||||
Dimensions taken from Tech Note #28</description>
|
||||
<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-10.287" y1="-0.127" x2="-74.803" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-74.803" y1="-0.127" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-9.652" y1="7.747" x2="-9.652" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-0.127" y1="7.747" x2="-9.652" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-177.927" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-82.5246" y1="-0.127" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-86.8426" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-88.4174" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-88.2142" y1="1.4986" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-88.2396" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-88.2396" y1="6.2484" x2="-86.8172" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-86.8172" y1="6.2484" x2="-87.5284" y2="7.747" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-87.5284" y2="5.5372" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-87.5284" y2="1.9558" width="0" layer="48"/>
|
||||
<wire x1="-86.8426" y1="1.4986" x2="-88.2142" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-75.438" y1="-1.143" x2="-75.438" y2="-8.382" width="0" layer="48"/>
|
||||
<wire x1="-9.652" y1="-0.2286" x2="-9.652" y2="-8.128" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-75.4126" y1="-6.985" x2="-73.025" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-5.715" x2="-73.025" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-8.255" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-12.065" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-12.065" y1="-5.715" x2="-12.065" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-12.065" y1="-8.255" x2="-9.6774" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-177.927" y2="77.597" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="5.715" width="0.1524" layer="21"/>
|
||||
<wire x1="-101.6" y1="2.54" x2="-101.6" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-99.06" y1="2.54" x2="-99.06" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-96.52" y1="2.54" x2="-96.52" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-93.98" y1="2.54" x2="-93.98" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-91.44" y1="2.54" x2="-91.44" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-88.9" y1="2.54" x2="-88.9" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-86.36" y1="2.54" x2="-86.36" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-83.82" y1="2.54" x2="-83.82" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-81.28" y1="2.54" x2="-81.28" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-78.74" y1="2.54" x2="-78.74" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-76.2" y1="2.54" x2="-76.2" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-73.66" y1="2.54" x2="-73.66" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-71.12" y1="2.54" x2="-71.12" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-68.58" y1="2.54" x2="-68.58" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-66.04" y1="2.54" x2="-66.04" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-63.5" y1="2.54" x2="-63.5" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-60.96" y1="2.54" x2="-60.96" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-58.42" y1="2.54" x2="-58.42" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-55.88" y1="2.54" x2="-55.88" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-53.34" y1="2.54" x2="-53.34" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-50.8" y1="2.54" x2="-50.8" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-48.26" y1="2.54" x2="-48.26" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-45.72" y1="2.54" x2="-45.72" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-43.18" y1="2.54" x2="-43.18" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-40.64" y1="2.54" x2="-40.64" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-38.1" y1="2.54" x2="-38.1" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-35.56" y1="2.54" x2="-35.56" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-33.02" y1="2.54" x2="-33.02" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-30.48" y1="2.54" x2="-30.48" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-27.94" y1="2.54" x2="-27.94" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-25.4" y1="2.54" x2="-25.4" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-105.41" y1="-3.81" x2="-16.51" y2="-3.81" width="1.016" layer="34"/>
|
||||
<wire x1="-101.6" y1="2.54" x2="-101.6" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-99.06" y1="2.54" x2="-99.06" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-96.52" y1="2.54" x2="-96.52" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-93.98" y1="2.54" x2="-93.98" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-91.44" y1="2.54" x2="-91.44" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-88.9" y1="2.54" x2="-88.9" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-86.36" y1="2.54" x2="-86.36" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-83.82" y1="2.54" x2="-83.82" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-81.28" y1="2.54" x2="-81.28" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-78.74" y1="2.54" x2="-78.74" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-76.2" y1="2.54" x2="-76.2" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-73.66" y1="2.54" x2="-73.66" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-71.12" y1="2.54" x2="-71.12" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-68.58" y1="2.54" x2="-68.58" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-66.04" y1="2.54" x2="-66.04" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-63.5" y1="2.54" x2="-63.5" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-60.96" y1="2.54" x2="-60.96" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-58.42" y1="2.54" x2="-58.42" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-55.88" y1="2.54" x2="-55.88" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-53.34" y1="2.54" x2="-53.34" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-50.8" y1="2.54" x2="-50.8" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-48.26" y1="2.54" x2="-48.26" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-45.72" y1="2.54" x2="-45.72" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-43.18" y1="2.54" x2="-43.18" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-40.64" y1="2.54" x2="-40.64" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-38.1" y1="2.54" x2="-38.1" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-35.56" y1="2.54" x2="-35.56" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-33.02" y1="2.54" x2="-33.02" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-30.48" y1="2.54" x2="-30.48" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-27.94" y1="2.54" x2="-27.94" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-25.4" y1="2.54" x2="-25.4" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-105.41" y1="-3.81" x2="-16.51" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-0.127" y2="7.778" width="0.2032" layer="21"/>
|
||||
<smd name="26" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<text x="-5.715" y="3.175" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
|
||||
2.950"</text>
|
||||
<text x="-5.715" y="-0.635" size="1.778" layer="27">>VALUE</text>
|
||||
<rectangle x1="-102.362" y1="1.778" x2="-100.838" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-102.362" y1="1.778" x2="-100.838" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-99.822" y1="1.778" x2="-98.298" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-99.822" y1="1.778" x2="-98.298" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-97.282" y1="1.778" x2="-95.758" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-97.282" y1="1.778" x2="-95.758" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-94.742" y1="1.778" x2="-93.218" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-94.742" y1="1.778" x2="-93.218" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-92.202" y1="1.778" x2="-90.678" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-92.202" y1="1.778" x2="-90.678" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-89.662" y1="1.778" x2="-88.138" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-89.662" y1="1.778" x2="-88.138" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-87.122" y1="1.778" x2="-85.598" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-87.122" y1="1.778" x2="-85.598" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-84.582" y1="1.778" x2="-83.058" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-84.582" y1="1.778" x2="-83.058" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-82.042" y1="1.778" x2="-80.518" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-82.042" y1="1.778" x2="-80.518" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-79.502" y1="1.778" x2="-77.978" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-79.502" y1="1.778" x2="-77.978" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-76.962" y1="1.778" x2="-75.438" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-76.962" y1="1.778" x2="-75.438" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-74.422" y1="1.778" x2="-72.898" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-74.422" y1="1.778" x2="-72.898" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-71.882" y1="1.778" x2="-70.358" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-71.882" y1="1.778" x2="-70.358" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-69.342" y1="1.778" x2="-67.818" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-69.342" y1="1.778" x2="-67.818" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-66.802" y1="1.778" x2="-65.278" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-66.802" y1="1.778" x2="-65.278" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-64.262" y1="1.778" x2="-62.738" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-64.262" y1="1.778" x2="-62.738" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-61.722" y1="1.778" x2="-60.198" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-61.722" y1="1.778" x2="-60.198" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-59.182" y1="1.778" x2="-57.658" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-59.182" y1="1.778" x2="-57.658" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-56.642" y1="1.778" x2="-55.118" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-56.642" y1="1.778" x2="-55.118" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-54.102" y1="1.778" x2="-52.578" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-54.102" y1="1.778" x2="-52.578" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-51.562" y1="1.778" x2="-50.038" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-51.562" y1="1.778" x2="-50.038" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-49.022" y1="1.778" x2="-47.498" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-49.022" y1="1.778" x2="-47.498" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-46.482" y1="1.778" x2="-44.958" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-46.482" y1="1.778" x2="-44.958" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-43.942" y1="1.778" x2="-42.418" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-43.942" y1="1.778" x2="-42.418" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-41.402" y1="1.778" x2="-39.878" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-41.402" y1="1.778" x2="-39.878" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-38.862" y1="1.778" x2="-37.338" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-38.862" y1="1.778" x2="-37.338" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-36.322" y1="1.778" x2="-34.798" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-36.322" y1="1.778" x2="-34.798" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-33.782" y1="1.778" x2="-32.258" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-33.782" y1="1.778" x2="-32.258" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-31.242" y1="1.778" x2="-29.718" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-31.242" y1="1.778" x2="-29.718" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-28.702" y1="1.778" x2="-27.178" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-28.702" y1="1.778" x2="-27.178" y2="8.382" layer="33"/>
|
||||
<rectangle x1="-26.162" y1="1.778" x2="-24.638" y2="8.382" layer="34"/>
|
||||
<rectangle x1="-26.162" y1="1.778" x2="-24.638" y2="8.382" layer="33"/>
|
||||
<wire x1="-177.927" y1="77.597" x2="-177.927" y2="7.747" width="0.2032" layer="21"/>
|
||||
</package>
|
||||
<package name="A2-50PIN-SL4-7">
|
||||
<description><B>Apple ][ Peripheral Card</B>
|
||||
<br />
|
||||
Standard 50-pin edge connector for Apple ][ systems
|
||||
<br />
|
||||
Dimensions for slot #4 to #7
|
||||
<br />
|
||||
Dimensions taken from Tech Note #28</description>
|
||||
<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-10.287" y1="-0.127" x2="-74.803" y2="-0.127" width="0.2032" layer="21"/>
|
||||
<wire x1="-74.803" y1="-0.127" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-9.652" y1="7.747" x2="-9.652" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-0.127" y1="7.747" x2="-9.652" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-254.127" y2="7.747" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
|
||||
<wire x1="-82.5246" y1="-0.127" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-86.8426" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-88.4174" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-88.2142" y1="1.4986" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-88.2396" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-88.2396" y1="6.2484" x2="-86.8172" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-86.8172" y1="6.2484" x2="-87.5284" y2="7.747" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="7.747" x2="-87.5284" y2="5.5372" width="0" layer="48"/>
|
||||
<wire x1="-87.5284" y1="-0.127" x2="-87.5284" y2="1.9558" width="0" layer="48"/>
|
||||
<wire x1="-86.8426" y1="1.4986" x2="-88.2142" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-75.438" y1="-1.143" x2="-75.438" y2="-8.382" width="0" layer="48"/>
|
||||
<wire x1="-9.652" y1="-0.2286" x2="-9.652" y2="-8.128" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-75.4126" y1="-6.985" x2="-73.025" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-5.715" x2="-73.025" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-73.025" y1="-8.255" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-9.6774" y1="-6.985" x2="-12.065" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-12.065" y1="-5.715" x2="-12.065" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-12.065" y1="-8.255" x2="-9.6774" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-196.977" y2="77.597" width="0.2032" layer="21"/>
|
||||
<wire x1="-75.438" y1="7.747" x2="-75.438" y2="5.715" width="0.1524" layer="21"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-0.127" y2="7.778" width="0.2032" layer="21"/>
|
||||
<smd name="26" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<text x="-5.715" y="3.175" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
|
||||
2.950"</text>
|
||||
<text x="-5.715" y="-0.635" size="1.778" layer="27">>VALUE</text>
|
||||
<wire x1="-196.977" y1="77.597" x2="-254.127" y2="63.627" width="0.2032" layer="21"/>
|
||||
<wire x1="-254.127" y1="63.627" x2="-254.127" y2="7.747" width="0.2032" layer="21"/>
|
||||
</package>
|
||||
<package name="A2GS-44PIN-MEM">
|
||||
<description><B>Apple IIgs Memory Expansion Card</B>
|
||||
<br />
|
||||
The maximum PCB dimensions for an Apple IIgs Memory Expansion Card
|
||||
<br />
|
||||
Dimensions taken from Tech Note #28</description>
|
||||
<wire x1="-253.238" y1="0.508" x2="-252.603" y2="-0.127" width="0.2032" layer="22"/>
|
||||
<wire x1="-252.603" y1="-0.127" x2="-195.707" y2="-0.127" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.707" y1="-0.127" x2="-195.072" y2="0.508" width="0.2032" layer="22"/>
|
||||
<wire x1="-253.238" y1="7.747" x2="-253.238" y2="0.508" width="0.2032" layer="22"/>
|
||||
<wire x1="-439.293" y1="7.747" x2="-347.472" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-347.472" y1="7.747" x2="-347.472" y2="-8.255" width="0.2032" layer="22"/>
|
||||
<wire x1="-347.472" y1="-8.255" x2="-337.312" y2="-8.255" width="0.2032" layer="22"/>
|
||||
<wire x1="-337.312" y1="-8.255" x2="-337.312" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-337.312" y1="7.747" x2="-253.238" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.072" y1="7.747" x2="-185.293" y2="7.747" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.072" y1="7.747" x2="-195.072" y2="0.508" width="0.2032" layer="22"/>
|
||||
<wire x1="-191.7954" y1="-0.127" x2="-186.7916" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="-0.127" x2="-187.4774" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="-0.127" x2="-185.9026" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-186.1058" y1="1.4986" x2="-186.7916" y2="-0.127" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="7.747" x2="-186.0804" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-186.0804" y1="6.2484" x2="-187.5028" y2="6.2484" width="0" layer="48"/>
|
||||
<wire x1="-187.5028" y1="6.2484" x2="-186.7916" y2="7.747" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="7.747" x2="-186.7916" y2="5.5372" width="0" layer="48"/>
|
||||
<wire x1="-186.7916" y1="-0.127" x2="-186.7916" y2="1.9558" width="0" layer="48"/>
|
||||
<wire x1="-187.4774" y1="1.4986" x2="-186.1058" y2="1.4986" width="0" layer="48"/>
|
||||
<wire x1="-195.072" y1="-1.143" x2="-195.072" y2="-8.382" width="0" layer="48"/>
|
||||
<wire x1="-253.238" y1="-0.2286" x2="-253.238" y2="-8.128" width="0" layer="48"/>
|
||||
<wire x1="-253.2126" y1="-6.985" x2="-195.0974" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-195.0974" y1="-6.985" x2="-197.485" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-197.485" y1="-5.715" x2="-197.485" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-197.485" y1="-8.255" x2="-195.0974" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-253.2126" y1="-6.985" x2="-250.825" y2="-5.715" width="0" layer="48"/>
|
||||
<wire x1="-250.825" y1="-5.715" x2="-250.825" y2="-8.255" width="0" layer="48"/>
|
||||
<wire x1="-250.825" y1="-8.255" x2="-253.2126" y2="-6.985" width="0" layer="48"/>
|
||||
<wire x1="-439.293" y1="77.597" x2="-242.443" y2="77.597" width="0.2032" layer="22"/>
|
||||
<wire x1="-195.072" y1="7.747" x2="-195.072" y2="5.715" width="0.1524" layer="22"/>
|
||||
<wire x1="-439.293" y1="77.597" x2="-439.293" y2="7.778" width="0.2032" layer="22"/>
|
||||
<smd name="23" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="24" x="-248.285" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="25" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="26" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="27" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="28" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="29" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="30" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="31" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="32" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="33" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="34" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="35" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="36" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="37" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="38" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="39" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="40" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="41" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="42" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="43" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="44" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
|
||||
<smd name="22" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="21" x="-248.285" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="20" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="19" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="18" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="17" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="16" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="15" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="14" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="13" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="12" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="11" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="10" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="09" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="08" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="07" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="06" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="05" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="04" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="03" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="02" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<smd name="01" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
|
||||
<text x="-280.035" y="4.445" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-182.3466" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-229.6668" y="-9.2964" size="1.778" layer="48">57,658 mm
|
||||
2.270"</text>
|
||||
<text x="-280.035" y="0.635" size="1.778" layer="27">>VALUE</text>
|
||||
<wire x1="-242.443" y1="77.597" x2="-185.293" y2="63.627" width="0.2032" layer="22"/>
|
||||
<wire x1="-185.293" y1="63.627" x2="-185.293" y2="7.747" width="0.2032" layer="22"/>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="ATPIN">
|
||||
<wire x1="0" y1="0.635" x2="3.175" y2="0.635" width="0.3048" layer="94"/>
|
||||
<wire x1="3.175" y1="0.635" x2="3.175" y2="-0.635" width="0.3048" layer="94"/>
|
||||
<wire x1="3.175" y1="-0.635" x2="0" y2="-0.635" width="0.3048" layer="94"/>
|
||||
<wire x1="0" y1="-0.635" x2="0" y2="0.635" width="0.3048" layer="94"/>
|
||||
<text x="4.445" y="-0.9652" size="1.778" layer="95">>NAME</text>
|
||||
<pin name="P" x="-2.54" y="0" visible="pad" length="short" swaplevel="1"/>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
|
||||
<description><B>Apple ][ Peripheral Card Connector</B>
|
||||
<br />
|
||||
This is the, default, 50-pin connector for slot #1 to #7
|
||||
<br />
|
||||
Pins are laid out as seen from the top of the slot</description>
|
||||
<gates>
|
||||
<gate name="_-12V@2" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
|
||||
<gate name="_D0" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
|
||||
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
|
||||
<gate name="_D2" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
|
||||
<gate name="_D3" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
|
||||
<gate name="_D4" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
|
||||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_-12V@1" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
|
||||
<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
|
||||
<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
<gate name="_A03" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
|
||||
<gate name="_A04" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
|
||||
<gate name="_A05" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
|
||||
<gate name="_A06" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
|
||||
<gate name="_A07" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
|
||||
<gate name="_A08" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
|
||||
<gate name="_A09" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
|
||||
<gate name="_A10" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
|
||||
<gate name="_A11" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
|
||||
<gate name="_A12" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
|
||||
<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
|
||||
<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="SLOT1-3" package="A2-50PIN-SL1-3">
|
||||
<connects>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V@1" pin="P" pad="33"/>
|
||||
<connect gate="_-12V@2" pin="P" pad="50"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
<connect gate="_A02" pin="P" pad="04"/>
|
||||
<connect gate="_A03" pin="P" pad="05"/>
|
||||
<connect gate="_A04" pin="P" pad="06"/>
|
||||
<connect gate="_A05" pin="P" pad="07"/>
|
||||
<connect gate="_A06" pin="P" pad="08"/>
|
||||
<connect gate="_A07" pin="P" pad="09"/>
|
||||
<connect gate="_A08" pin="P" pad="10"/>
|
||||
<connect gate="_A09" pin="P" pad="11"/>
|
||||
<connect gate="_A10" pin="P" pad="12"/>
|
||||
<connect gate="_A11" pin="P" pad="13"/>
|
||||
<connect gate="_A12" pin="P" pad="14"/>
|
||||
<connect gate="_A13" pin="P" pad="15"/>
|
||||
<connect gate="_A14" pin="P" pad="16"/>
|
||||
<connect gate="_A15" pin="P" pad="17"/>
|
||||
<connect gate="_D0" pin="P" pad="49"/>
|
||||
<connect gate="_D1" pin="P" pad="48"/>
|
||||
<connect gate="_D2" pin="P" pad="47"/>
|
||||
<connect gate="_D3" pin="P" pad="46"/>
|
||||
<connect gate="_D4" pin="P" pad="45"/>
|
||||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="SLOT4-7" package="A2-50PIN-SL4-7">
|
||||
<connects>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V@1" pin="P" pad="33"/>
|
||||
<connect gate="_-12V@2" pin="P" pad="50"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
<connect gate="_A02" pin="P" pad="04"/>
|
||||
<connect gate="_A03" pin="P" pad="05"/>
|
||||
<connect gate="_A04" pin="P" pad="06"/>
|
||||
<connect gate="_A05" pin="P" pad="07"/>
|
||||
<connect gate="_A06" pin="P" pad="08"/>
|
||||
<connect gate="_A07" pin="P" pad="09"/>
|
||||
<connect gate="_A08" pin="P" pad="10"/>
|
||||
<connect gate="_A09" pin="P" pad="11"/>
|
||||
<connect gate="_A10" pin="P" pad="12"/>
|
||||
<connect gate="_A11" pin="P" pad="13"/>
|
||||
<connect gate="_A12" pin="P" pad="14"/>
|
||||
<connect gate="_A13" pin="P" pad="15"/>
|
||||
<connect gate="_A14" pin="P" pad="16"/>
|
||||
<connect gate="_A15" pin="P" pad="17"/>
|
||||
<connect gate="_D0" pin="P" pad="49"/>
|
||||
<connect gate="_D1" pin="P" pad="48"/>
|
||||
<connect gate="_D2" pin="P" pad="47"/>
|
||||
<connect gate="_D3" pin="P" pad="46"/>
|
||||
<connect gate="_D4" pin="P" pad="45"/>
|
||||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="A2GSRAM-44PIN" prefix="ST" uservalue="yes">
|
||||
<description><B>Apple IIgs Memory Expansion Slot 44-pin</B>
|
||||
<br />
|
||||
This is the 44-pin board dimensions for an Apple IIgs Memory Expansion Card
|
||||
<br />
|
||||
Pins are laid out as seen from the top of the slot. Pin 1 is towards the front of the case/keyboard</description>
|
||||
<gates>
|
||||
<gate name="_GND@5" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
|
||||
<gate name="_+5V@5" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
|
||||
<gate name="_A13" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
|
||||
<gate name="_A12" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
|
||||
<gate name="_A11" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_A10" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_CRAS\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_GND@4" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_D3" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_ABORT" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_02" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_D4" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_MSIZE" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_CSEL\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_GND@3" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_+5V@4" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_D0" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_GND@1" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_+5V@1" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_FRA9" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_FRA8" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
<gate name="_D2" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
|
||||
<gate name="_FRA6" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
|
||||
<gate name="_FRA3" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
|
||||
<gate name="_FRA4" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
|
||||
<gate name="_FRA5" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
|
||||
<gate name="_FRA7" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
|
||||
<gate name="_+5V@2" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
|
||||
<gate name="_FR/W" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
|
||||
<gate name="_FRA0" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
|
||||
<gate name="_FRA2" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
|
||||
<gate name="_FRA1" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_CCAS\" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_CROW0" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_CROW1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_CROMSEL\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_+5V@3" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_GND@2" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="IIGS-RAM" package="A2GS-44PIN-MEM">
|
||||
<connects>
|
||||
<connect gate="_+5V@1" pin="P" pad="02"/>
|
||||
<connect gate="_+5V@2" pin="P" pad="11"/>
|
||||
<connect gate="_+5V@3" pin="P" pad="21"/>
|
||||
<connect gate="_+5V@4" pin="P" pad="24"/>
|
||||
<connect gate="_+5V@5" pin="P" pad="43"/>
|
||||
<connect gate="_02" pin="P" pad="31"/>
|
||||
<connect gate="_A10" pin="P" pad="37"/>
|
||||
<connect gate="_A11" pin="P" pad="38"/>
|
||||
<connect gate="_A12" pin="P" pad="39"/>
|
||||
<connect gate="_A13" pin="P" pad="40"/>
|
||||
<connect gate="_A14" pin="P" pad="41"/>
|
||||
<connect gate="_A15" pin="P" pad="42"/>
|
||||
<connect gate="_ABORT" pin="P" pad="32"/>
|
||||
<connect gate="_CCAS\" pin="P" pad="17"/>
|
||||
<connect gate="_CRAS\" pin="P" pad="35"/>
|
||||
<connect gate="_CROMSEL\" pin="P" pad="20"/>
|
||||
<connect gate="_CROW0" pin="P" pad="18"/>
|
||||
<connect gate="_CROW1" pin="P" pad="19"/>
|
||||
<connect gate="_CSEL\" pin="P" pad="26"/>
|
||||
<connect gate="_D0" pin="P" pad="25"/>
|
||||
<connect gate="_D1" pin="P" pad="36"/>
|
||||
<connect gate="_D2" pin="P" pad="05"/>
|
||||
<connect gate="_D3" pin="P" pad="33"/>
|
||||
<connect gate="_D4" pin="P" pad="29"/>
|
||||
<connect gate="_D5" pin="P" pad="30"/>
|
||||
<connect gate="_D6" pin="P" pad="28"/>
|
||||
<connect gate="_D7" pin="P" pad="16"/>
|
||||
<connect gate="_FR/W" pin="P" pad="12"/>
|
||||
<connect gate="_FRA0" pin="P" pad="13"/>
|
||||
<connect gate="_FRA1" pin="P" pad="15"/>
|
||||
<connect gate="_FRA2" pin="P" pad="14"/>
|
||||
<connect gate="_FRA3" pin="P" pad="07"/>
|
||||
<connect gate="_FRA4" pin="P" pad="08"/>
|
||||
<connect gate="_FRA5" pin="P" pad="09"/>
|
||||
<connect gate="_FRA6" pin="P" pad="06"/>
|
||||
<connect gate="_FRA7" pin="P" pad="10"/>
|
||||
<connect gate="_FRA8" pin="P" pad="04"/>
|
||||
<connect gate="_FRA9" pin="P" pad="03"/>
|
||||
<connect gate="_GND@1" pin="P" pad="01"/>
|
||||
<connect gate="_GND@2" pin="P" pad="22"/>
|
||||
<connect gate="_GND@3" pin="P" pad="23"/>
|
||||
<connect gate="_GND@4" pin="P" pad="34"/>
|
||||
<connect gate="_GND@5" pin="P" pad="44"/>
|
||||
<connect gate="_MSIZE" pin="P" pad="27"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
<compatibility>
|
||||
<note version="6.3" minversion="6.2.2" severity="warning">
|
||||
Since Version 6.2.2 text objects can contain more than one line,
|
||||
which will not be processed correctly with this version.
|
||||
</note>
|
||||
</compatibility>
|
||||
</eagle>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,2 +0,0 @@
|
|||
C:\sources\AppleIISd\spi6502b.ngc 1494085672
|
||||
OK
|
||||
23
spi6502b.bld
23
spi6502b.bld
|
|
@ -1,23 +0,0 @@
|
|||
Release - ngdbuild G.38
|
||||
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Command Line: ngdbuild -dd _ngo -uc SPI6502B.ucf -p xc9500xl spi6502b.ngc
|
||||
spi6502b.ngd
|
||||
|
||||
Reading NGO file "C:/sources/AppleIISd/spi6502b.ngc" ...
|
||||
Reading component libraries for design expansion...
|
||||
|
||||
Annotating constraints to design from file "SPI6502B.ucf" ...
|
||||
|
||||
Checking timing specifications ...
|
||||
Checking expanded design ...
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 59352 kilobytes
|
||||
|
||||
Writing NGD file "spi6502b.ngd" ...
|
||||
|
||||
Writing NGDBUILD log file "spi6502b.bld"...
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -1 +0,0 @@
|
|||
vhdl work SPI6502B1.1.vhd
|
||||
213
spi6502b.syr
213
spi6502b.syr
|
|
@ -1,213 +0,0 @@
|
|||
Release 6.3.03i - xst G.38
|
||||
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to __projnav
|
||||
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
|
||||
|
||||
--> Parameter xsthdpdir set to ./xst
|
||||
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
|
||||
|
||||
--> Reading design: spi6502b.prj
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Compilation
|
||||
3) HDL Analysis
|
||||
4) HDL Synthesis
|
||||
5) Advanced HDL Synthesis
|
||||
5.1) HDL Synthesis Report
|
||||
6) Low Level Synthesis
|
||||
7) Final Report
|
||||
|
||||
=========================================================================
|
||||
* Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : spi6502b.prj
|
||||
Input Format : mixed
|
||||
Ignore Synthesis Constraint File : NO
|
||||
Verilog Include Directory :
|
||||
|
||||
---- Target Parameters
|
||||
Output File Name : spi6502b
|
||||
Output Format : NGC
|
||||
Target Device : xc9500xl
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : spi6502b
|
||||
Automatic FSM Extraction : YES
|
||||
FSM Encoding Algorithm : Auto
|
||||
Mux Extraction : YES
|
||||
Resource Sharing : YES
|
||||
|
||||
---- Target Options
|
||||
Add IO Buffers : YES
|
||||
Equivalent register Removal : YES
|
||||
MACRO Preserve : YES
|
||||
XOR Preserve : YES
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Speed
|
||||
Optimization Effort : 1
|
||||
Keep Hierarchy : YES
|
||||
RTL Output : Yes
|
||||
Hierarchy Separator : _
|
||||
Bus Delimiter : <>
|
||||
Case Specifier : maintain
|
||||
|
||||
---- Other Options
|
||||
lso : spi6502b.lso
|
||||
verilog2001 : YES
|
||||
Clock Enable : YES
|
||||
wysiwyg : NO
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work.
|
||||
Entity <spi6502b> (Architecture <behavioral>) compiled.
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing Entity <spi6502b> (Architecture <behavioral>).
|
||||
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded
|
||||
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 316: Mux is complete : default of case is discarded
|
||||
Entity <spi6502b> analyzed. Unit <spi6502b> generated.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Synthesizing Unit <spi6502b>.
|
||||
Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd.
|
||||
Found 8-bit tristate buffer for signal <cpu_d>.
|
||||
Found 1-bit tristate buffer for signal <cpu_Nirq>.
|
||||
Found 1-bit tristate buffer for signal <spi_mosi>.
|
||||
Found 1-bit xor3 for signal <$n0040> created at line 206.
|
||||
Found 4-bit adder for signal <$n0047> created at line 160.
|
||||
Found 1-bit register for signal <cpha>.
|
||||
Found 1-bit register for signal <cpol>.
|
||||
Found 3-bit down counter for signal <divcnt>.
|
||||
Found 3-bit register for signal <divisor>.
|
||||
Found 1-bit register for signal <ece>.
|
||||
Found 1-bit register for signal <frx>.
|
||||
Found 1-bit register for signal <ier>.
|
||||
Found 1-bit register for signal <int_mosi>.
|
||||
Found 1-bit register for signal <int_sclk>.
|
||||
Found 4-bit register for signal <shiftcnt>.
|
||||
Found 1-bit register for signal <shiftdone>.
|
||||
Found 1-bit register for signal <shifting2>.
|
||||
Found 1-bit register for signal <slaveinten>.
|
||||
Found 1-bit register for signal <slavesel>.
|
||||
Found 8-bit register for signal <spidatain>.
|
||||
Found 8-bit register for signal <spidataout>.
|
||||
Found 1-bit register for signal <start_shifting>.
|
||||
Found 1-bit register for signal <tc>.
|
||||
Found 1-bit register for signal <tmo>.
|
||||
Found 24 1-bit 2-to-1 multiplexers.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
inferred 20 D-type flip-flop(s).
|
||||
inferred 1 Adder/Subtracter(s).
|
||||
inferred 10 Tristate(s).
|
||||
Unit <spi6502b> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Advanced RAM inference ...
|
||||
Advanced multiplier inference ...
|
||||
Advanced Registered AddSub inference ...
|
||||
Dynamic shift register inference ...
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 1
|
||||
4-bit adder : 1
|
||||
# Registers : 25
|
||||
1-bit register : 22
|
||||
8-bit register : 1
|
||||
3-bit register : 1
|
||||
4-bit register : 1
|
||||
# Multiplexers : 12
|
||||
2-to-1 multiplexer : 12
|
||||
# Tristates : 3
|
||||
1-bit tristate buffer : 2
|
||||
8-bit tristate buffer : 1
|
||||
# Xors : 1
|
||||
1-bit xor3 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Optimizing unit <spi6502b> ...
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : spi6502b.ngr
|
||||
Top Level Output File Name : spi6502b
|
||||
Output Format : NGC
|
||||
Optimization Goal : Speed
|
||||
Keep Hierarchy : YES
|
||||
Target Technology : xc9500xl
|
||||
Macro Preserve : YES
|
||||
XOR Preserve : YES
|
||||
Clock Enable : YES
|
||||
wysiwyg : NO
|
||||
|
||||
Design Statistics
|
||||
# IOs : 23
|
||||
|
||||
Macro Statistics :
|
||||
# Registers : 60
|
||||
# 1-bit register : 60
|
||||
# Tristates : 3
|
||||
# 1-bit tristate buffer : 2
|
||||
# 8-bit tristate buffer : 1
|
||||
# Xors : 5
|
||||
# 1-bit xor2 : 5
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 252
|
||||
# AND2 : 119
|
||||
# AND3 : 5
|
||||
# AND4 : 1
|
||||
# GND : 1
|
||||
# INV : 77
|
||||
# OR2 : 42
|
||||
# OR3 : 1
|
||||
# VCC : 1
|
||||
# XOR2 : 5
|
||||
# FlipFlops/Latches : 37
|
||||
# FD : 1
|
||||
# FDC : 5
|
||||
# FDCE : 27
|
||||
# FDCP : 1
|
||||
# FDP : 1
|
||||
# FDPE : 2
|
||||
# IO Buffers : 23
|
||||
# IBUF : 10
|
||||
# IOBUFE : 8
|
||||
# OBUF : 3
|
||||
# OBUFE : 2
|
||||
=========================================================================
|
||||
CPU : 0.65 / 1.07 s | Elapsed : 0.00 / 1.00 s
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 68376 kilobytes
|
||||
|
||||
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
Release 6.1i - Fit G.38
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
5- 6-2017 5:47PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
character is used as the data field separator.
|
||||
This file is also designed to support parsing.
|
||||
|
||||
Input file: spi6502b.ngd
|
||||
output file: spi6502b_pad.csv
|
||||
Part type: xc9572xl
|
||||
Speed grade: -10
|
||||
Package: pc44
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
|
||||
P1,TIE,,I/O,,,,,,,,,,
|
||||
P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,,
|
||||
P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,,
|
||||
P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,,
|
||||
P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P10,GND,,GND,,,,,,,,,,
|
||||
P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,,
|
||||
P14,cpu_Nirq,O,I/O,OUTPUT,,,,,,,,,
|
||||
P15,TDI,,TDI,,,,,,,,,,
|
||||
P16,TMS,,TMS,,,,,,,,,,
|
||||
P17,TCK,,TCK,,,,,,,,,,
|
||||
P18,Ncs2,I,I/O,INPUT,,,,,,,,,
|
||||
P19,cpu_Nres,I,I/O,INPUT,,,,,,,,,
|
||||
P20,cs1,I,I/O,INPUT,,,,,,,,,
|
||||
P21,VCC,,VCCINT,,,,,,,,,,
|
||||
P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,,
|
||||
P23,GND,,GND,,,,,,,,,,
|
||||
P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,,
|
||||
P25,TIE,,I/O,,,,,,,,,,
|
||||
P26,TIE,,I/O,,,,,,,,,,
|
||||
P27,TIE,,I/O,,,,,,,,,,
|
||||
P28,spi_Nsel,O,I/O,OUTPUT,,,,,,,,,
|
||||
P29,led,O,I/O,OUTPUT,,,,,,,,,
|
||||
P30,TDO,,TDO,,,,,,,,,,
|
||||
P31,GND,,GND,,,,,,,,,,
|
||||
P32,VCC,,VCCIO,,,,,,,,,,
|
||||
P33,TIE,,I/O,,,,,,,,,,
|
||||
P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
|
||||
P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
|
||||
P36,TIE,,I/O,,,,,,,,,,
|
||||
P37,TIE,,I/O,,,,,,,,,,
|
||||
P38,TIE,,I/O,,,,,,,,,,
|
||||
P39,TIE,,I/O/GSR,,,,,,,,,,
|
||||
P40,TIE,,I/O/GTS2,,,,,,,,,,
|
||||
P41,VCC,,VCCINT,,,,,,,,,,
|
||||
P42,spi_int,I,I/O/GTS1,INPUT,,,,,,,,,
|
||||
P43,TIE,,I/O,,,,,,,,,,
|
||||
P44,spi_miso,I,I/O,INPUT,,,,,,,,,
|
||||
|
||||
To preserve the pinout above for future design iterations in
|
||||
Project Navigator simply execute the (Lock Pins) process
|
||||
located under the (Implement Design) process in a toolbox named
|
||||
(Optional Implementation Tools) or invoke PIN2UCF from the
|
||||
command line. The location constraints will be written into your
|
||||
specified UCF file
|
||||
|
||||
|
||||
|
Loading…
Reference in New Issue