GR8RAM/cpld/db/GR8RAM.hier_info

|GR8RAM
C25M => SA[0]~reg0.CLK
C25M => SA[1]~reg0.CLK
C25M => SA[2]~reg0.CLK
C25M => SA[3]~reg0.CLK
C25M => SA[4]~reg0.CLK
C25M => SA[5]~reg0.CLK
C25M => SA[6]~reg0.CLK
C25M => SA[7]~reg0.CLK
C25M => SA[8]~reg0.CLK
C25M => SA[9]~reg0.CLK
C25M => SA[10]~reg0.CLK
C25M => SA[11]~reg0.CLK
C25M => SA[12]~reg0.CLK
C25M => SBA[0]~reg0.CLK
C25M => SBA[1]~reg0.CLK
C25M => DQMH~reg0.CLK
C25M => DQML~reg0.CLK
C25M => SDOE.CLK
C25M => nSWE~reg0.CLK
C25M => nCAS~reg0.CLK
C25M => nRAS~reg0.CLK
C25M => nRCS~reg0.CLK
C25M => RCKE~reg0.CLK
C25M => RDD[0].CLK
C25M => RDD[1].CLK
C25M => RDD[2].CLK
C25M => RDD[3].CLK
C25M => RDD[4].CLK
C25M => RDD[5].CLK
C25M => RDD[6].CLK
C25M => RDD[7].CLK
C25M => WRD[0].CLK
C25M => WRD[1].CLK
C25M => WRD[2].CLK
C25M => WRD[3].CLK
C25M => WRD[4].CLK
C25M => WRD[5].CLK
C25M => WRD[6].CLK
C25M => WRD[7].CLK
C25M => MOSIout.CLK
C25M => FCKOE.CLK
C25M => MOSIOE.CLK
C25M => FCS.CLK
C25M => FCKout.CLK
C25M => Bank.CLK
C25M => AddrIncH.CLK
C25M => AddrIncM.CLK
C25M => AddrIncL.CLK
C25M => Addr[0].CLK
C25M => Addr[1].CLK
C25M => Addr[2].CLK
C25M => Addr[3].CLK
C25M => Addr[4].CLK
C25M => Addr[5].CLK
C25M => Addr[6].CLK
C25M => Addr[7].CLK
C25M => Addr[8].CLK
C25M => Addr[9].CLK
C25M => Addr[10].CLK
C25M => Addr[11].CLK
C25M => Addr[12].CLK
C25M => Addr[13].CLK
C25M => Addr[14].CLK
C25M => Addr[15].CLK
C25M => Addr[16].CLK
C25M => Addr[17].CLK
C25M => Addr[18].CLK
C25M => Addr[19].CLK
C25M => Addr[20].CLK
C25M => Addr[21].CLK
C25M => Addr[22].CLK
C25M => Addr[23].CLK
C25M => REGEN.CLK
C25M => IOROMEN.CLK
C25M => nRESout~reg0.CLK
C25M => LS[0].CLK
C25M => LS[1].CLK
C25M => LS[2].CLK
C25M => LS[3].CLK
C25M => LS[4].CLK
C25M => LS[5].CLK
C25M => LS[6].CLK
C25M => LS[7].CLK
C25M => LS[8].CLK
C25M => LS[9].CLK
C25M => LS[10].CLK
C25M => LS[11].CLK
C25M => LS[12].CLK
C25M => LS[13].CLK
C25M => PS[0].CLK
C25M => PS[1].CLK
C25M => PS[2].CLK
C25M => PS[3].CLK
C25M => SetFWr[0].CLK
C25M => SetFWr[1].CLK
C25M => SetFWLoaded.CLK
C25M => nRESr.CLK
C25M => nRESf[0].CLK
C25M => nRESf[1].CLK
C25M => nRESf[2].CLK
C25M => nRESf[3].CLK
C25M => PHI0r2.CLK
C25M => PHI0r1.CLK
C25M => IS~7.DATAIN
PHI0 => comb.IN1
PHI0 => nWEr.CLK
PHI0 => RAMSpecSELr.CLK
PHI0 => ROMSpecRDr.CLK
PHI0 => PHI0r1.DATAIN
nRES => nRESf[0].DATAIN
nRES => IOROMRES.IN1
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
SetFW[0] => SetFWr[0].DATAIN
SetFW[1] => SetFWr[1].DATAIN
INTin => INTout.DATAIN
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
DMAin => DMAout.DATAIN
DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
nNMIout <= <VCC>
nIRQout <= <VCC>
nRDYout <= <VCC>
nINHout <= <VCC>
RWout <= <VCC>
nDMAout <= <VCC>
RA[0] => DQML.DATAA
RA[0] => Equal10.IN3
RA[0] => Equal11.IN3
RA[0] => Equal12.IN2
RA[0] => Equal13.IN3
RA[0] => Equal14.IN3
RA[0] => Equal15.IN10
RA[0] => DQMH.DATAA
RA[1] => SA.DATAA
RA[1] => Equal10.IN2
RA[1] => Equal11.IN2
RA[1] => Equal12.IN3
RA[1] => Equal13.IN2
RA[1] => Equal14.IN2
RA[1] => Equal15.IN9
RA[2] => SA.DATAA
RA[2] => Equal10.IN1
RA[2] => Equal11.IN1
RA[2] => Equal12.IN1
RA[2] => Equal13.IN1
RA[2] => Equal14.IN1
RA[2] => Equal15.IN8
RA[3] => SA.DATAA
RA[3] => Equal10.IN0
RA[3] => Equal11.IN0
RA[3] => Equal12.IN0
RA[3] => Equal13.IN0
RA[3] => Equal14.IN0
RA[3] => Equal15.IN7
RA[4] => SA.DATAA
RA[4] => Equal15.IN6
RA[5] => SA.DATAA
RA[5] => Equal15.IN5
RA[6] => SA.DATAA
RA[6] => Equal15.IN4
RA[7] => comb.IN1
RA[7] => SA.DATAA
RA[7] => Equal15.IN3
RA[8] => SA.DATAA
RA[8] => Equal9.IN3
RA[8] => Equal15.IN2
RA[9] => SA.DATAA
RA[9] => Equal9.IN2
RA[9] => Equal15.IN1
RA[10] => SA.DATAA
RA[10] => Equal9.IN1
RA[10] => Equal15.IN0
RA[11] => comb.IN1
RA[11] => SA.DATAA
RA[11] => comb.IN1
RA[11] => Equal9.IN0
RA[12] => Equal8.IN1
RA[13] => Equal8.IN0
RA[14] => Equal8.IN3
RA[15] => Equal8.IN2
nWE => comb.IN1
nWE => comb.IN1
nWE => nWEr.DATAIN
RD[0] <> RD[0]
RD[1] <> RD[1]
RD[2] <> RD[2]
RD[3] <> RD[3]
RD[4] <> RD[4]
RD[5] <> RD[5]
RD[6] <> RD[6]
RD[7] <> RD[7]
RAdir <= <VCC>
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
nIOSEL => comb.IN0
nIOSEL => always7.IN1
nDEVSEL => comb.IN1
nDEVSEL => RAMSEL.IN1
nDEVSEL => comb.IN1
nDEVSEL => RAMRegSEL.IN1
nIOSTRB => comb.IN1
nIOSTRB => comb.IN1
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD[0] <> SD[0]
SD[1] <> SD[1]
SD[2] <> SD[2]
SD[3] <> SD[3]
SD[4] <> SD[4]
SD[5] <> SD[5]
SD[6] <> SD[6]
SD[7] <> SD[7]
nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
MISO => WRD.DATAB
MOSI <> MOSI
ugh 2021-03-19 06:56:20 +00:00			`\|GR8RAM`
Works? 2021-04-03 07:44:42 +00:00			`C25M => SA[0]~reg0.CLK`
			`C25M => SA[1]~reg0.CLK`
			`C25M => SA[2]~reg0.CLK`
			`C25M => SA[3]~reg0.CLK`
			`C25M => SA[4]~reg0.CLK`
			`C25M => SA[5]~reg0.CLK`
			`C25M => SA[6]~reg0.CLK`
			`C25M => SA[7]~reg0.CLK`
			`C25M => SA[8]~reg0.CLK`
			`C25M => SA[9]~reg0.CLK`
			`C25M => SA[10]~reg0.CLK`
			`C25M => SA[11]~reg0.CLK`
			`C25M => SA[12]~reg0.CLK`
			`C25M => SBA[0]~reg0.CLK`
			`C25M => SBA[1]~reg0.CLK`
			`C25M => DQMH~reg0.CLK`
			`C25M => DQML~reg0.CLK`
			`C25M => SDOE.CLK`
ugh 2021-03-19 06:56:20 +00:00			`C25M => nSWE~reg0.CLK`
			`C25M => nCAS~reg0.CLK`
			`C25M => nRAS~reg0.CLK`
			`C25M => nRCS~reg0.CLK`
			`C25M => RCKE~reg0.CLK`
Works? 2021-04-03 07:44:42 +00:00			`C25M => RDD[0].CLK`
			`C25M => RDD[1].CLK`
			`C25M => RDD[2].CLK`
			`C25M => RDD[3].CLK`
			`C25M => RDD[4].CLK`
			`C25M => RDD[5].CLK`
			`C25M => RDD[6].CLK`
			`C25M => RDD[7].CLK`
			`C25M => WRD[0].CLK`
			`C25M => WRD[1].CLK`
			`C25M => WRD[2].CLK`
			`C25M => WRD[3].CLK`
			`C25M => WRD[4].CLK`
			`C25M => WRD[5].CLK`
ugh 2021-03-19 06:56:20 +00:00			`C25M => WRD[6].CLK`
			`C25M => WRD[7].CLK`
			`C25M => MOSIout.CLK`
Make apple boot Apple boots but SDRAM not working. Register R/W/increment works 2021-04-18 07:54:45 +00:00			`C25M => FCKOE.CLK`
Works? 2021-04-03 07:44:42 +00:00			`C25M => MOSIOE.CLK`
better 2021-03-19 10:45:31 +00:00			`C25M => FCS.CLK`
Make apple boot Apple boots but SDRAM not working. Register R/W/increment works 2021-04-18 07:54:45 +00:00			`C25M => FCKout.CLK`
Works? 2021-04-03 07:44:42 +00:00			`C25M => Bank.CLK`
			`C25M => AddrIncH.CLK`
			`C25M => AddrIncM.CLK`
			`C25M => AddrIncL.CLK`
ugh 2021-03-19 06:56:20 +00:00			`C25M => Addr[0].CLK`
			`C25M => Addr[1].CLK`
			`C25M => Addr[2].CLK`
			`C25M => Addr[3].CLK`
			`C25M => Addr[4].CLK`
			`C25M => Addr[5].CLK`
			`C25M => Addr[6].CLK`
			`C25M => Addr[7].CLK`
			`C25M => Addr[8].CLK`
			`C25M => Addr[9].CLK`
			`C25M => Addr[10].CLK`
			`C25M => Addr[11].CLK`
			`C25M => Addr[12].CLK`
			`C25M => Addr[13].CLK`
			`C25M => Addr[14].CLK`
			`C25M => Addr[15].CLK`
			`C25M => Addr[16].CLK`
			`C25M => Addr[17].CLK`
			`C25M => Addr[18].CLK`
			`C25M => Addr[19].CLK`
			`C25M => Addr[20].CLK`
			`C25M => Addr[21].CLK`
			`C25M => Addr[22].CLK`
			`C25M => Addr[23].CLK`
better 2021-03-19 10:45:31 +00:00			`C25M => REGEN.CLK`
			`C25M => IOROMEN.CLK`
ugh 2021-03-19 06:56:20 +00:00			`C25M => nRESout~reg0.CLK`
			`C25M => LS[0].CLK`
			`C25M => LS[1].CLK`
			`C25M => LS[2].CLK`
			`C25M => LS[3].CLK`
			`C25M => LS[4].CLK`
			`C25M => LS[5].CLK`
			`C25M => LS[6].CLK`
			`C25M => LS[7].CLK`
			`C25M => LS[8].CLK`
			`C25M => LS[9].CLK`
			`C25M => LS[10].CLK`
			`C25M => LS[11].CLK`
			`C25M => LS[12].CLK`
			`C25M => LS[13].CLK`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`C25M => PS[0].CLK`
			`C25M => PS[1].CLK`
			`C25M => PS[2].CLK`
			`C25M => PS[3].CLK`
			`C25M => SetFWr[0].CLK`
			`C25M => SetFWr[1].CLK`
			`C25M => SetFWLoaded.CLK`
ugh 2021-03-19 06:56:20 +00:00			`C25M => nRESr.CLK`
Works better? 2021-04-20 08:10:26 +00:00			`C25M => nRESf[0].CLK`
			`C25M => nRESf[1].CLK`
			`C25M => nRESf[2].CLK`
			`C25M => nRESf[3].CLK`
ugh 2021-03-19 06:56:20 +00:00			`C25M => PHI0r2.CLK`
			`C25M => PHI0r1.CLK`
Sorta works 2021-04-18 10:01:08 +00:00			`C25M => IS~7.DATAIN`
better 2021-03-19 10:45:31 +00:00			`PHI0 => comb.IN1`
idk 2021-04-11 19:39:19 +00:00			`PHI0 => nWEr.CLK`
			`PHI0 => RAMSpecSELr.CLK`
Sorta works 2021-04-18 10:01:08 +00:00			`PHI0 => ROMSpecRDr.CLK`
Works? 2021-04-03 07:44:42 +00:00			`PHI0 => PHI0r1.DATAIN`
Works better? 2021-04-20 08:10:26 +00:00			`nRES => nRESf[0].DATAIN`
Sorta works 2021-04-19 06:57:51 +00:00			`nRES => IOROMRES.IN1`
better 2021-03-19 10:45:31 +00:00			`nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`SetFW[0] => SetFWr[0].DATAIN`
			`SetFW[1] => SetFWr[1].DATAIN`
Make apple boot Apple boots but SDRAM not working. Register R/W/increment works 2021-04-18 07:54:45 +00:00			`INTin => INTout.DATAIN`
			`INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE`
			`DMAin => DMAout.DATAIN`
			`DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE`
			`nNMIout <= <VCC>`
			`nIRQout <= <VCC>`
			`nRDYout <= <VCC>`
			`nINHout <= <VCC>`
			`RWout <= <VCC>`
Sorta works 2021-04-19 06:57:51 +00:00			`nDMAout <= <VCC>`
Works? 2021-04-03 07:44:42 +00:00			`RA[0] => DQML.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[0] => Equal10.IN3`
Sorta works 2021-04-19 06:57:51 +00:00			`RA[0] => Equal11.IN3`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[0] => Equal12.IN2`
			`RA[0] => Equal13.IN3`
			`RA[0] => Equal14.IN3`
			`RA[0] => Equal15.IN10`
Works? 2021-04-03 07:44:42 +00:00			`RA[0] => DQMH.DATAA`
			`RA[1] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[1] => Equal10.IN2`
Sorta works 2021-04-19 06:57:51 +00:00			`RA[1] => Equal11.IN2`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[1] => Equal12.IN3`
			`RA[1] => Equal13.IN2`
			`RA[1] => Equal14.IN2`
			`RA[1] => Equal15.IN9`
Works? 2021-04-03 07:44:42 +00:00			`RA[2] => SA.DATAA`
Sorta works 2021-04-19 06:57:51 +00:00			`RA[2] => Equal10.IN1`
			`RA[2] => Equal11.IN1`
Make apple boot Apple boots but SDRAM not working. Register R/W/increment works 2021-04-18 07:54:45 +00:00			`RA[2] => Equal12.IN1`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[2] => Equal13.IN1`
			`RA[2] => Equal14.IN1`
			`RA[2] => Equal15.IN8`
Works? 2021-04-03 07:44:42 +00:00			`RA[3] => SA.DATAA`
Sorta works 2021-04-19 06:57:51 +00:00			`RA[3] => Equal10.IN0`
			`RA[3] => Equal11.IN0`
Make apple boot Apple boots but SDRAM not working. Register R/W/increment works 2021-04-18 07:54:45 +00:00			`RA[3] => Equal12.IN0`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[3] => Equal13.IN0`
			`RA[3] => Equal14.IN0`
			`RA[3] => Equal15.IN7`
Works? 2021-04-03 07:44:42 +00:00			`RA[4] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[4] => Equal15.IN6`
Works? 2021-04-03 07:44:42 +00:00			`RA[5] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[5] => Equal15.IN5`
Works? 2021-04-03 07:44:42 +00:00			`RA[6] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[6] => Equal15.IN4`
Works? 2021-04-03 07:44:42 +00:00			`RA[7] => comb.IN1`
			`RA[7] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[7] => Equal15.IN3`
Works? 2021-04-03 07:44:42 +00:00			`RA[8] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[8] => Equal9.IN3`
			`RA[8] => Equal15.IN2`
Works? 2021-04-03 07:44:42 +00:00			`RA[9] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[9] => Equal9.IN2`
			`RA[9] => Equal15.IN1`
Works? 2021-04-03 07:44:42 +00:00			`RA[10] => SA.DATAA`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[10] => Equal9.IN1`
			`RA[10] => Equal15.IN0`
Added CKE back 2021-04-19 00:24:58 +00:00			`RA[11] => comb.IN1`
Works? 2021-04-03 07:44:42 +00:00			`RA[11] => SA.DATAA`
Added CKE back 2021-04-19 00:24:58 +00:00			`RA[11] => comb.IN1`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`RA[11] => Equal9.IN0`
			`RA[12] => Equal8.IN1`
			`RA[13] => Equal8.IN0`
			`RA[14] => Equal8.IN3`
			`RA[15] => Equal8.IN2`
Added CKE back 2021-04-19 00:24:58 +00:00			`nWE => comb.IN1`
better 2021-03-19 10:45:31 +00:00			`nWE => comb.IN1`
Works? 2021-04-03 07:44:42 +00:00			`nWE => nWEr.DATAIN`
ugh 2021-03-19 06:56:20 +00:00			`RD[0] <> RD[0]`
			`RD[1] <> RD[1]`
			`RD[2] <> RD[2]`
			`RD[3] <> RD[3]`
			`RD[4] <> RD[4]`
			`RD[5] <> RD[5]`
			`RD[6] <> RD[6]`
			`RD[7] <> RD[7]`
Sorta works 2021-04-19 06:57:51 +00:00			`RAdir <= <VCC>`
better 2021-03-19 10:45:31 +00:00			`RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE`
Sorta works 2021-04-19 06:57:51 +00:00			`nIOSEL => comb.IN0`
Latch config DIP switches at boot Also rearranged GR8RAM.v 2021-04-20 08:23:57 +00:00			`nIOSEL => always7.IN1`
Sorta works 2021-04-19 06:57:51 +00:00			`nDEVSEL => comb.IN1`
			`nDEVSEL => RAMSEL.IN1`
			`nDEVSEL => comb.IN1`
			`nDEVSEL => RAMRegSEL.IN1`
			`nIOSTRB => comb.IN1`
			`nIOSTRB => comb.IN1`
Works? 2021-04-03 07:44:42 +00:00			`SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
ugh 2021-03-19 06:56:20 +00:00			`nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE`
Works? 2021-04-03 07:44:42 +00:00			`DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE`
ugh 2021-03-19 06:56:20 +00:00			`RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE`
			`SD[0] <> SD[0]`
			`SD[1] <> SD[1]`
			`SD[2] <> SD[2]`
			`SD[3] <> SD[3]`
			`SD[4] <> SD[4]`
			`SD[5] <> SD[5]`
			`SD[6] <> SD[6]`
			`SD[7] <> SD[7]`
Make apple boot Apple boots but SDRAM not working. Register R/W/increment works 2021-04-18 07:54:45 +00:00			`nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE`
			`FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE`
Works? 2021-04-03 07:44:42 +00:00			`MISO => WRD.DATAB`
			`MOSI <> MOSI`
hmm 2021-03-19 10:59:22 +00:00