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Zane Kaminski 2021-03-19 06:45:31 -04:00
parent 72851cefc5
commit 4defba0f50
48 changed files with 1724 additions and 2128 deletions
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161
Documentation/Initialization Sequence
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@ -1,164 +1,3 @@
Init sequence
Init State SDRAM Flash IS Other
--------------------------------------------------------------------------------
$000000-$0FFFBF Wait for Vcc Wait for Vcc 0
$000000 NOP CKE /CS hi, CLK lo
...
$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
....
$0FFFA0 NOP CKE /CS lo, CLK lo
...
$0FFFAF NOP CKE /CS lo, CLK lo
$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03) 1
$0FFFB0 NOP CKE CLK lo, MOSI 0 (b7)
$0FFFB1 NOP CKE CLK hi
$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6)
$0FFFB3 PC all CLK hi
$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5)
$0FFFB5 NOP CKE CLK hi
$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4)
$0FFFB7 NOP CKE CLK hi
$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3)
$0FFFB9 NOP CKE CLK hi
$0FFFBA NOP CKE CLK lo, MOSI 0 (b2)
$0FFFBB Load mode CLK hi
$0FFFBC NOP CKE CLK lo, MOSI 1 (b1)
$0FFFBD NOP CKE CLK hi
$0FFFBE NOP CKE CLK lo, MOSI 1 (b0)
$0FFFBF NOP CKE CLK hi
$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000) 2
$0FFFC0 NOP CKE CLK lo, MOSI 0 (b23)
$0FFFC1 NOP CKE CLK hi
$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22)
$0FFFC3 AREF CLK hi
$0FFFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
$0FFFC5 NOP CKE CLK hi
$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
$0FFFC7 NOP CKE CLK hi
$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19)
$0FFFC9 NOP CKE CLK hi
$0FFFCA NOP CKE CLK lo, MOSI 0 (b18)
$0FFFCB AREF CLK hi
$0FFFCC NOP CKE CLK lo, MOSI 0 (b17)
$0FFFCD NOP CKE CLK hi
$0FFFCE NOP CKE CLK lo, MOSI 0 (b16)
$0FFFCF NOP CKE CLK hi
$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15)
$0FFFD1 NOP CKE CLK hi
$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14)
$0FFFD3 AREF CLK hi
$0FFFD4 NOP CKE CLK lo, MOSI 0 (b13)
$0FFFD5 NOP CKE CLK hi
$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12)
$0FFFD7 NOP CKE CLK hi
$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11)
$0FFFD9 NOP CKE CLK hi
$0FFFDA NOP CKE CLK lo, MOSI 0 (b10)
$0FFFDB AREF CLK hi
$0FFFDC NOP CKE CLK lo, MOSI 0 (b9)
$0FFFDD NOP CKE CLK hi
$0FFFDE NOP CKE CLK lo, MOSI 0 (b8)
$0FFFDF NOP CKE CLK hi
$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7)
$0FFFE1 NOP CKE CLK hi
$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6)
$0FFFE3 AREF CLK hi
$0FFFE4 NOP CKE CLK lo, MOSI 0 (b5)
$0FFFE5 NOP CKE CLK hi
$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4)
$0FFFE7 NOP CKE CLK hi
$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3)
$0FFFE9 NOP CKE CLK hi
$0FFFEA NOP CKE CLK lo, MOSI 0 (b2)
$0FFFEB AREF CLK hi
$0FFFEC NOP CKE CLK lo, MOSI 0 (b1)
$0FFFED NOP CKE CLK hi
$0FFFEE NOP CKE CLK lo, MOSI 0 (b0)
$0FFFEF NOP CKE CLK hi
$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks 2
$0FFFF0 NOP CKE CLK lo, MOSIOE 0
$0FFFF1 NOP CKE CLK hi
$0FFFF2 NOP CKE CLK lo
$0FFFF3 AREF CLK hi
$0FFFF4 NOP CKE CLK lo
$0FFFF5 NOP CKE CLK hi
$0FFFF6 NOP CKE CLK lo
$0FFFF7 NOP CKE CLK hi
$0FFFF8 NOP CKE CLK lo
$0FFFF9 NOP CKE CLK hi
$0FFFFA NOP CKE CLK lo
$0FFFFB AREF CLK hi
$0FFFFC NOP CKE CLK lo
$0FFFFD NOP CKE CLK hi
$0FFFFE NOP CKE CLK lo
$0FFFFF NOP CKE CLK hi
$100000-$503FFF Write ROM data Shift in read data 3
$100000 NOP CKE CLK lo
$100001 NOP CKE CLK hi, get b7:6 of $000000
$100002 NOP CKE CLK lo
$100003 AREF CLK hi, get b5:4 of $000000
$100004 NOP CKE CLK lo
$100005 ACT CLK hi, get b3:2 of $000000
$100006 NOP CKE CLK lo
$100007 WR AP CLK hi, get b1:0 of $000000
$100008 NOP CKE CLK lo
$100009 NOP CKE CLK hi, get b7:6 of $000001
$10000A NOP CKE CLK lo
$10000B AREF CLK hi, get b5:4 of $000001
$10000C NOP CKE CLK lo
$10000D ACT CLK hi, get b3:2 of $000001
$10000E NOP CKE CLK lo
$10000F WR AP CLK hi, get b1:0 of $000001
...
$503FF0 NOP CKE CLK lo
$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE
$503FF2 NOP CKE CLK lo
$503FF3 AREF CLK hi, get b5:4 of $0807FE
$503FF4 NOP CKE CLK lo
$503FF5 ACT CLK hi, get b3:2 of $0807FE
$503FF6 NOP CKE CLK lo
$503FF7 WR AP CLK hi, get b1:0 of $0807FE
$503FF8 NOP CKE CLK lo
$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF
$503FFA NOP CKE CLK lo
$503FFB AREF CLK hi, get b5:4 of $0807FF
$503FFC NOP CKE CLK lo
$503FFD ACT CLK hi, get b3:2 of $0807FF
$503FFE NOP CKE CLK lo
$503FFF WR AP CLK hi, get b1:0 of $0807FF
$504000 NOP CKE CLK lo, /CS hi 3
$504001 NOP CKE CLK lo, /CS hi 3
$504002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
...
$5F5E0F flip 1hz, wrap
Init sequence Init sequence
Init State SDRAM Flash IS Other Init State SDRAM Flash IS Other

7
Documentation/Settings
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@ -1,7 +1,6 @@
GR8RAM Settings (not applicable to Library Card!) GR8RAM Settings (not applicable to Library Card!)
Settings[15] SetValid (1 = invalid, 0 = valid) Settings[15] SetValid (1 = invalid, 0 = valid)
Settings[14] SetFW[1] (1 = RAMFactor, 0 = Slinky) Settings[14] SetFW (1 = RAMFactor, 0 = Slinky)
Settings[13] SetFW[0] Settings[13] SetLim8M
Settings[12] SetLim8M Settings[12:0] Reserved
Settings[11:0] Reserved

76
Documentation/UFM Load
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@ -78,62 +78,30 @@ $1004 0 0 1 1 SetLoaded <= Dout
$1005 0 0 1 1 $1005 0 0 1 1
$1006 0 0 0 1 $1006 0 0 0 1
$1007 0 0 0 1 $1007 0 0 0 1
$1008 0 0 1 1 latch DR[14] (nSetFW[1]) $1008 0 0 1 1 latch DR[14] (SetFW)
$1009 0 0 1 1 $1009 0 0 1 1
$100A 0 0 0 1 $100A 0 0 0 1
$100B 0 0 0 1 $100B 0 0 0 1
$100C 0 0 1 1 latch DR[13] (nSetFW[0]) $100C 1 0 0 1 latch DR[13] (SetLim8M)
$100D 0 0 1 1 $100D 1 0 0 1
$100E 0 0 0 1 $100E 0 0 0 0
$100F 0 0 0 1 $100F 0 0 0 0
$1010 0 0 0 1 latch DR[12] (nSetLim8M)
$1011 0 0 0 1
$1012 0 0 0 1
$1013 0 0 0 1
$1014 0 0 0 1
$1015 0 0 0 1
$1016 0 0 0 1
$1017 0 0 0 1
$1018 0 0 0 1
$1019 0 0 0 1
$101A 0 0 0 1
$101B 0 0 0 1
$101C 1 0 0 1 Increment address
$101D 1 0 0 1
$101E 0 0 0 1
$101F 0 0 0 1
... ...
$2FE0 0 0 1 0 parallel load into DR $1FF0 0 0 1 0 parallel load into DR
$2FE1 0 0 1 0 $1FF1 0 0 1 0
$2FE2 0 0 0 1 $1FF2 0 0 0 1
$2FE3 0 0 0 1 $1FF3 0 0 0 1
$2FE4 0 0 1 1 SetLoaded <= Dout $1FF4 0 0 1 1 SetLoaded <= Dout
$2FE5 0 0 1 1 $1FF5 0 0 1 1
$2FE6 0 0 0 1 $1FF6 0 0 0 1
$2FE7 0 0 0 1 $1FF7 0 0 0 1
$2FE8 0 0 1 1 latch DR[14] (nSetFW[1]) $1FF8 0 0 1 1 latch DR[14] (SetFW)
$2FE9 0 0 1 1 $1FF9 0 0 1 1
$2FEA 0 0 0 1 $1FFA 0 0 0 1
$2FEB 0 0 0 1 $1FFB 0 0 0 1
$2FEC 0 0 1 1 latch DR[13] (nSetFW[0]) $1FFC 1 0 0 1 latch DR[13] (SetLim8M)
$2FED 0 0 1 1 $1FFD 1 0 0 1
$2FEE 0 0 0 1 $1FFE 0 0 0 0
$2FEF 0 0 0 1 $1FFF 0 0 0 0
$2FF0 0 0 0 1 latch DR[12] (nSetLim8M)
$2FF1 0 0 0 1
$2FF2 0 0 0 1
$2FF3 0 0 0 1
$2FF4 0 0 0 1
$2FF5 0 0 0 1
$2FF6 0 0 0 1
$2FF7 0 0 0 1
$2FF8 0 0 0 1
$2FF9 0 0 0 1
$2FFA 0 0 0 1
$2FFB 0 0 0 1
$2FFC 1 0 0 1 Increment address
$2FFD 1 0 0 1
$2FFE 0 0 0 1
$2FFF 0 0 0 1
$3000 0 0 0 0 Everything 0, set SetLoaded $2000 0 0 0 0 Everything 0, set SetLoaded

613
cpld/GR8RAM.v
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@ -1,8 +1,6 @@
module GR8RAM(C25M, PHI0, nBOD, nRES, module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout,
nIOSEL, nDEVSEL, nIOSTRB, nIOSEL, nDEVSEL, nIOSTRB,
RA, nWE, RAdir, RA, nWE, RAdir, RD, RDdir,
RD, RDdir,
DMAin, DMAout, INTin, INTout, nRESout,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI); nFCS, FCK, MISO, MOSI);
@ -14,50 +12,46 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end
/* Reset/brown-out detect synchronized inputs */ /* Reset/brown-out detect synchronized inputs */
/* Outputs: nRESr, nPBODr, nBODf */ /* Outputs: nRESr, nBODf */
input nRES, nBOD; input nRES, nBOD;
reg nRESr0, nRESr; reg nRESr0, nRESr;
reg nBODr0, nBODr, nBODf0, nBODf; reg nBODr0, nBODr, nBODf0, nBODf;
always @(negedge C25M) begin nBODr0 <= nBOD; nRESr0 <= nRES; end
always @(posedge C25M) begin nBODr <= nBODr0; nRESr <= nRESr0; end
always @(posedge C25M) begin always @(posedge C25M) begin
// Double-synchronize nBOD, nPBOD, nRES
nBODr0 <= nBOD; nRESr0 <= nRES;
nBODr <= nBODr0; nRESr <= nRESr0;
// Filter nBODr to get nBODf. Output hi when hi for $10000 cycles // Filter nBODr to get nBODf. Output hi when hi for $10000 cycles
if (LS[15:0]==16'hFFFF) begin // When LS low-order is $FFFF if (LS[15:0]==16'hFF00) begin // When LS low-order is $FFF0
nBODf0 <= nBODr; // "Precharge" nBODf0 nBODf0 <= nBODr; // "Precharge" nBODf0
nBODf <= nBODf0; // "Evaluate" computed nBODf0 into nBODf nBODf <= nBODf0; // Move computed nBODf0 into nBODf
end else if (nBODr) begin // Else AND nBODf0 with nBODr end else if (nBODr) begin // Else AND nBODf0 with nBODr
nBODf0 <= nBODf0 && nBODr; nBODf0 <= nBODf0 && nBODr; // "Evaluate" by ANDing
end end
end end
/* Long state counter: counts from 0 to $3FFFF */ /* Long state counter: counts from 0 to $3FFFF */
/* Outputs: LS, CSec */ /* Outputs: LS */
reg [17:0] LS = 0; reg [17:0] LS = 0;
always @(posedge C25M) begin always @(posedge C25M) begin LS <= LS+1; end
LS <= LS+1;
end
/* Init state */ /* Init state */
output reg nRESout = 0; output reg nRESout = 0;
reg InitActv = 0; reg InitActv = 0;
reg InitIntr = 0; reg InitIntr = 0;
reg CmdActv = 0;
reg SDRAMActv = 0; reg SDRAMActv = 0;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~nBODf) begin if (~nBODf) begin
nRESout <= 0; nRESout <= 0;
InitIntr <= 1; InitIntr <= 1;
CmdActv <= 0; end else if (~nRESr && LS[17:0]==18'h0FF00) begin
end else if (LS[17:0]==18'h0FF10) begin nRESout <= 0;
InitActv <= ~CmdActv; InitActv <= 1;
InitIntr <= 0; InitIntr <= 0;
end else if (LS[17:0]==18'h30010) begin end else if (LS[17:0]==18'h30002) begin
nRESout <= InitActv && ~InitIntr;
InitActv <= 0; InitActv <= 0;
CmdActv <= InitActv && ~InitIntr; if (InitActv && ~InitIntr) begin
if (InitActv && ~InitIntr) SDRAMActv <= 1; SDRAMActv <= 1;
nRESout <= 1;
end
end end
end end
@ -74,11 +68,6 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
DEVSELr <= DEVSELr0; IOSELr <= IOSELr0; IOSTRBr <= IOSTRBr0; DEVSELr <= DEVSELr0; IOSELr <= IOSELr0; IOSTRBr <= IOSTRBr0;
end end
/* DMA/IRQ daisy chain */
input DMAin, INTin;
output DMAout = DMAin;
output INTout = INTin;
/* Apple address bus */ /* Apple address bus */
/* Outputs: RACr, RAcur, nWEcur, RAdir */ /* Outputs: RACr, RAcur, nWEcur, RAdir */
input [15:0] RA; input [15:0] RA;
@ -87,7 +76,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
reg [11:0] RAcur; reg nWEcur; reg [11:0] RAcur; reg nWEcur;
output RAdir = 1; output RAdir = 1;
always @(posedge C25M) begin always @(posedge C25M) begin
if (S==0 && PHI0r1 && ~PHI0r2) begin if (PSStart) begin
RACr <= RA[15:12]==4'hC; RACr <= RA[15:12]==4'hC;
RAcur[11:0] <= RA[11:0]; RAcur[11:0] <= RA[11:0];
nWEcur <= nWE; nWEcur <= nWE;
@ -95,17 +84,11 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
end end
/* Apple select signals */ /* Apple select signals */
/* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR, RAMSEL */ /* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR */
wire ROMSpecRD = RACr && RAcur[11:8]!=4'h0 && nWEcur; wire ROMSpecRD = RACr && RAcur[11:8]!=4'h0 && nWEcur;
wire RAMSpecSEL = RACr && RAcur[11:8]==4'h0 && RAcur[3:0]==4'h3; wire RAMSpecSEL = RACr && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[3:0]==4'h3;
wire RAMSpecRD = RAMSpecSEL && nWEcur; wire RAMSpecRD = RAMSpecSEL && nWEcur;
wire RAMSpecWR = RAMSpecSEL && ~nWEcur; wire RAMSpecWR = RAMSpecSEL && ~nWEcur;
reg RAMSEL = 0;
wire RAMWR = RAMSEL && ~nWEcur;
always @(posedge C25M) begin
if (S==5) RAMSEL <= RAMSpecSEL && DEVSELr;
else if (S==0) RAMSEL <= 0;
end
/* IOROMEN and REGEN control */ /* IOROMEN and REGEN control */
reg IOROMEN = 0; reg IOROMEN = 0;
@ -114,9 +97,9 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
if (~nRESr) begin if (~nRESr) begin
IOROMEN <= 0; IOROMEN <= 0;
REGEN <= 0; REGEN <= 0;
end else if (S==7 && IOSTRBr && RAcur[10:0]==11'h7FF) begin end else if (PS==7 && IOSTRBr && RAcur[10:0]==11'h7FF) begin
IOROMEN <= 0; IOROMEN <= 0;
end else if (S==7 && IOSELr) begin end else if (PS==7 && IOSELr) begin
IOROMEN <= 1; IOROMEN <= 1;
REGEN <= 1; REGEN <= 1;
end end
@ -125,9 +108,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
/* Apple data bus */ /* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0]; inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
reg [7:0] RDout; reg [7:0] RDout;
reg RDOE = 0; output RDdir = ~(PHI0 && PHI0r2 && nWE && nRESr &&
output RDdir = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)) && ((~nDEVSEL && REGEN) || ~nIOSEL || (~nIOSTRB && IOROMEN)));
PHI0 && PHI0r2 && nWE && RDOE && nBODf);
/* Slinky address registers */ /* Slinky address registers */
reg [23:0] Addr = 0; reg [23:0] Addr = 0;
@ -138,26 +120,25 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
if (~nRESr) begin if (~nRESr) begin
Addr[23:20] <= SetFW[1] ? 4'h0 : 4'hF; Addr[23:20] <= SetFW[1] ? 4'h0 : 4'hF;
Addr[19:0] <= 20'h00000; Addr[19:0] <= 20'h00000;
end else if (S==7 && DEVSELr) begin end else if (PS==7 && REGEN && DEVSELr) begin
if (AddrHSpecSEL && ~nWEcur) begin if (RAMSpecSEL) begin
Addr[23:16] <= { SetFW[1] ? RD[7:4] : 4'hF, RD[3:0] }; if (SetFW[1]) Addr[23:0] <= Addr[23:0]+1;
end else if ((RAMSEL && Addr[15:0]==16'hFFFF) || else Addr[23:0] <= { 4'hF, Addr[19:0]+1 };
(AddrMSpecSEL && Addr[15] && ~RD[7] && ~nWEcur) || end else if (AddrLSpecSEL && ~nWEcur) begin
(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF && ~nWEcur)) begin
Addr[23:16] <= Addr[23:16]+1;
end
if (AddrMSpecSEL && ~nWEcur) begin
Addr[15:8] <= RD[7:0];
end else if ((RAMSEL && Addr[7:0]==8'hFF) ||
(AddrLSpecSEL && Addr[7] && ~RD[7] && ~nWEcur)) begin
Addr[15:8] <= Addr[15:8]+1;
end
if (AddrLSpecSEL && ~nWEcur) begin
Addr[7:0] <= RD[7:0]; Addr[7:0] <= RD[7:0];
end else if (RAMSEL) begin if (~RD[7] && Addr[7]) begin
Addr[7:0] <= Addr[7:0]+1; if (SetFW[1]) Addr[23:8] <= Addr[23:8]+1;
else Addr[23:8] <= { 4'hF, Addr[19:8]+1 };
end
end else if (AddrMSpecSEL && ~nWEcur) begin
Addr[15:8] <= RD[7:0];
if (~RD[7] && Addr[15]) begin
if (SetFW[1]) Addr[23:16] <= Addr[23:16]+1;
else Addr[23:16] <= { 4'hF, Addr[19:16]+1 };
end
end else if (AddrHSpecSEL && ~nWEcur) begin
if (SetFW[1]) Addr[23:16] <= RD[7:0];
else Addr[23:16] <= { 4'hF, RD[3:0] };
end end
end end
end end
@ -166,9 +147,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
reg [1:0] Bank = 0; reg [1:0] Bank = 0;
wire BankSpecSEL = RAcur[3:0]==4'hF; wire BankSpecSEL = RAcur[3:0]==4'hF;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~nRESr) begin if (~nRESr) Bank <= 0;
Bank <= 0; else if (PS==7 && DEVSELr && BankSpecSEL && ~nWEcur) begin
end else if (S==7 && DEVSELr && BankSpecSEL && ~nWEcur) begin
Bank[1:0] <= RD[1:0]; Bank[1:0] <= RD[1:0];
end end
end end
@ -185,35 +165,35 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
/* SPI flash control */ /* SPI flash control */
always @(posedge C25M) begin always @(posedge C25M) begin
FCK <= FCKEN && LS[0]; FCK <= (FCKEN && LS[0]) || (nRESr && FCKEN);
end end
always @(posedge C25M) begin always @(posedge C25M) begin
if (InitActv) begin if (InitActv) begin
// Pulse clock from init states $0FFC0 to $2FFFF
if (LS[17:0]==18'h0FFB0) FCKEN <= 1'b0;
else if (LS[17:0]==18'h0FFC0) FCKEN <= 1'b1;
else if (LS[17:0]==18'h30000) FCKEN <= 1'b0;
// Flash /CS enabled from init states $0FFB0 to $2FFFF // Flash /CS enabled from init states $0FFB0 to $2FFFF
if (LS[17:0]==18'h0FFA0) FCS <= 1'b0; if (LS[17:0]==18'h0FF90) FCS <= 1'b0;
else if (LS[17:0]==18'h0FFB0) FCS <= 1'b1; else if (LS[17:0]==18'h0FFA0) FCS <= 1'b1;
else if (LS[17:0]==18'h30000) FCS <= 1'b0; else if (LS[17:0]==18'h30000) FCS <= 1'b0;
// Pulse clock from init states $0FFC0 to $2FFFF
if (LS[17:0]==18'h0FF90) FCKEN <= 1'b0;
else if (LS[17:0]==18'h0FFB0) FCKEN <= 1'b1;
else if (LS[17:0]==18'h30000) FCKEN <= 1'b0;
// Send command $3B (read) (MSB first) // Send command $3B (read) (MSB first)
/*if (LS[17:0]==18'h0FFB0 || LS[17:0]==18'h0FFB1) MOSIout <= 0; if (LS[17:0]==18'h0FFB0 || LS[17:0]==18'h0FFB1) MOSIout <= 0;
else if (LS[17:0]==18'h0FFB2 || LS[17:0]==18'h0FFB3) MOSIout <= 0; else if (LS[17:0]==18'h0FFB2 || LS[17:0]==18'h0FFB3) MOSIout <= 0;
else*/ if (LS[17:0]==18'h0FFB4 || LS[17:0]==18'h0FFB5) MOSIout <= 1; else if (LS[17:0]==18'h0FFB4 || LS[17:0]==18'h0FFB5) MOSIout <= 1;
else if (LS[17:0]==18'h0FFB6 || LS[17:0]==18'h0FFB7) MOSIout <= 1; else if (LS[17:0]==18'h0FFB6 || LS[17:0]==18'h0FFB7) MOSIout <= 1;
else if (LS[17:0]==18'h0FFB8 || LS[17:0]==18'h0FFB9) MOSIout <= 1; else if (LS[17:0]==18'h0FFB8 || LS[17:0]==18'h0FFB9) MOSIout <= 1;
/*else if (LS[17:0]==18'h0FFBA || LS[17:0]==18'h0FFBB) MOSIout <= 0;*/ else if (LS[17:0]==18'h0FFBA || LS[17:0]==18'h0FFBB) MOSIout <= 0;
else if (LS[17:0]==18'h0FFBC || LS[17:0]==18'h0FFBD) MOSIout <= 1; else if (LS[17:0]==18'h0FFBC || LS[17:0]==18'h0FFBD) MOSIout <= 1;
else if (LS[17:0]==18'h0FFBE || LS[17:0]==18'h0FFBF) MOSIout <= 1; else if (LS[17:0]==18'h0FFBE || LS[17:0]==18'h0FFBF) MOSIout <= 1;
// Send 24-bit address (MSB first) // Send 24-bit address (MSB first)
/*else if (LS[17:0]==18'h0FFC0 || LS[17:0]==18'h0FFC1) MOSIout <= 0; else if (LS[17:0]==18'h0FFC0 || LS[17:0]==18'h0FFC1) MOSIout <= 0;
else if (LS[17:0]==18'h0FFC2 || LS[17:0]==18'h0FFC3) MOSIout <= 0;*/ else if (LS[17:0]==18'h0FFC2 || LS[17:0]==18'h0FFC3) MOSIout <= 0;
else if (LS[17:0]==18'h0FFC4 || LS[17:0]==18'h0FFC5) MOSIout <= SetFW[1]; else if (LS[17:0]==18'h0FFC4 || LS[17:0]==18'h0FFC5) MOSIout <= 0;
else if (LS[17:0]==18'h0FFC6 || LS[17:0]==18'h0FFC7) MOSIout <= SetFW[0]; else if (LS[17:0]==18'h0FFC6 || LS[17:0]==18'h0FFC7) MOSIout <= SetFW;
/*else if (LS[17:0]==18'h0FFC8 || LS[17:0]==18'h0FFC9) MOSIout <= 0; else if (LS[17:0]==18'h0FFC8 || LS[17:0]==18'h0FFC9) MOSIout <= 0;
else if (LS[17:0]==18'h0FFCA || LS[17:0]==18'h0FFCB) MOSIout <= 0; else if (LS[17:0]==18'h0FFCA || LS[17:0]==18'h0FFCB) MOSIout <= 0;
else if (LS[17:0]==18'h0FFCC || LS[17:0]==18'h0FFCD) MOSIout <= 0; else if (LS[17:0]==18'h0FFCC || LS[17:0]==18'h0FFCD) MOSIout <= 0;
else if (LS[17:0]==18'h0FFCE || LS[17:0]==18'h0FFCF) MOSIout <= 0; else if (LS[17:0]==18'h0FFCE || LS[17:0]==18'h0FFCF) MOSIout <= 0;
@ -232,25 +212,22 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
else if (LS[17:0]==18'h0FFE8 || LS[17:0]==18'h0FFE9) MOSIout <= 0; else if (LS[17:0]==18'h0FFE8 || LS[17:0]==18'h0FFE9) MOSIout <= 0;
else if (LS[17:0]==18'h0FFEA || LS[17:0]==18'h0FFEB) MOSIout <= 0; else if (LS[17:0]==18'h0FFEA || LS[17:0]==18'h0FFEB) MOSIout <= 0;
else if (LS[17:0]==18'h0FFEC || LS[17:0]==18'h0FFED) MOSIout <= 0; else if (LS[17:0]==18'h0FFEC || LS[17:0]==18'h0FFED) MOSIout <= 0;
else if (LS[17:0]==18'h0FFEE || LS[17:0]==18'h0FFEF) MOSIout <= 0;*/ else if (LS[17:0]==18'h0FFEE || LS[17:0]==18'h0FFEF) MOSIout <= 0;
else MOSIout <= 0; else MOSIout <= 0;
if (LS[17:0]==18'h0FFA0) MOSIOE <= 1'b0; if (LS[17:0]==18'h0FF90) MOSIOE <= 1'b1;
else if (LS[17:0]==18'h0FFB0) MOSIOE <= 1'b1;
else if (LS[17:0]==18'h0FFF0) MOSIOE <= 1'b0; else if (LS[17:0]==18'h0FFF0) MOSIOE <= 1'b0;
end else if (CmdActv) begin end else if (nRESr) begin
//TODO: control these with Apple II //TODO: control these with Apple II
FCS <= 0; FCS <= 0;
FCKEN <= 0; FCKEN <= 0;
MOSIout <= 0; MOSIout <= 0;
MOSIOE <= 0; MOSIOE <= 0;
//TODO? sample nMenu when MOSI not outputting?
end end
end end
/* UFM control */ /* UFM control */
reg ARCLK = 0; // UFM address register clock reg ARCLK = 0; // UFM address register clock
// UFM address register data input tied to 0
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
reg DRCLK = 0; // UFM data register clock reg DRCLK = 0; // UFM data register clock
reg DRDIn = 0; // UFM data register input reg DRDIn = 0; // UFM data register input
@ -280,16 +257,14 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
reg UFMBr = 0; // UFMBusy registered to sync with C25M reg UFMBr = 0; // UFMBusy registered to sync with C25M
reg RTPBr0 = 0; // RTPBusy registered to sync with C25M reg RTPBr0 = 0; // RTPBusy registered to sync with C25M
reg RTPBr = 0; // RTPBusy registered to sync with C25M reg RTPBr = 0; // RTPBusy registered to sync with C25M
always @(posedge C25M) begin always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end
UFMBr <= UFMBr0; UFMBr0 <= UFMB; always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end
RTPBr <= RTPBr0; RTPBr0 <= RTPB;
end
reg SetLoaded = 0; reg SetLoaded = 0;
reg [1:0] SetFW; reg [1:0] SetFW;
reg SetLim8M; reg SetLim8M;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~SetLoaded) begin if (~SetLoaded) begin
if (LS[15:0]<=16'h0FBF) begin if (LS[15:0]<=16'h0FB0) begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 1; ARShift <= 1;
DRCLK <= 0; DRCLK <= 0;
@ -301,106 +276,61 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
DRShift <= 0; DRShift <= 0;
SetFW[1:0] <= 2'b11; SetFW[1:0] <= 2'b11;
SetLim8M <= 1'b1; SetLim8M <= 1'b1;
end else if (LS[15:0]<=16'h2FFF) begin end else if (LS[15:0]<=16'h1FFF) begin
if (LS[4:0]==5'h00 || LS[4:0]==5'h01) begin case (LS[3:1])
3'h0: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 1; DRCLK <= 1;
DRShift <= 0; DRShift <= 0;
end else if (LS[4:0]==5'h02 || LS[4:0]==5'h03) begin end 3'h1: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 1; DRShift <= 1;
end else if (LS[4:0]==5'h04 || LS[4:0]==5'h05) begin end 3'h2: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 1; DRCLK <= 1;
DRShift <= 1; DRShift <= 1;
if (LS[4:0]==5'h04 && DRDOut) SetLoaded <= 1; if (LS[3:0]==4'h2 && DRDOut) SetLoaded <= 1;
end else if (LS[4:0]==5'h06 || LS[4:0]==5'h07) begin end 3'h3: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 1; DRShift <= 1;
end else if (LS[4:0]==5'h08 || LS[4:0]==5'h09) begin end 3'h4: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 1; DRCLK <= 1;
DRShift <= 1; DRShift <= 1;
if (LS[4:0]==5'h08) SetFW[1] <= DRDOut; if (LS[3:0]==4'h4) SetFW <= DRDOut;
end else if (LS[4:0]==5'h0A || LS[4:0]==5'h0B) begin end 3'h5: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 1; DRShift <= 1;
end else if (LS[4:0]==5'h0C || LS[4:0]==5'h0D) begin end 3'h6: begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 1;
DRShift <= 1;
if (LS[4:0]==5'h0C) SetFW[0] <= DRDOut;
end else if (LS[4:0]==5'h0E || LS[4:0]==5'h0F) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
end else if (LS[4:0]==5'h10 || LS[4:0]==5'h11) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
if (LS[4:0]==5'h10) SetLim8M <= DRDOut;
end else if (LS[4:0]==5'h12 || LS[4:0]==5'h13) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
end else if (LS[4:0]==5'h14 || LS[4:0]==5'h15) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
end else if (LS[4:0]==5'h16 || LS[4:0]==5'h17) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
end else if (LS[4:0]==5'h18 || LS[4:0]==5'h19) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
end else if (LS[4:0]==5'h1A || LS[4:0]==5'h1B) begin
ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 1;
end else if (LS[4:0]==5'h1C || LS[4:0]==5'h1D) begin
ARCLK <= 1; ARCLK <= 1;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 1; DRShift <= 1;
end else if (LS[4:0]==5'h1E || LS[4:0]==5'h1F) begin if (LS[3:0]==4'h6) SetLim8M <= DRDOut;
end 3'h7: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 1; DRShift <= 0;
end end
endcase
end else SetLoaded <= 1; end else SetLoaded <= 1;
DRDIn <= 0; DRDIn <= 0;
end else if (CmdActv) begin end else if (PS==7 /* && ... FIXME */) begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRShift <= 1; DRShift <= 1;
DRCLK <= 0;
DRDIn <= 0;
end else begin
ARCLK <= 0;
ARShift <= 0;
DRShift <= 1;
DRCLK <= 0; DRCLK <= 0;
DRDIn <= 0; DRDIn <= 0;
end end
@ -412,25 +342,18 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
reg SDOE = 0; reg SDOE = 0;
always @(posedge C25M) begin always @(posedge C25M) begin
// Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD // Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD
if (InitActv) if (LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; if (InitActv && LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0]; else if (PS==8) WRD[7:0] <= RD[7:0];
// Output data on SDRAM data bus only during init and when writing // Output data on SDRAM data bus only during init and when writing
SDOE <= InitActv || (RAMSEL && nWEcur && S==6); SDOE <= InitActv || (RAMSpecWR && PS==8);
end end
/* State counters */ reg [2:0] PS = 0;
reg [3:0] S = 0; wire PSStart = ~InitActv && nRESr && PS==0 && PHI0r1 && ~PHI0r2;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~InitActv && SDRAMActv && S==0 && PHI0r1 && ~PHI0r2 && nRESr && nBODf) S <= 1; if (PSStart) PS <= 1;
else if (S==0) S <= 0; else if (PS==0) PS <= 0;
else S <= S+1; else PS <= PS+1;
end
/* Refresh state */
reg RefDone = 0;
always @(posedge C25M) begin
if (LS[6:0]==7'h00) RefDone <= 0; // Reset RefDone every 128 C25M cycles (5.12 us)
else if (S==0 && ~RefDone && ~(PHI0r1 && ~PHI0r2)) RefDone <= 1;
end end
reg [1:0] IS = 0; reg [1:0] IS = 0;
@ -442,32 +365,67 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
end else IS <= 0; end else IS <= 0;
end end
/* Refresh state */
reg RefReqd = 0;
reg RefReady = 0;
always @(posedge C25M) begin
if (LS[6:0]==7'h00) RefReqd <= SDRAMActv; // Reset RefDone every 128 C25M cycles (5.12 us)
else if (PS==0 && ~RefReqd) RefReqd <= 0;
end
/* SDRAM address/command */ /* SDRAM address/command */
output reg [1:0] SBA; output [1:0] SBA; assign SBA[1:0] =
output reg [12:0] SA; Amux[2:0]==2'h0 ? 2'b00 : // mode register / "all"
Amux[2:0]==2'h1 ? 2'b00 : // FIXME: init row / col
Amux[2:0]==2'h2 ? 2'b10 : // ROM row / col
/* 2'h3 */ { 1'b0, Addr[23] }; // RAM col
output [12:0] SA; assign SA[12:0] =
Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register
Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all"
Amux[2:0]==3'h2 ? 13'b0011000100000 : // FIXME: init row
Amux[2:0]==3'h3 ? 13'b0011000100000 : // FIXME: init col
Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row
Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col
Amux[2:0]==3'h6 ? { Addr[22:10] } : // RAM row
/* 3'h7 */ { 4'b0000, Addr[9:1] }; // RAM col
output DQML; assign DQML =
Amux[2:0]==3'h0 ? 1'b1 : // mode register
Amux[2:0]==3'h1 ? 1'b1 : // "all"
Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row
Amux[2:0]==3'h3 ? LS[3] : // FIXME: init col
Amux[2:0]==3'h4 ? 1'b1 : // ROM row
Amux[2:0]==3'h5 ? RAcur[0]: // ROM col
Amux[2:0]==3'h6 ? 1'b1 : // RAM row
/* 3'h7 */ Addr[0]; // RAM col
output DQMH; assign DQMH =
Amux[2:0]==3'h0 ? 1'b1 : // mode register
Amux[2:0]==3'h1 ? 1'b1 : // "all"
Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row
Amux[2:0]==3'h3 ? ~LS[3] : // FIXME: init col
Amux[2:0]==3'h4 ? 1'b1 : // ROM row
Amux[2:0]==3'h5 ? ~RAcur[0]: // ROM col
Amux[2:0]==3'h6 ? 1'b1 : // RAM row
/* 3'h7 */ ~Addr[0]; // RAM col
reg [2:0] Amux = 0;
output reg RCKE = 1; output reg RCKE = 1;
output reg nRCS = 1; output reg nRCS = 1;
output reg nRAS = 1; output reg nRAS = 1;
output reg nCAS = 1; output reg nCAS = 1;
output reg nSWE = 1; output reg nSWE = 1;
output reg DQMH = 1;
output reg DQML = 1;
always @(posedge C25M) begin always @(posedge C25M) begin
if (S==0 && InitActv) begin case (PS[2:0])
if (IS[1:0]==2'h0) begin 0: begin
if (InitActv) begin
case (IS[1:0])
0: begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; Amux <= 3'b000;
DQML <= 1'b1; end 1: begin
SBA[1:0] <= 2'b00;
SA[12:11] <= 2'b00;
SA[10] <= 1'b1;
SA[9:0] <= 10'b1000100000;
end else if (IS[1:0]==2'h1) begin
if (LS[3:0]==4'h3) begin if (LS[3:0]==4'h3) begin
// PC all // PC all
RCKE <= 1'b1; RCKE <= 1'b1;
@ -475,38 +433,15 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b0; nSWE <= 1'b0;
DQMH <= 1'b1; Amux <= 3'b001;
DQML <= 1'b1;
SA[10] <= 1'b1; // "all"
end else if (LS[3:0]==4'hB) begin end else if (LS[3:0]==4'hB) begin
// Load mode register // Load mode
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b0; nRCS <= 1'b0;
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b0; nCAS <= 1'b0;
nSWE <= 1'b0; nSWE <= 1'b0;
DQMH <= 1'b1; Amux <= 3'b000;
DQML <= 1'b1;
SA[10] <= 1'b0; // reserved in mode register
end
SBA[1:0] <= 2'b00; // reserved in mode register
SA[12:11] <= 2'b00; // reserved in mode register
SA[9] <= 1'b1; // single write mode
SA[8] <= 1'b0; // reserved in mode register
SA[7] <= 1'b0; // don't enter test mode
SA[6:4] <= 2'b010; // CAS latency 2
SA[3] <= 1'b0; // sequential addressing mode
SA[2:0] <= 3'b000; // burst length 1
end else if (IS[1:0]==2'h2) begin
if (LS[2:0]==3'h3) begin
// AREF
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin end else begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
@ -514,14 +449,9 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; Amux <= 3'b000;
DQML <= 1'b1;
end end
SBA[1:0] <= 2'b10; end 2: begin
SA[12:11] <= 2'b00;
SA[10] <= 1'b1;
SA[9:0] <= 10'b1000100000;
end else if (IS[1:0]==2'h3) begin
if (LS[2:0]==3'h3) begin if (LS[2:0]==3'h3) begin
// AREF // AREF
RCKE <= 1'b1; RCKE <= 1'b1;
@ -529,12 +459,25 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b0; nCAS <= 1'b0;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; Amux <= 3'b000;
DQML <= 1'b1; end else begin
SBA[1:0] <= 2'b10; // NOP CKE
SA[12:11] <= 2'b00; RCKE <= 1'b1;
SA[10] <= 1'b1; nRCS <= 1'b1;
SA[9:0] <= 10'b1000100000; nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b000;
end
end 3: begin
if (LS[2:0]==3'h3) begin
// AREF
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
Amux <= 3'b010;
end else if (LS[2:0]==3'h5) begin end else if (LS[2:0]==3'h5) begin
// ACT // ACT
RCKE <= 1'b1; RCKE <= 1'b1;
@ -542,25 +485,15 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
SBA[1:0] <= 1'b10; Amux <= 3'b010;
SA[12:10] <= 3'b001;
SA[9:4] <= 10'b100010;
SA[3:0] <= { ~LS[17], LS[16:14] };
DQMH <= 1'b1;
DQML <= 1'b1;
end else if (LS[2:0]==3'h7) begin end else if (LS[2:0]==3'h7) begin
// WR auto-PC // WR AP
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b0; nRCS <= 1'b0;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b0; nCAS <= 1'b0;
nSWE <= 1'b0; nSWE <= 1'b0;
SBA[1:0] <= 1'b10; Amux <= 3'b011;
SA[12:11] <= 2'b00; // don't care
SA[10] <= 1'b1; // auto-precharge
SA[9:0] <= LS[13:4];
DQML <= LS[3];
DQMH <= ~LS[3];
end else begin end else begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
@ -568,199 +501,159 @@ module GR8RAM(C25M, PHI0, nBOD, nRES,
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; Amux <= 3'b010;
DQML <= 1'b1;
SBA[1:0] <= 2'b10;
SA[12:11] <= 2'b00;
SA[10] <= 1'b1;
SA[9:0] <= 10'b1000100000;
end end
end end
end else if (S==0 && ~RefDone) begin endcase
end else if (PSStart) begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b001;
end else if (RefReqd) begin
if (RCKE) begin
// AREF // AREF
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b0; nRCS <= 1'b0;
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b0; nCAS <= 1'b0;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; Amux <= 3'b001;
DQML <= 1'b1; end else begin
SBA[1:0] <= 2'b10;
SA[12:11] <= 2'b00;
SA[10] <= 1'b1;
SA[9:0] <= 10'b1000100000;
end else if (S==0) begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; Amux <= 3'b001;
DQML <= 1'b1; end
SBA[1:0] <= 2'b10; end else begin
SA[12:11] <= 2'b00; // NOP CKD
SA[10] <= 1'b1; RCKE <= 1'b0;
SA[9:0] <= 10'b1000100000; nRCS <= 1'b1;
end else if (S==4'h1) begin nRAS <= 1'b1;
if (ROMSpecRD || RAMSpecRD) begin nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b001;
end
end 1: begin
if (ROMSpecRD || RAMSpecSEL) begin
// ACT // ACT
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b0; nRCS <= 1'b0;
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin end else begin
// NOP CKE // NOP CKD
RCKE <= 1'b1; RCKE <= 1'b0;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end end
if (ROMSpecRD) Amux <= 3'b100;
if (RAMSpecRD) begin else Amux <= 3'b110;
SBA[1] <= 1'b0; end 2: begin
SBA[0] <= Addr[23] & ~SetLim8M;
SA[12:0] <= Addr[22:10];
end else begin
SBA[1] <= 1'b1;
SBA[0] <= 1'b0;
SA[12:11] <= 2'b00;
SA[10] <= 1'b1;
SA[9:4] <= 10'b100010;
SA[9:1] <= Bank[1:0];
SA[1:0] <= RAcur[11:10];
end
end else if (S==4'h2) begin
if (ROMSpecRD || RAMSpecRD) begin if (ROMSpecRD || RAMSpecRD) begin
// RD auto-PC // RD
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b0; nRCS <= 1'b0;
nRAS <= 1'b1; nRAS <= 1'b0;
nCAS <= 1'b0; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
if (RAMSpecRD) begin
DQMH <= ~Addr[0];
DQML <= Addr[0];
end else begin end else begin
DQMH <= ~RAcur[0]; // NOP CKD
DQML <= RAcur[0]; RCKE <= 1'b0;
end
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end end
SA[12:11] <= 2'b00; // don't care if (ROMSpecRD) Amux <= 3'b101;
SA[10] <= 1'b1; // auto-precharge else Amux <= 3'b111;
SA[9] <= 1'b1; // don't care end 3: begin
if (RAMSpecRD) begin if (ROMSpecRD || RAMSpecRD) begin
SBA[1] <= 1'b0;
SBA[0] <= Addr[23];
SA[8:0] <= Addr[9:1];
end else begin
SBA[1] <= 1'b1;
SBA[0] <= 1'b0;
SA[8:0] <= RAcur[9:1];
end
end else if (S==4'h3) begin
// NOP CKE
RCKE <= 1'B1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
SBA[1:0] <= 2'b10;
SA[12:11] <= 2'b00;
SA[10] <= 1'b1;
SA[9:0] <= 10'b1000100000;
end else if (S==4'h4) begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; end else begin
DQML <= 1'b1; // NOP CKD
SBA[1] <= 1'b0; RCKE <= 1'b0;
SBA[0] <= Addr[23]; nRCS <= 1'b1;
SA[12:0] <= Addr[22:10]; nRAS <= 1'b1;
end else if (S==4'h5) begin nCAS <= 1'b1;
nSWE <= 1'b1;
end
Amux <= 3'b001;
end 4: begin
if (RAMSpecWR && DEVSELr) begin if (RAMSpecWR && DEVSELr) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end else begin
// NOP CKE // NOP CKE
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1; end else begin
DQML <= 1'b1; // NOP CKD
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
end end
SBA[1] <= 1'b0; Amux <= 3'b001;
SBA[0] <= Addr[23]; end 5: begin
SA[12:0] <= Addr[22:10]; if (RAMSpecWR && DEVSELr) begin
end else if (S==4'h6) begin // WR AP
if (RAMWR) begin
// WR auto-PC
RCKE <= 1'b1; RCKE <= 1'b1;
nRCS <= 1'b0; nRCS <= 1'b0;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b0; nCAS <= 1'b0;
nSWE <= 1'b0; nSWE <= 1'b0;
DQMH <= ~Addr[10];
DQML <= Addr[10];
end else begin end else begin
// NOP CKE // NOP CKD
RCKE <= 1'b1; RCKE <= 1'b0;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
end end
SBA[1] <= 1'b0; Amux <= 3'b111;
SBA[0] <= Addr[23]; end 6: begin
SA[12:11] <= 2'b00; // don't care // NOP CKE if ACT'd, else CKD
SA[10] <= 1'b1; // auto-precharge RCKE <= ROMSpecRD || RAMSpecSEL;
SA[9:0] <= Addr[9:0]; nRCS <= 1'b1;
end else if (S==4'h7) begin nRAS <= 1'b1;
// NOP CKE nCAS <= 1'b1;
RCKE <= 1'b1; nSWE <= 1'b1;
Amux <= 3'b001;
end 7: begin
if (ROMSpecRD || RAMSpecSEL) begin
// PC all CKD
RCKE <= 1'b0;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b0;
end else begin
// NOP CKD
RCKE <= 1'b0;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
DQMH <= 1'b1;
DQML <= 1'b1;
SBA[1] <= 1'b0;
SBA[0] <= Addr[23];
SA[12:11] <= 2'b00; // don't care
SA[10] <= 1'b1; // auto-precharge
SA[9:0] <= Addr[9:0];
end end
Amux <= 3'b001;
end
endcase
end end
endmodule endmodule

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@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056850427 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616146132498 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:50 2021 " "Processing started: Thu Mar 18 04:40:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616146132498 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 05:28:52 2021 " "Processing started: Fri Mar 19 05:28:52 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616146132498 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616146132498 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616146132498 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616056851802 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616146133795 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616056851833 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616146133889 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:52 2021 " "Processing ended: Thu Mar 18 04:40:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616056852411 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 05:28:54 2021 " "Processing ended: Fri Mar 19 05:28:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616146134545 ""}

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cpld/db/GR8RAM.fit.qmsg
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cpld/db/GR8RAM.hier_info
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@ -1,56 +1,27 @@
|GR8RAM |GR8RAM
C25M => SA[0]~reg0.CLK C25M => Amux[0].CLK
C25M => SA[1]~reg0.CLK C25M => Amux[1].CLK
C25M => SA[2]~reg0.CLK C25M => Amux[2].CLK
C25M => SA[3]~reg0.CLK
C25M => SA[4]~reg0.CLK
C25M => SA[5]~reg0.CLK
C25M => SA[6]~reg0.CLK
C25M => SA[7]~reg0.CLK
C25M => SA[8]~reg0.CLK
C25M => SA[9]~reg0.CLK
C25M => SA[10]~reg0.CLK
C25M => SA[11]~reg0.CLK
C25M => SA[12]~reg0.CLK
C25M => SBA[0]~reg0.CLK
C25M => SBA[1]~reg0.CLK
C25M => DQML~reg0.CLK
C25M => DQMH~reg0.CLK
C25M => nSWE~reg0.CLK C25M => nSWE~reg0.CLK
C25M => nCAS~reg0.CLK C25M => nCAS~reg0.CLK
C25M => nRAS~reg0.CLK C25M => nRAS~reg0.CLK
C25M => nRCS~reg0.CLK C25M => nRCS~reg0.CLK
C25M => RCKE~reg0.CLK C25M => RCKE~reg0.CLK
C25M => RefReqd.CLK
C25M => IS[0].CLK C25M => IS[0].CLK
C25M => IS[1].CLK C25M => IS[1].CLK
C25M => RefDone.CLK C25M => PS[0].CLK
C25M => S[0].CLK C25M => PS[1].CLK
C25M => S[1].CLK C25M => PS[2].CLK
C25M => S[2].CLK
C25M => S[3].CLK
C25M => SDOE.CLK C25M => SDOE.CLK
C25M => WRD[0].CLK
C25M => WRD[1].CLK
C25M => WRD[2].CLK
C25M => WRD[3].CLK
C25M => WRD[4].CLK
C25M => WRD[5].CLK
C25M => WRD[6].CLK C25M => WRD[6].CLK
C25M => WRD[7].CLK C25M => WRD[7].CLK
C25M => DRDIn.CLK
C25M => SetLoaded.CLK
C25M => SetLim8M.CLK
C25M => SetFW[0].CLK
C25M => SetFW[1].CLK
C25M => DRShift.CLK
C25M => DRCLK.CLK
C25M => ARShift.CLK
C25M => ARCLK.CLK
C25M => MOSIOE.CLK C25M => MOSIOE.CLK
C25M => MOSIout.CLK C25M => MOSIout.CLK
C25M => FCS.CLK
C25M => FCKEN.CLK C25M => FCKEN.CLK
C25M => FCS.CLK
C25M => FCK~reg0.CLK C25M => FCK~reg0.CLK
C25M => Bank[0].CLK
C25M => Bank[1].CLK C25M => Bank[1].CLK
C25M => Addr[0].CLK C25M => Addr[0].CLK
C25M => Addr[1].CLK C25M => Addr[1].CLK
@ -76,7 +47,8 @@ C25M => Addr[20].CLK
C25M => Addr[21].CLK C25M => Addr[21].CLK
C25M => Addr[22].CLK C25M => Addr[22].CLK
C25M => Addr[23].CLK C25M => Addr[23].CLK
C25M => RAMSEL.CLK C25M => REGEN.CLK
C25M => IOROMEN.CLK
C25M => nWEcur.CLK C25M => nWEcur.CLK
C25M => RAcur[0].CLK C25M => RAcur[0].CLK
C25M => RAcur[1].CLK C25M => RAcur[1].CLK
@ -91,10 +63,11 @@ C25M => RAcur[9].CLK
C25M => RAcur[10].CLK C25M => RAcur[10].CLK
C25M => RAcur[11].CLK C25M => RAcur[11].CLK
C25M => RACr.CLK C25M => RACr.CLK
C25M => IOSTRBr.CLK
C25M => IOSELr.CLK
C25M => DEVSELr.CLK C25M => DEVSELr.CLK
C25M => SDRAMActv.CLK C25M => SDRAMActv.CLK
C25M => InitActv.CLK C25M => InitActv.CLK
C25M => CmdActv.CLK
C25M => InitIntr.CLK C25M => InitIntr.CLK
C25M => nRESout~reg0.CLK C25M => nRESout~reg0.CLK
C25M => LS[0].CLK C25M => LS[0].CLK
@ -119,18 +92,25 @@ C25M => nBODf.CLK
C25M => nBODf0.CLK C25M => nBODf0.CLK
C25M => nRESr.CLK C25M => nRESr.CLK
C25M => nBODr.CLK C25M => nBODr.CLK
C25M => nRESr0.CLK
C25M => nBODr0.CLK
C25M => PHI0r2.CLK C25M => PHI0r2.CLK
C25M => PHI0r1.CLK C25M => PHI0r1.CLK
C25M => PHI0r0.CLK C25M => PHI0r0.CLK
C25M => nRESr0.CLK
C25M => nBODr0.CLK
C25M => IOSTRBr0.CLK
C25M => IOSELr0.CLK
C25M => DEVSELr0.CLK C25M => DEVSELr0.CLK
PHI0 => comb.IN1
PHI0 => PHI0r0.DATAIN PHI0 => PHI0r0.DATAIN
nBOD => nBODr0.DATAIN nBOD => nBODr0.DATAIN
nRES => nRESr0.DATAIN nRES => nRESr0.DATAIN
nIOSEL => ~NO_FANOUT~ nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
nIOSEL => comb.IN1
nIOSEL => IOSELr0.DATAIN
nDEVSEL => comb.IN1
nDEVSEL => DEVSELr0.DATAIN nDEVSEL => DEVSELr0.DATAIN
nIOSTRB => ~NO_FANOUT~ nIOSTRB => comb.IN1
nIOSTRB => IOSTRBr0.DATAIN
RA[0] => RAcur[0].DATAIN RA[0] => RAcur[0].DATAIN
RA[1] => RAcur[1].DATAIN RA[1] => RAcur[1].DATAIN
RA[2] => RAcur[2].DATAIN RA[2] => RAcur[2].DATAIN
@ -147,6 +127,7 @@ RA[12] => Equal3.IN3
RA[13] => Equal3.IN2 RA[13] => Equal3.IN2
RA[14] => Equal3.IN1 RA[14] => Equal3.IN1
RA[15] => Equal3.IN0 RA[15] => Equal3.IN0
nWE => comb.IN1
nWE => nWEcur.DATAIN nWE => nWEcur.DATAIN
RAdir <= <VCC> RAdir <= <VCC>
RD[0] <> RD[0] RD[0] <> RD[0]
@ -157,33 +138,28 @@ RD[4] <> RD[4]
RD[5] <> RD[5] RD[5] <> RD[5]
RD[6] <> RD[6] RD[6] <> RD[6]
RD[7] <> RD[7] RD[7] <> RD[7]
RDdir <= <VCC> RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
DMAin => DMAout.DATAIN SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE
DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE
INTin => INTout.DATAIN SA[0] <= SA.DB_MAX_OUTPUT_PORT_TYPE
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE SA[1] <= SA.DB_MAX_OUTPUT_PORT_TYPE
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[2] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[3] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[4] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[5] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[6] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[7] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[8] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[9] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[10] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[11] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE
SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE DQML <= DQML.DB_MAX_OUTPUT_PORT_TYPE
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE DQMH <= DQMH.DB_MAX_OUTPUT_PORT_TYPE
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD[0] <> SD[0] SD[0] <> SD[0]
SD[1] <> SD[1] SD[1] <> SD[1]
@ -195,39 +171,7 @@ SD[6] <> SD[6]
SD[7] <> SD[7] SD[7] <> SD[7]
nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
MISO => WRD.DATAB MISO => WRD[7].DATAIN
MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE
|GR8RAM|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy
drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout
osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc
rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy
|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY

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32
cpld/db/GR8RAM.lpc.html
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@ -15,36 +15,4 @@
<TH>Input only Bidir</TH> <TH>Input only Bidir</TH>
<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR >
<TD >UFM_inst|UFM_altufm_none_0ep_component</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >UFM_inst</TD>
<TD >9</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >4</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE> </TABLE>

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9
cpld/db/GR8RAM.lpc.txt
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@ -1,8 +1,5 @@
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; UFM_inst|UFM_altufm_none_0ep_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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cpld/db/GR8RAM.map.qmsg
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@ -1,35 +1,31 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616150630415 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:44 2021 " "Processing started: Fri Mar 19 02:55:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:43:50 2021 " "Processing started: Fri Mar 19 06:43:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136946282 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616150631900 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946532 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150632103 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946548 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150632103 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150632353 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(233) " "Verilog HDL warning at gr8ram.v(233): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150632353 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""} { "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632353 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616150632353 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616150632384 ""}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946860 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136946860 ""} { "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""} { "Warning" "WVRFX_VERI_2106_UNCONVERTED" "SetFW gr8ram.v(230) " "Verilog HDL warning at gr8ram.v(230): object SetFW used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(263) " "Verilog HDL or VHDL warning at gr8ram.v(263): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 263 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136946892 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(34) " "Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(125) " "Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 24 gr8ram.v(126) " "Verilog HDL assignment warning at gr8ram.v(126): truncated value with size 36 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(130) " "Verilog HDL assignment warning at gr8ram.v(130): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 16 gr8ram.v(131) " "Verilog HDL assignment warning at gr8ram.v(131): truncated value with size 36 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(136) " "Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 8 gr8ram.v(137) " "Verilog HDL assignment warning at gr8ram.v(137): truncated value with size 36 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 gr8ram.v(195) " "Verilog HDL assignment warning at gr8ram.v(195): truncated value with size 2 to match size of target (1)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 195 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632400 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(249) " "Verilog HDL assignment warning at gr8ram.v(249): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 249 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632400 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(110) " "Net \"RDout\" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "SetFW 0 gr8ram.v(230) " "Net \"SetFW\" at gr8ram.v(230) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(234) " "Net \"WRD\[5..0\]\" at gr8ram.v(234) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 234 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 161 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616150633900 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616150633900 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947142 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616150634400 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616150634400 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947204 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "350 " "Implemented 350 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_LCELLS" "281 " "Implemented 281 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616150634962 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616150634962 ""}
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 181 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616136948751 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616136948751 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616150635150 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RDdir VCC " "Pin \"RDdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RDdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RCKE VCC " "Pin \"RCKE\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 448 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RCKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616136949454 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 06:43:55 2021 " "Processing ended: Fri Mar 19 06:43:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSEL " "No output dependent on input pin \"nIOSEL\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSEL"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSTRB " "No output dependent on input pin \"nIOSTRB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSTRB"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1616136950063 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "417 " "Implemented 417 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_LCELLS" "343 " "Implemented 343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616136950095 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616136950095 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136950376 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:50 2021 " "Processing ended: Fri Mar 19 02:55:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056855068 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616146137780 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:54 2021 " "Processing started: Thu Mar 18 04:40:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 05:28:56 2021 " "Processing started: Fri Mar 19 05:28:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616056855099 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616056855286 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616146138030 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616056856161 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616146138936 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616146139139 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616146139139 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616056856536 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616146139342 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616056856896 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616146139686 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616056857052 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616146139874 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616056857052 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616146139874 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616056857115 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616146139921 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616056857240 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616146140030 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.447 -415.877 C25M " " -8.447 -415.877 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.598 -485.527 C25M " " -9.598 -485.527 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.286 " "Worst-case hold slack is -16.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.286 -16.286 DRCLK " " -16.286 -16.286 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.579 -1.579 C25M " " -1.579 -1.579 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -16.296 " "Worst-case hold slack is -16.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.296 -16.296 ARCLK " " -16.296 -16.296 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 DRCLK " " -16.276 -16.276 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.031 -1.031 C25M " " -1.031 -1.031 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857333 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616146140108 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857365 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616146140124 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616056857677 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616146140483 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616146140592 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616146140592 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:58 2021 " "Processing ended: Thu Mar 18 04:40:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 05:29:00 2021 " "Processing ended: Fri Mar 19 05:29:00 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136912610 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616150602476 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:12 2021 " "Processing started: Fri Mar 19 02:55:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:43:22 2021 " "Processing started: Fri Mar 19 06:43:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136914344 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616150604133 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150604383 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150604383 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150604383 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150604383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616150604383 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150604680 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(230) " "Verilog HDL warning at gr8ram.v(230): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150604695 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""} { "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150604695 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616150604695 ""}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(121) " "Verilog HDL error at gr8ram.v(121): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 121 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604695 ""}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914954 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136914954 ""} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(125) " "Verilog HDL error at gr8ram.v(125): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 125 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604695 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(130) " "Verilog HDL error at gr8ram.v(130): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604695 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(136) " "Verilog HDL error at gr8ram.v(136): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 136 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604711 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136914985 ""} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(140) " "Verilog HDL error at gr8ram.v(140): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 140 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604711 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(195) " "Verilog HDL error at gr8ram.v(195): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 195 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604711 ""}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616150604914 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} { "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 6 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 6 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "297 " "Peak virtual memory: 297 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616150605101 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 06:43:25 2021 " "Processing ended: Fri Mar 19 06:43:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} { "Error" "EFLOW_ERROR_COUNT" "Full Compilation 8 s 1 " "Quartus II Full Compilation was unsuccessful. 8 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150605976 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"}
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "FCK gr8ram.v(190) " "Can't resolve multiple constant drivers for net \"FCK\" at gr8ram.v(190)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 190 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""}
{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "gr8ram.v(187) " "Constant driver at gr8ram.v(187)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 187 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Quartus II" 0 -1 1616136915016 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136915188 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 3 errors, 17 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:15 2021 " "Processing ended: Fri Mar 19 02:55:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 17 s " "Quartus II Full Compilation was unsuccessful. 5 errors, 17 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136916625 ""}

BIN
cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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Binary file not shown.

12
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM Assembler report for GR8RAM
Thu Mar 18 04:40:52 2021 Fri Mar 19 05:28:54 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Mar 18 04:40:52 2021 ; ; Assembler Status ; Successful - Fri Mar 19 05:28:54 2021 ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
@ -90,8 +90,8 @@ applicable agreement for further details.
; Option ; Setting ; ; Option ; Setting ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x00178E81 ; ; JTAG usercode ; 0x0016E052 ;
; Checksum ; 0x001792F1 ; ; Checksum ; 0x0016E4CA ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
@ -101,13 +101,13 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Mar 18 04:40:50 2021 Info: Processing started: Fri Mar 19 05:28:52 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 293 megabytes Info: Peak virtual memory: 293 megabytes
Info: Processing ended: Thu Mar 18 04:40:52 2021 Info: Processing ended: Fri Mar 19 05:28:54 2021
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02 Info: Total CPU time (on all processors): 00:00:02

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Fri Mar 19 02:49:01 2021 Fri Mar 19 05:29:01 2021

906
cpld/output_files/GR8RAM.fit.rpt
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File diff suppressed because it is too large Load Diff

8
cpld/output_files/GR8RAM.fit.summary
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@ -1,11 +1,11 @@
Fitter Status : Failed - Fri Mar 19 02:55:57 2021 Fitter Status : Failed - Fri Mar 19 06:44:01 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Device : EPM240T100C5 Device : EPM240T100C5
Timing Models : Final Timing Models : Final
Total logic elements : 313 / 240 ( 130 % ) Total logic elements : 250 / 240 ( 104 % )
Total pins : 73 / 80 ( 91 % ) Total pins : 69 / 80 ( 86 % )
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % ) UFM blocks : 0 / 1 ( 0 % )

20
cpld/output_files/GR8RAM.flow.rpt
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@ -1,5 +1,5 @@
Flow report for GR8RAM Flow report for GR8RAM
Fri Mar 19 02:55:57 2021 Fri Mar 19 06:44:01 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,17 +40,17 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Flow Status ; Flow Failed - Fri Mar 19 02:55:57 2021 ; ; Flow Status ; Flow Failed - Fri Mar 19 06:44:01 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 313 / 240 ( 130 % ) ; ; Total logic elements ; 250 / 240 ( 104 % ) ;
; Total pins ; 73 / 80 ( 91 % ) ; ; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
@ -59,7 +59,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/19/2021 02:55:46 ; ; Start date & time ; 03/19/2021 06:43:51 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -70,7 +70,7 @@ applicable agreement for further details.
+---------------------------------------+--------------------------------+---------------+-------------+------------+ +---------------------------------------+--------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+--------------------------------+---------------+-------------+------------+ +---------------------------------------+--------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 44085571633675.161613694503328 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 44085571633675.161615063101880 ; -- ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; ; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
@ -88,9 +88,9 @@ applicable agreement for further details.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ; ; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ;
; Fitter ; 00:00:05 ; 1.0 ; 367 MB ; 00:00:05 ; ; Fitter ; 00:00:05 ; 1.0 ; 359 MB ; 00:00:04 ;
; Total ; 00:00:11 ; -- ; -- ; 00:00:11 ; ; Total ; 00:00:10 ; -- ; -- ; 00:00:09 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
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@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="18569980bfd13b712cb1"/> <hash md5_digest_80b="44fd0c6dc62a03a951eb"/>
</project> </project>
<file_info> <file_info>
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/> <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>

209
cpld/output_files/GR8RAM.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Fri Mar 19 02:55:50 2021 Fri Mar 19 06:43:55 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -13,14 +13,12 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
5. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis IP Cores Summary 8. Registers Removed During Synthesis
9. Registers Removed During Synthesis 9. General Register Statistics
10. General Register Statistics 10. Inverted Register Statistics
11. Inverted Register Statistics 11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Multiplexer Restructuring Statistics (Restructuring Performed) 12. Analysis & Synthesis Messages
13. Port Connectivity Checks: "UFM:UFM_inst" 13. Analysis & Synthesis Suppressed Messages
14. Analysis & Synthesis Messages
15. Analysis & Synthesis Suppressed Messages
@ -46,15 +44,15 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Mar 19 02:55:50 2021 ; ; Analysis & Synthesis Status ; Successful - Fri Mar 19 06:43:55 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Total logic elements ; 343 ; ; Total logic elements ; 281 ;
; Total pins ; 73 ; ; Total pins ; 69 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
@ -153,7 +151,6 @@ applicable agreement for further details.
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------------+-------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------------+-------------------------------+---------+
; UFM.v ; yes ; User Wizard-Generated File ; Z:/Repos/GR8RAM/cpld/UFM.v ; ;
; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ; ; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ;
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------------+-------------------------------+---------+
@ -163,68 +160,54 @@ applicable agreement for further details.
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Total logic elements ; 343 ; ; Total logic elements ; 281 ;
; -- Combinational with no register ; 220 ; ; -- Combinational with no register ; 182 ;
; -- Register only ; 30 ; ; -- Register only ; 31 ;
; -- Combinational with a register ; 93 ; ; -- Combinational with a register ; 68 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 198 ; ; -- 4 input functions ; 118 ;
; -- 3 input functions ; 43 ; ; -- 3 input functions ; 54 ;
; -- 2 input functions ; 66 ; ; -- 2 input functions ; 70 ;
; -- 1 input functions ; 5 ; ; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ; ; -- 0 input functions ; 0 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 306 ; ; -- normal mode ; 233 ;
; -- arithmetic mode ; 37 ; ; -- arithmetic mode ; 48 ;
; -- qfbk mode ; 0 ; ; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 28 ; ; -- synchronous clear/load mode ; 28 ;
; -- asynchronous clear/load mode ; 0 ; ; -- asynchronous clear/load mode ; 0 ;
; ; ; ; ; ;
; Total registers ; 123 ; ; Total registers ; 99 ;
; Total logic cells in carry chains ; 41 ; ; Total logic cells in carry chains ; 51 ;
; I/O pins ; 73 ; ; I/O pins ; 69 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; C25M ; ; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 123 ; ; Maximum fan-out ; 99 ;
; Total fan-out ; 1357 ; ; Total fan-out ; 1030 ;
; Average fan-out ; 3.25 ; ; Average fan-out ; 2.94 ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |GR8RAM ; 343 (343) ; 123 ; 1 ; 73 ; 0 ; 220 (220) ; 30 (30) ; 93 (93) ; 41 (41) ; 0 (0) ; |GR8RAM ; work ; ; |GR8RAM ; 281 (281) ; 99 ; 0 ; 69 ; 0 ; 182 (182) ; 31 (31) ; 68 (68) ; 51 (51) ; 0 (0) ; |GR8RAM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |GR8RAM|UFM:UFM_inst ; Z:/Repos/GR8RAM/cpld/UFM.v ;
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ; ; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+ +---------------------------------------+----------------------+
; Register name ; Reason for Removal ; ; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+ +---------------------------------------+----------------------+
; DRDIn ; Stuck at GND due to stuck port data_in ; ; Addr[21,22] ; Merged with Addr[23] ;
; nRESout~reg0 ; Merged with CmdActv ; ; Total Number of Removed Registers = 2 ; ;
; RCKE~reg0 ; Stuck at VCC due to stuck port data_in ; +---------------------------------------+----------------------+
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+ +------------------------------------------------------+
@ -232,12 +215,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Statistic ; Value ; ; Statistic ; Value ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Total registers ; 123 ; ; Total registers ; 99 ;
; Number of registers using Synchronous Clear ; 24 ; ; Number of registers using Synchronous Clear ; 25 ;
; Number of registers using Synchronous Load ; 4 ; ; Number of registers using Synchronous Load ; 3 ;
; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 69 ; ; Number of registers using Clock Enable ; 43 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@ -247,13 +230,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------+---------+ +----------------------------------------+---------+
; Inverted Register ; Fan out ; ; Inverted Register ; Fan out ;
+----------------------------------------+---------+ +----------------------------------------+---------+
; nRCS~reg0 ; 3 ; ; nRCS~reg0 ; 1 ;
; nRAS~reg0 ; 3 ; ; nRAS~reg0 ; 1 ;
; nCAS~reg0 ; 3 ; ; nCAS~reg0 ; 1 ;
; nSWE~reg0 ; 3 ; ; nSWE~reg0 ; 1 ;
; DQML~reg0 ; 1 ; ; RCKE~reg0 ; 2 ;
; DQMH~reg0 ; 1 ; ; Total number of inverted registers = 5 ; ;
; Total number of inverted registers = 6 ; ;
+----------------------------------------+---------+ +----------------------------------------+---------+
@ -262,87 +244,64 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|S[3] ; ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|Addr[2] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[0] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|Addr[18] ; ; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[4] ;
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |GR8RAM|IS[1] ; ; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |GR8RAM|IS[0] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[8] ; ; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[14] ;
; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |GR8RAM|DRShift ; ; 9:1 ; 4 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |GR8RAM|Addr[17] ;
; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[23] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ;
; 13:1 ; 2 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |GR8RAM|SA[12]~reg0 ; ; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ;
; 17:1 ; 5 bits ; 55 LEs ; 30 LEs ; 25 LEs ; Yes ; |GR8RAM|SA[7]~reg0 ; ; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ;
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQMH ;
; 20:1 ; 2 bits ; 26 LEs ; 8 LEs ; 18 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst" ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; ardin ; Input ; Info ; Stuck at GND ;
; oscena ; Input ; Info ; Stuck at VCC ;
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+ +-------------------------------+
; Analysis & Synthesis Messages ; ; Analysis & Synthesis Messages ;
+-------------------------------+ +-------------------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Mar 19 02:55:44 2021 Info: Processing started: Fri Mar 19 06:43:50 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_0ep Info (12023): Found entity 1: UFM_altufm_none_0ep
Info (12023): Found entity 2: UFM Info (12023): Found entity 2: UFM
Warning (10229): Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits
Warning (10229): Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits
Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: GR8RAM Info (12023): Found entity 1: GR8RAM
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for "UFMB"
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for "RTPB"
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(112): object "REGEN" assigned a value but never read Warning (10858): Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned
Warning (10858): Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned Warning (10858): Verilog HDL warning at gr8ram.v(230): object SetFW used but never assigned
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(280): object "UFMBr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(263): object "RefReady" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(282): object "RTPBr" assigned a value but never read Warning (10230): Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18) Warning (10230): Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at gr8ram.v(126): truncated value with size 36 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at gr8ram.v(130): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at gr8ram.v(131): truncated value with size 36 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6) Warning (10230): Verilog HDL assignment warning at gr8ram.v(137): truncated value with size 36 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6) Warning (10230): Verilog HDL assignment warning at gr8ram.v(195): truncated value with size 2 to match size of target (1)
Warning (10030): Net "RDout" at gr8ram.v(127) has no driver or initial value, using a default initial value '0' Warning (10230): Verilog HDL assignment warning at gr8ram.v(249): truncated value with size 32 to match size of target (3)
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" Warning (10030): Net "RDout" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'
Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component" Warning (10030): Net "SetFW" at gr8ram.v(230) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "WRD[5..0]" at gr8ram.v(234) has no driver or initial value, using a default initial value '0'
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate
Warning (13024): Output pins are stuck at VCC or GND Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "RAdir" is stuck at VCC Warning (13410): Pin "RAdir" is stuck at VCC
Warning (13410): Pin "RDdir" is stuck at VCC Info (21057): Implemented 350 device resources after synthesis - the final resource count might be different
Warning (13410): Pin "RCKE" is stuck at VCC Info (21058): Implemented 25 input pins
Warning (21074): Design contains 2 input pin(s) that do not drive logic Info (21059): Implemented 28 output pins
Warning (15610): No output dependent on input pin "nIOSEL"
Warning (15610): No output dependent on input pin "nIOSTRB"
Info (21057): Implemented 417 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 27 input pins
Info (21059): Implemented 30 output pins
Info (21060): Implemented 16 bidirectional pins Info (21060): Implemented 16 bidirectional pins
Info (21061): Implemented 343 logic cells Info (21061): Implemented 281 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings
Info: Peak virtual memory: 301 megabytes Info: Peak virtual memory: 301 megabytes
Info: Processing ended: Fri Mar 19 02:55:50 2021 Info: Processing ended: Fri Mar 19 06:43:55 2021
Info: Elapsed time: 00:00:06 Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:06 Info: Total CPU time (on all processors): 00:00:05
+------------------------------------------+ +------------------------------------------+

4
cpld/output_files/GR8RAM.map.smsg
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@ -1,4 +1,4 @@
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
Warning (10273): Verilog HDL warning at gr8ram.v(126): extended using "x" or "z" Warning (10273): Verilog HDL warning at gr8ram.v(109): extended using "x" or "z"
Warning (10273): Verilog HDL warning at gr8ram.v(410): extended using "x" or "z" Warning (10273): Verilog HDL warning at gr8ram.v(233): extended using "x" or "z"

8
cpld/output_files/GR8RAM.map.summary
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@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Fri Mar 19 02:55:50 2021 Analysis & Synthesis Status : Successful - Fri Mar 19 06:43:55 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Total logic elements : 343 Total logic elements : 281
Total pins : 73 Total pins : 69
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % ) UFM blocks : 0 / 1 ( 0 % )

BIN
cpld/output_files/GR8RAM.pof
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940
cpld/output_files/GR8RAM.sta.rpt
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16
cpld/output_files/GR8RAM.sta.summary
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@ -11,20 +11,20 @@ Slack : -99.000
TNS : -99.000 TNS : -99.000
Type : Setup 'C25M' Type : Setup 'C25M'
Slack : -8.447 Slack : -9.598
TNS : -415.877 TNS : -485.527
Type : Hold 'DRCLK'
Slack : -16.286
TNS : -16.286
Type : Hold 'ARCLK' Type : Hold 'ARCLK'
Slack : -16.296
TNS : -16.296
Type : Hold 'DRCLK'
Slack : -16.276 Slack : -16.276
TNS : -16.276 TNS : -16.276
Type : Hold 'C25M' Type : Hold 'C25M'
Slack : -1.579 Slack : -1.031
TNS : -1.579 TNS : -1.031
Type : Minimum Pulse Width 'ARCLK' Type : Minimum Pulse Width 'ARCLK'
Slack : -29.500 Slack : -29.500