Add SPI control
This commit is contained in:
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(kicad_sch (version 20230121) (generator eeschema)
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(uuid 03d59670-8c65-499d-9846-d220ccf72801)
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(paper "A4")
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(lib_symbols
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(kicad_sch (version 20230121) (generator eeschema)
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(uuid 73789c9c-4faf-4437-8e94-73a6bbbf318f)
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(paper "A4")
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(lib_symbols
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27371
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"active_layer": 0,
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"active_layer": 0,
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"active_layer_preset": "All Layers",
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"active_layer_preset": "All Layers",
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||||||
"auto_track_width": true,
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [],
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"hidden_nets": [],
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"high_contrast_mode": 0,
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"high_contrast_mode": 0,
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||||||
"net_color_mode": 1,
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"net_color_mode": 1,
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||||||
"opacity": {
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"opacity": {
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||||||
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"images": 0.6,
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||||||
"pads": 1.0,
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"pads": 1.0,
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"tracks": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"vias": 1.0,
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@ -38,7 +40,6 @@
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@ -59,7 +60,9 @@
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],
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],
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"visible_layers": "fffffff_ffffffff",
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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"zone_display_mode": 0
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@ -1,5 +1,6 @@
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{
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{
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"board": {
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"board": {
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"3dviewports": [],
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"design_settings": {
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"design_settings": {
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"defaults": {
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"defaults": {
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"board_outline_line_width": 0.15,
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"board_outline_line_width": 0.15,
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@ -63,20 +64,26 @@
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"rule_severities": {
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"rule_severities": {
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"annular_width": "error",
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"annular_width": "error",
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||||||
"clearance": "error",
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"clearance": "error",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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||||||
"courtyards_overlap": "error",
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"courtyards_overlap": "error",
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||||||
"diff_pair_gap_out_of_range": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_type_mismatch": "error",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"length_out_of_range": "error",
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"lib_footprint_issues": "warning",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_courtyard": "ignore",
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@ -86,9 +93,14 @@
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"padstack": "error",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_dangling": "warning",
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@ -97,7 +109,6 @@
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"unconnected_items": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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"zones_intersect": "error"
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},
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},
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"rule_severitieslegacy_courtyards_overlap": true,
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"rule_severitieslegacy_courtyards_overlap": true,
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@ -107,18 +118,63 @@
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"allow_microvias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.075,
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"min_copper_edge_clearance": 0.075,
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"min_hole_clearance": 0.25,
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"min_hole_clearance": 0.25,
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||||||
"min_hole_to_hole": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_microvia_drill": 0.09999999999999999,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.0,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.19999999999999998,
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"min_through_hole_diameter": 0.19999999999999998,
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"min_track_width": 0.15,
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"min_track_width": 0.15,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.5,
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"min_via_diameter": 0.5,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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"use_height_for_length_calcs": true
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},
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},
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"teardrop_options": [
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{
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"td_allow_use_two_tracks": true,
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"td_curve_segcount": 5,
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"td_on_pad_in_zone": false,
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"td_onpadsmd": true,
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"td_onroundshapesonly": false,
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"td_ontrackend": false,
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"td_onviapad": true
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}
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],
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"teardrop_parameters": [
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_round_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_rect_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 0,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_track_end",
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [
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"track_widths": [
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0.0,
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0.0,
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0.15,
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0.15,
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@ -165,7 +221,8 @@
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"zones_allow_external_fillets": false,
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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"zones_use_no_outline": true
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||||||
},
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},
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||||||
"layer_presets": []
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"layer_presets": [],
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||||||
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"viewports": []
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||||||
},
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},
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||||||
"boards": [],
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"boards": [],
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"cvpcb": {
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"cvpcb": {
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@ -349,18 +406,23 @@
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"rule_severities": {
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"hier_label_mismatch": "error",
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||||||
"label_dangling": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"multiple_net_names": "warning",
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||||||
"net_not_bus_member": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_connected": "warning",
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@ -370,6 +432,7 @@
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"pin_to_pin": "warning",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"similar_labels": "warning",
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"simulation_model_issue": "error",
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"unannotated": "error",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"unresolved_variable": "error",
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@ -387,7 +450,7 @@
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"net_settings": {
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"net_settings": {
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"classes": [
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"classes": [
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{
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.15,
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"clearance": 0.15,
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"diff_pair_gap": 0.25,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -401,13 +464,15 @@
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"track_width": 0.15,
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"track_width": 0.15,
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"via_diameter": 0.5,
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"via_diameter": 0.5,
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"via_drill": 0.2,
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"via_drill": 0.2,
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"wire_width": 6.0
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"wire_width": 6
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}
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}
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],
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],
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"meta": {
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"meta": {
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"version": 2
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"version": 3
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},
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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||||||
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"netclass_patterns": []
|
||||||
},
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},
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"pcbnew": {
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"pcbnew": {
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"last_paths": {
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"last_paths": {
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@ -423,6 +488,8 @@
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"schematic": {
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"schematic": {
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||||||
"annotate_start_num": 0,
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"annotate_start_num": 0,
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||||||
"drawing": {
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"drawing": {
|
||||||
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"dashed_lines_dash_length_ratio": 12.0,
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||||||
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"dashed_lines_gap_length_ratio": 3.0,
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||||||
"default_line_thickness": 6.0,
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"default_line_thickness": 6.0,
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||||||
"default_text_size": 50.0,
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"default_text_size": 50.0,
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||||||
"field_names": [],
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"field_names": [],
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||||||
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@ -454,7 +521,11 @@
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||||||
"page_layout_descr_file": "",
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"page_layout_descr_file": "",
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||||||
"plot_directory": "",
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"plot_directory": "",
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||||||
"spice_adjust_passive_values": false,
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"spice_adjust_passive_values": false,
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||||||
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"spice_current_sheet_as_root": false,
|
||||||
"spice_external_command": "spice \"%I\"",
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"spice_external_command": "spice \"%I\"",
|
||||||
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"spice_model_current_sheet_as_root": true,
|
||||||
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"spice_save_all_currents": false,
|
||||||
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"spice_save_all_voltages": false,
|
||||||
"subpart_first_id": 65,
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"subpart_first_id": 65,
|
||||||
"subpart_id_separator": 0
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"subpart_id_separator": 0
|
||||||
},
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},
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@ -466,6 +537,18 @@
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[
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[
|
||||||
"00000000-0000-0000-0000-00005d4d21a0",
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"00000000-0000-0000-0000-00005d4d21a0",
|
||||||
"Docs"
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"Docs"
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||||||
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],
|
||||||
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[
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||||||
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"b38206eb-cbcb-4774-86d5-3e407357811e",
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||||||
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"Bus"
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||||||
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],
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||||||
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[
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||||||
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"5e16a16a-d8a6-4780-b76e-bb404ed87b79",
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||||||
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"FPGA"
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||||||
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],
|
||||||
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[
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||||||
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"8ff39fed-057b-492d-8c59-5abc49c84644",
|
||||||
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"Power"
|
||||||
]
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]
|
||||||
],
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],
|
||||||
"text_variables": {}
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"text_variables": {}
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7069
GR8RAM.kicad_sch
7069
GR8RAM.kicad_sch
File diff suppressed because it is too large
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
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set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
|
||||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
|
||||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
|
|
@ -21,17 +21,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
|
|
||||||
/* Firmware select */
|
/* Firmware select */
|
||||||
input [1:0] SetFW;
|
input [1:0] SetFW;
|
||||||
reg [1:0] SetFWr;
|
wire [1:0] SetROM = 2'b00;
|
||||||
reg SetFWLoaded = 0;
|
wire SetEN16MB = 0;
|
||||||
always @(posedge C25M) begin
|
wire SetEN24bit = 1;
|
||||||
if (~SetFWLoaded) begin
|
|
||||||
SetFWLoaded <= 1;
|
|
||||||
SetFWr[1:0] <= SetFW[1:0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
wire [1:0] SetROM = ~SetFWr[1:0];
|
|
||||||
wire SetEN16MB = SetROM[1:0]==2'b11;
|
|
||||||
wire SetEN24bit = SetROM[1];
|
|
||||||
|
|
||||||
/* State counter from PHI0 rising edge */
|
/* State counter from PHI0 rising edge */
|
||||||
reg [3:0] PS = 0;
|
reg [3:0] PS = 0;
|
||||||
|
@ -77,6 +69,8 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
|
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
|
||||||
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
|
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
|
||||||
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
|
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
|
||||||
|
wire SPITX1SpecSEL = REGSpecSEL && RAr[3:0]==4'hD;
|
||||||
|
wire SPITX0SpecSEL = REGSpecSEL && RAr[3:0]==4'hC;
|
||||||
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
|
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
|
||||||
wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
|
wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
|
||||||
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
|
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
|
||||||
|
@ -153,18 +147,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
|
|
||||||
/* ROM bank register */
|
/* ROM bank register */
|
||||||
reg Bank = 0;
|
reg Bank = 0;
|
||||||
|
reg RestoreDone = 0;
|
||||||
always @(posedge C25M, negedge nRESr) begin
|
always @(posedge C25M, negedge nRESr) begin
|
||||||
if (~nRESr) Bank <= 0;
|
if (~nRESr) Bank <= 0;
|
||||||
else if (PS==8 && BankSEL && ~nWEr) begin
|
else if (PS==8 && BankSEL && ~nWEr) begin
|
||||||
Bank <= RD[0];
|
if (!RestoreDone) begin
|
||||||
|
RestoreDone <= RD[1:0]==2'b11;
|
||||||
|
end else Bank <= RD[0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
/* SPI flash control signals */
|
/* SPI flash control signals */
|
||||||
output nFCS = FCKOE ? ~FCS : 1'bZ;
|
output reg nFCS = 1;
|
||||||
reg FCS = 0;
|
output FCK = FCKout;
|
||||||
output FCK = FCKOE ? FCKout : 1'bZ;
|
|
||||||
reg FCKOE = 0;
|
|
||||||
reg FCKout = 0;
|
reg FCKout = 0;
|
||||||
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
|
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
|
||||||
reg MOSIOE = 0;
|
reg MOSIOE = 0;
|
||||||
|
@ -186,7 +181,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
end 6: begin // NOP CKE
|
end 6: begin // NOP CKE
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 7: begin // NOP CKE
|
end 7: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5 || IS==6);
|
FCKout <= ~(IS==5 || IS==6 || (!nDEVSEL && RestoreDone && (SPITX0SpecSEL || SPITX1SpecSEL)));
|
||||||
end 8: begin // WR AP
|
end 8: begin // WR AP
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 9: begin // NOP CKE
|
end 9: begin // NOP CKE
|
||||||
|
@ -205,9 +200,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
FCKout <= ~(IS==5);
|
FCKout <= ~(IS==5);
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
FCS <= IS==4 || IS==5 || IS==6;
|
|
||||||
MOSIOE <= IS==5;
|
nFCS <= !(IS==4 || IS==5 || IS==6 || Bank);
|
||||||
FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
|
MOSIOE <= IS==5 || IS==7;
|
||||||
end
|
end
|
||||||
|
|
||||||
/* SPI flash MOSI control */
|
/* SPI flash MOSI control */
|
||||||
|
@ -218,7 +213,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
case (LS[2:0])
|
case (LS[2:0])
|
||||||
3'h3: MOSIout <= 1'b0; // Command bit 7
|
3'h3: MOSIout <= 1'b0; // Command bit 7
|
||||||
3'h4: MOSIout <= 1'b0; // Address bit 23
|
3'h4: MOSIout <= 1'b0; // Address bit 23
|
||||||
3'h5: MOSIout <= 1'b0; // Address bit 15
|
3'h5: MOSIout <= 1'b1; // Address bit 15
|
||||||
3'h6: MOSIout <= 1'b0; // Address bit 7
|
3'h6: MOSIout <= 1'b0; // Address bit 7
|
||||||
default MOSIout <= 1'b0;
|
default MOSIout <= 1'b0;
|
||||||
endcase
|
endcase
|
||||||
|
@ -239,13 +234,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
default MOSIout <= 1'b0;
|
default MOSIout <= 1'b0;
|
||||||
endcase
|
endcase
|
||||||
end 7: begin
|
end 7: begin
|
||||||
case (LS[2:0])
|
if (nRES) case (LS[2:0])
|
||||||
3'h3: MOSIout <= 1'b1; // Command bit 4
|
3'h3: MOSIout <= 1'b1; // Command bit 4
|
||||||
3'h4: MOSIout <= 1'b0; // Address bit 20
|
3'h4: MOSIout <= 1'b0; // Address bit 20
|
||||||
3'h5: MOSIout <= 1'b0; // Address bit 12
|
3'h5: MOSIout <= 1'b0; // Address bit 12
|
||||||
3'h6: MOSIout <= 1'b0; // Address bit 4
|
3'h6: MOSIout <= 1'b0; // Address bit 4
|
||||||
default MOSIout <= 1'b0;
|
default MOSIout <= 1'b0;
|
||||||
endcase
|
endcase else MOSIout <= RAr[0];
|
||||||
end 9: begin
|
end 9: begin
|
||||||
case (LS[2:0])
|
case (LS[2:0])
|
||||||
3'h3: MOSIout <= 1'b1; // Command bit 3
|
3'h3: MOSIout <= 1'b1; // Command bit 3
|
||||||
|
@ -330,6 +325,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
|
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
|
||||||
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
|
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
|
||||||
else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
|
else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
|
||||||
|
else if (BankSpecSEL) RDD[7:0] <= { MISO, 7'h7F };
|
||||||
else RDD[7:0] <= SD[7:0];
|
else RDD[7:0] <= SD[7:0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
@ -454,19 +450,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
DQML <= 1'b1;
|
DQML <= 1'b1;
|
||||||
DQMH <= 1'b1;
|
DQMH <= 1'b1;
|
||||||
if (IS==6) begin
|
if (IS==6) begin
|
||||||
SBA[1:0] <= { 2'b10 };
|
SBA[1:0] <= 2'b10;
|
||||||
SA[12:0] <= { 10'b0011000100, LS[12:10] };
|
SA[12:0] <= { 10'b0011000100, LS[12:10] };
|
||||||
end else if (RAMSpecSEL) begin
|
end else if (RAMSpecSEL) begin
|
||||||
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
SBA[1:0] <= { 1'b0, 1'b0 };
|
||||||
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
|
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
|
||||||
SA[9:0] <= Addr[19:10];
|
SA[9:0] <= Addr[19:10];
|
||||||
end else begin
|
end else begin
|
||||||
SBA[1:0] <= 2'b10;
|
SBA[1:0] <= 2'b10;
|
||||||
SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
|
SA[12:0] <= { 10'b0011000100, RestoreDone ? (nIOSEL ? 1'b0 : Bank) : 1'b1, RAr[11:10] };
|
||||||
end
|
end
|
||||||
end 2: begin // RD
|
end 2: begin // RD
|
||||||
if (RAMSpecSEL) begin
|
if (RAMSpecSEL) begin
|
||||||
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
SBA[1:0] <= 2'b00;
|
||||||
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
||||||
DQML <= Addr[0];
|
DQML <= Addr[0];
|
||||||
DQMH <= ~Addr[0];
|
DQMH <= ~Addr[0];
|
||||||
|
@ -508,7 +504,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
DQML <= LS[0];
|
DQML <= LS[0];
|
||||||
DQMH <= ~LS[0];
|
DQMH <= ~LS[0];
|
||||||
end else begin
|
end else begin
|
||||||
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
SBA[1:0] <= 2'b00;
|
||||||
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
||||||
DQML <= Addr[0];
|
DQML <= Addr[0];
|
||||||
DQMH <= ~Addr[0];
|
DQMH <= ~Addr[0];
|
||||||
|
|
|
@ -0,0 +1,808 @@
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus Prime
|
||||||
|
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
# Date created = 19:21:05 March 25, 2023
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Note:
|
||||||
|
#
|
||||||
|
# 1) Do not modify this file. This file was generated
|
||||||
|
# automatically by the Quartus Prime software and is used
|
||||||
|
# to preserve global assignments across Quartus Prime versions.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
|
||||||
|
set_global_assignment -name IP_COMPONENT_INTERNAL Off
|
||||||
|
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||||
|
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||||
|
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
|
||||||
|
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||||
|
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||||
|
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||||
|
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||||
|
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||||
|
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||||
|
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||||
|
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||||
|
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||||
|
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||||
|
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||||
|
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||||
|
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||||
|
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||||
|
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
|
||||||
|
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
|
||||||
|
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
|
||||||
|
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
|
||||||
|
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||||
|
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||||
|
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||||
|
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||||
|
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
||||||
|
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
|
||||||
|
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
|
||||||
|
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
|
||||||
|
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||||
|
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||||
|
set_global_assignment -name OPTIMIZATION_MODE Balanced
|
||||||
|
set_global_assignment -name ALLOW_REGISTER_MERGING On
|
||||||
|
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
|
||||||
|
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||||
|
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||||
|
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||||
|
set_global_assignment -name SAVE_DISK_SPACE On
|
||||||
|
set_global_assignment -name OCP_HW_EVAL -value OFF
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||||
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||||
|
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||||
|
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||||
|
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||||
|
set_global_assignment -name FAMILY -value "Cyclone V"
|
||||||
|
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||||
|
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||||
|
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||||
|
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||||
|
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||||
|
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||||
|
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||||
|
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||||
|
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||||
|
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||||
|
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||||
|
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||||
|
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||||
|
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||||
|
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||||
|
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||||
|
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||||
|
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||||
|
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||||
|
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||||
|
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||||
|
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||||
|
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||||
|
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||||
|
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||||
|
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||||
|
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||||
|
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||||
|
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||||
|
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||||
|
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||||
|
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||||
|
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||||
|
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||||
|
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||||
|
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||||
|
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||||
|
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||||
|
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||||
|
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||||
|
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||||
|
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||||
|
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||||
|
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||||
|
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||||
|
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||||
|
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||||
|
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||||
|
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||||
|
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||||
|
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||||
|
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||||
|
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||||
|
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||||
|
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||||
|
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||||
|
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||||
|
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||||
|
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||||
|
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||||
|
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||||
|
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||||
|
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||||
|
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||||
|
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
||||||
|
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||||
|
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||||
|
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||||
|
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||||
|
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||||
|
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||||
|
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||||
|
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||||
|
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||||
|
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||||
|
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||||
|
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||||
|
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
|
||||||
|
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||||
|
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
|
||||||
|
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
|
||||||
|
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||||
|
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||||
|
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||||
|
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||||
|
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||||
|
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||||
|
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||||
|
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||||
|
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||||
|
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||||
|
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||||
|
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||||
|
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||||
|
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||||
|
set_global_assignment -name PRPOF_ID Off
|
||||||
|
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
|
||||||
|
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
|
||||||
|
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
|
||||||
|
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
|
||||||
|
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||||
|
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||||
|
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||||
|
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||||
|
set_global_assignment -name ADCE_ENABLED Auto
|
||||||
|
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||||
|
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||||
|
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||||
|
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||||
|
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS Off
|
||||||
|
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||||
|
set_global_assignment -name DEVICE AUTO
|
||||||
|
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||||
|
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||||
|
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||||
|
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||||
|
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||||
|
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||||
|
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||||
|
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
|
||||||
|
set_global_assignment -name CVP_MODE Off
|
||||||
|
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
|
||||||
|
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
|
||||||
|
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
|
||||||
|
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
|
||||||
|
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
|
||||||
|
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
|
||||||
|
set_global_assignment -name USE_CONF_DONE AUTO
|
||||||
|
set_global_assignment -name USE_PWRMGT_SCL AUTO
|
||||||
|
set_global_assignment -name USE_PWRMGT_SDA AUTO
|
||||||
|
set_global_assignment -name USE_PWRMGT_ALERT AUTO
|
||||||
|
set_global_assignment -name USE_INIT_DONE AUTO
|
||||||
|
set_global_assignment -name USE_CVP_CONFDONE AUTO
|
||||||
|
set_global_assignment -name USE_SEU_ERROR AUTO
|
||||||
|
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||||
|
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||||
|
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||||
|
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||||
|
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||||
|
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||||
|
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
|
||||||
|
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
|
||||||
|
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
|
||||||
|
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
|
||||||
|
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||||
|
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||||
|
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||||
|
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||||
|
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||||
|
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||||
|
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||||
|
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||||
|
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||||
|
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||||
|
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||||
|
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||||
|
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||||
|
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||||
|
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||||
|
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||||
|
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||||
|
set_global_assignment -name ENABLE_NCE_PIN Off
|
||||||
|
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||||
|
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||||
|
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||||
|
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||||
|
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||||
|
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||||
|
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||||
|
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||||
|
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||||
|
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||||
|
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||||
|
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
|
||||||
|
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
|
||||||
|
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
|
||||||
|
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
|
||||||
|
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||||
|
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||||
|
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||||
|
set_global_assignment -name OPTIMIZE_SSN Off
|
||||||
|
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||||
|
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||||
|
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||||
|
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||||
|
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||||
|
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||||
|
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||||
|
set_global_assignment -name SEED 1
|
||||||
|
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
|
||||||
|
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
|
||||||
|
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||||
|
set_global_assignment -name PCI_IO Off
|
||||||
|
set_global_assignment -name TURBO_BIT On
|
||||||
|
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||||
|
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||||
|
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||||
|
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||||
|
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
|
||||||
|
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
|
||||||
|
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||||
|
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
|
||||||
|
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||||
|
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||||
|
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||||
|
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||||
|
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||||
|
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||||
|
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||||
|
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||||
|
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||||
|
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
|
||||||
|
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||||
|
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||||
|
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||||
|
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||||
|
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||||
|
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||||
|
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||||
|
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||||
|
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||||
|
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||||
|
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||||
|
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||||
|
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
|
||||||
|
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||||
|
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||||
|
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||||
|
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||||
|
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||||
|
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||||
|
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||||
|
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||||
|
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||||
|
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||||
|
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||||
|
set_global_assignment -name ENABLE_PR_PINS Off
|
||||||
|
set_global_assignment -name RESERVE_PR_PINS Off
|
||||||
|
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
|
||||||
|
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||||
|
set_global_assignment -name CLAMPING_DIODE Off
|
||||||
|
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||||
|
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||||
|
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||||
|
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||||
|
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
|
||||||
|
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
|
||||||
|
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
|
||||||
|
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
|
||||||
|
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
|
||||||
|
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
|
||||||
|
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
|
||||||
|
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
|
||||||
|
set_global_assignment -name SEU_FIT_REPORT Off
|
||||||
|
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
|
||||||
|
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
|
||||||
|
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
|
||||||
|
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
|
||||||
|
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
|
||||||
|
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
|
||||||
|
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||||
|
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||||
|
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||||
|
set_global_assignment -name COMPRESSION_MODE Off
|
||||||
|
set_global_assignment -name CLOCK_SOURCE Internal
|
||||||
|
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||||
|
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||||
|
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||||
|
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||||
|
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||||
|
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||||
|
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||||
|
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||||
|
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||||
|
set_global_assignment -name SECURITY_BIT Off
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
|
||||||
|
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
|
||||||
|
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
|
||||||
|
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
|
||||||
|
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
|
||||||
|
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||||
|
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||||
|
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||||
|
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||||
|
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||||
|
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||||
|
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||||
|
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||||
|
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||||
|
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||||
|
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||||
|
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||||
|
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||||
|
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
|
||||||
|
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
|
||||||
|
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||||
|
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||||
|
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||||
|
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
|
||||||
|
set_global_assignment -name POR_SCHEME "Instant ON"
|
||||||
|
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
|
||||||
|
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
|
||||||
|
set_global_assignment -name POF_VERIFY_PROTECT Off
|
||||||
|
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
|
||||||
|
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
|
||||||
|
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||||
|
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
|
||||||
|
set_global_assignment -name GENERATE_PMSF_FILES On
|
||||||
|
set_global_assignment -name START_TIME 0ns
|
||||||
|
set_global_assignment -name SIMULATION_MODE TIMING
|
||||||
|
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||||
|
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||||
|
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||||
|
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||||
|
set_global_assignment -name CHECK_OUTPUTS Off
|
||||||
|
set_global_assignment -name SIMULATION_COVERAGE On
|
||||||
|
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||||
|
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||||
|
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||||
|
set_global_assignment -name GLITCH_DETECTION Off
|
||||||
|
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||||
|
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||||
|
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||||
|
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||||
|
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||||
|
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||||
|
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||||
|
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||||
|
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||||
|
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||||
|
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||||
|
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||||
|
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||||
|
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||||
|
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||||
|
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||||
|
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||||
|
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||||
|
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||||
|
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||||
|
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||||
|
set_global_assignment -name MERGE_HEX_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||||
|
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||||
|
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||||
|
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||||
|
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||||
|
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
|
||||||
|
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||||
|
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||||
|
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||||
|
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||||
|
set_global_assignment -name POWER_USE_PVA On
|
||||||
|
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||||
|
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||||
|
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||||
|
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||||
|
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||||
|
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||||
|
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||||
|
set_global_assignment -name POWER_TJ_VALUE 25
|
||||||
|
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||||
|
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||||
|
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||||
|
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||||
|
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||||
|
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
|
||||||
|
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||||
|
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||||
|
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||||
|
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||||
|
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||||
|
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||||
|
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||||
|
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||||
|
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||||
|
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||||
|
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||||
|
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||||
|
set_global_assignment -name EQC_BBOX_MERGE On
|
||||||
|
set_global_assignment -name EQC_LVDS_MERGE On
|
||||||
|
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||||
|
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||||
|
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||||
|
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||||
|
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||||
|
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||||
|
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||||
|
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||||
|
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||||
|
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||||
|
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||||
|
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||||
|
set_global_assignment -name EQC_RENAMING_RULES On
|
||||||
|
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||||
|
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||||
|
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||||
|
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||||
|
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||||
|
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||||
|
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||||
|
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||||
|
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||||
|
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||||
|
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||||
|
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||||
|
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||||
|
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||||
|
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||||
|
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||||
|
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||||
|
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||||
|
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
|
||||||
|
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||||
|
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||||
|
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||||
|
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||||
|
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||||
|
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
|
||||||
|
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||||
|
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||||
|
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||||
|
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||||
|
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||||
|
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||||
|
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||||
|
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||||
|
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
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|
@ -1,6 +1,7 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597731746 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994396726 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:31 2021 " "Processing started: Tue Sep 14 01:35:31 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:36 2023 " "Processing started: Tue Mar 28 05:06:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1631597731986 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679994396991 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1631597731986 ""}
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679994397038 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing ended: Tue Sep 14 01:35:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1631597732146 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679994397038 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13057 " "Peak virtual memory: 13057 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:37 2023 " "Processing ended: Tue Mar 28 05:06:37 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679994397272 ""}
|
||||||
|
|
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|
@ -1,38 +1,40 @@
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1631597728526 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679994392961 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1631597728536 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679994392961 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679994392961 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1631597728726 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""}
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1631597728736 ""}
|
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1679994393038 ""}
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1631597728876 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679994393054 ""}
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1631597729026 ""}
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679994393132 ""}
|
||||||
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1631597729036 ""}
|
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1679994393225 ""}
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1631597729036 ""}
|
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1679994393241 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1679994393241 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""}
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729046 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393257 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 418 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 417 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 88 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RestoreDone~0 " "Destination \"RestoreDone~0\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 150 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1631597729086 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1679994393272 ""}
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1679994393319 ""}
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1631597729116 ""}
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1631597729116 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1679994393366 ""}
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729186 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679994393366 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1631597729306 ""}
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393413 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729566 ""}
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679994393429 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1631597729576 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679994393554 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1631597730096 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393804 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730096 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679994393804 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1631597730126 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679994394585 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1631597730346 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1631597730346 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994394585 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730656 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679994394632 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1631597730666 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "31 " "Router estimated average interconnect usage is 31% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "31 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679994394866 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679994394866 ""}
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730666 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395147 ""}
|
||||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1631597730716 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.31 " "Total time spent on timing analysis during the Fitter is 0.31 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679994395163 ""}
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1631597730776 ""}
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395179 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "544 " "Peak virtual memory: 544 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:30 2021 " "Processing ended: Tue Sep 14 01:35:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1631597730806 ""}
|
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1679994395225 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679994395272 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13733 " "Peak virtual memory: 13733 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:35 2023 " "Processing ended: Tue Mar 28 05:06:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679994395319 ""}
|
||||||
|
|
|
@ -31,10 +31,10 @@ C25M => WRD[5].CLK
|
||||||
C25M => WRD[6].CLK
|
C25M => WRD[6].CLK
|
||||||
C25M => WRD[7].CLK
|
C25M => WRD[7].CLK
|
||||||
C25M => MOSIout.CLK
|
C25M => MOSIout.CLK
|
||||||
C25M => FCKOE.CLK
|
|
||||||
C25M => MOSIOE.CLK
|
C25M => MOSIOE.CLK
|
||||||
C25M => FCS.CLK
|
C25M => nFCS~reg0.CLK
|
||||||
C25M => FCKout.CLK
|
C25M => FCKout.CLK
|
||||||
|
C25M => RestoreDone.CLK
|
||||||
C25M => Bank.CLK
|
C25M => Bank.CLK
|
||||||
C25M => AddrIncH.CLK
|
C25M => AddrIncH.CLK
|
||||||
C25M => AddrIncM.CLK
|
C25M => AddrIncM.CLK
|
||||||
|
@ -85,9 +85,6 @@ C25M => PS[0].CLK
|
||||||
C25M => PS[1].CLK
|
C25M => PS[1].CLK
|
||||||
C25M => PS[2].CLK
|
C25M => PS[2].CLK
|
||||||
C25M => PS[3].CLK
|
C25M => PS[3].CLK
|
||||||
C25M => SetFWr[0].CLK
|
|
||||||
C25M => SetFWr[1].CLK
|
|
||||||
C25M => SetFWLoaded.CLK
|
|
||||||
C25M => nRESr.CLK
|
C25M => nRESr.CLK
|
||||||
C25M => nRESf[0].CLK
|
C25M => nRESf[0].CLK
|
||||||
C25M => nRESf[1].CLK
|
C25M => nRESf[1].CLK
|
||||||
|
@ -120,10 +117,11 @@ PHI0 => RAr[10].CLK
|
||||||
PHI0 => RAr[11].CLK
|
PHI0 => RAr[11].CLK
|
||||||
PHI0 => CXXXr.CLK
|
PHI0 => CXXXr.CLK
|
||||||
PHI0 => PHI0r1.DATAIN
|
PHI0 => PHI0r1.DATAIN
|
||||||
|
nRES => MOSIout.OUTPUTSELECT
|
||||||
nRES => nRESf[0].DATAIN
|
nRES => nRESf[0].DATAIN
|
||||||
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
SetFW[0] => SetFWr[0].DATAIN
|
SetFW[0] => ~NO_FANOUT~
|
||||||
SetFW[1] => SetFWr[1].DATAIN
|
SetFW[1] => ~NO_FANOUT~
|
||||||
INTin => INTout.DATAIN
|
INTin => INTout.DATAIN
|
||||||
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
DMAin => DMAout.DATAIN
|
DMAin => DMAout.DATAIN
|
||||||
|
@ -135,32 +133,32 @@ nINHout <= <VCC>
|
||||||
RWout <= <VCC>
|
RWout <= <VCC>
|
||||||
nDMAout <= <VCC>
|
nDMAout <= <VCC>
|
||||||
RA[0] => RAr[0].DATAIN
|
RA[0] => RAr[0].DATAIN
|
||||||
RA[0] => Equal16.IN10
|
RA[0] => Equal17.IN10
|
||||||
RA[1] => RAr[1].DATAIN
|
RA[1] => RAr[1].DATAIN
|
||||||
RA[1] => Equal16.IN9
|
RA[1] => Equal17.IN9
|
||||||
RA[2] => RAr[2].DATAIN
|
RA[2] => RAr[2].DATAIN
|
||||||
RA[2] => Equal16.IN8
|
RA[2] => Equal17.IN8
|
||||||
RA[3] => RAr[3].DATAIN
|
RA[3] => RAr[3].DATAIN
|
||||||
RA[3] => Equal16.IN7
|
RA[3] => Equal17.IN7
|
||||||
RA[4] => RAr[4].DATAIN
|
RA[4] => RAr[4].DATAIN
|
||||||
RA[4] => Equal16.IN6
|
RA[4] => Equal17.IN6
|
||||||
RA[5] => RAr[5].DATAIN
|
RA[5] => RAr[5].DATAIN
|
||||||
RA[5] => Equal16.IN5
|
RA[5] => Equal17.IN5
|
||||||
RA[6] => RAr[6].DATAIN
|
RA[6] => RAr[6].DATAIN
|
||||||
RA[6] => Equal16.IN4
|
RA[6] => Equal17.IN4
|
||||||
RA[7] => RAr[7].DATAIN
|
RA[7] => RAr[7].DATAIN
|
||||||
RA[7] => Equal16.IN3
|
RA[7] => Equal17.IN3
|
||||||
RA[8] => RAr[8].DATAIN
|
RA[8] => RAr[8].DATAIN
|
||||||
RA[8] => Equal16.IN2
|
RA[8] => Equal17.IN2
|
||||||
RA[9] => RAr[9].DATAIN
|
RA[9] => RAr[9].DATAIN
|
||||||
RA[9] => Equal16.IN1
|
RA[9] => Equal17.IN1
|
||||||
RA[10] => RAr[10].DATAIN
|
RA[10] => RAr[10].DATAIN
|
||||||
RA[10] => Equal16.IN0
|
RA[10] => Equal17.IN0
|
||||||
RA[11] => RAr[11].DATAIN
|
RA[11] => RAr[11].DATAIN
|
||||||
RA[12] => Equal8.IN1
|
RA[12] => Equal7.IN1
|
||||||
RA[13] => Equal8.IN0
|
RA[13] => Equal7.IN0
|
||||||
RA[14] => Equal8.IN3
|
RA[14] => Equal7.IN3
|
||||||
RA[15] => Equal8.IN2
|
RA[15] => Equal7.IN2
|
||||||
nWE => comb.IN1
|
nWE => comb.IN1
|
||||||
nWE => nWEr.DATAIN
|
nWE => nWEr.DATAIN
|
||||||
RD[0] <> RD[0]
|
RD[0] <> RD[0]
|
||||||
|
@ -173,10 +171,12 @@ RD[6] <> RD[6]
|
||||||
RD[7] <> RD[7]
|
RD[7] <> RD[7]
|
||||||
RAdir <= <VCC>
|
RAdir <= <VCC>
|
||||||
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
|
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
nIOSEL => SA.OUTPUTSELECT
|
||||||
nIOSEL => comb.IN0
|
nIOSEL => comb.IN0
|
||||||
nIOSEL => always7.IN1
|
nIOSEL => always6.IN1
|
||||||
nDEVSEL => comb.IN1
|
nDEVSEL => comb.IN1
|
||||||
nDEVSEL => RAMSEL.IN1
|
nDEVSEL => RAMSEL.IN1
|
||||||
|
nDEVSEL => FCKout.IN1
|
||||||
nDEVSEL => comb.IN1
|
nDEVSEL => comb.IN1
|
||||||
nDEVSEL => RAMRegSEL.IN1
|
nDEVSEL => RAMRegSEL.IN1
|
||||||
nIOSTRB => nIOSTRBr.DATAIN
|
nIOSTRB => nIOSTRBr.DATAIN
|
||||||
|
@ -212,9 +212,10 @@ SD[4] <> SD[4]
|
||||||
SD[5] <> SD[5]
|
SD[5] <> SD[5]
|
||||||
SD[6] <> SD[6]
|
SD[6] <> SD[6]
|
||||||
SD[7] <> SD[7]
|
SD[7] <> SD[7]
|
||||||
nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
|
nFCS <= nFCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
|
FCK <= FCKout.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
MISO => WRD.DATAB
|
MISO => WRD.DATAB
|
||||||
|
MISO => RDD.DATAB
|
||||||
MOSI <> MOSI
|
MOSI <> MOSI
|
||||||
|
|
||||||
|
|
||||||
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -1,19 +1,21 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597725836 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994373538 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:25 2021 " "Processing started: Tue Sep 14 01:35:25 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:13 2023 " "Processing started: Tue Mar 28 05:06:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597726126 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(104) " "Verilog HDL warning at GR8RAM.v(104): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(281) " "Verilog HDL warning at GR8RAM.v(281): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 281 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1631597726256 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994390038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679994390069 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(39) " "Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(128) " "Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(136) " "Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
||||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1631597726806 ""}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(143) " "Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 143 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
|
||||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1631597726986 ""}
|
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1679994390538 ""}
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1631597727226 ""}
|
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 559 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 560 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 558 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 442 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1679994390757 ""}
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1631597727256 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1631597727256 ""}
|
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1679994391085 ""}
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1631597727336 ""}
|
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "422 " "Peak virtual memory: 422 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:27 2021 " "Processing ended: Tue Sep 14 01:35:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "336 " "Implemented 336 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_LCELLS" "256 " "Implemented 256 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679994391100 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391147 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13094 " "Peak virtual memory: 13094 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:31 2023 " "Processing ended: Tue Mar 28 05:06:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391179 ""}
|
||||||
|
|
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0
cpld/db/GR8RAM.syn_hier_info → cpld/db/GR8RAM.quiproj.10860.rdr.flock
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0
cpld/db/GR8RAM.syn_hier_info → cpld/db/GR8RAM.quiproj.10860.rdr.flock
Executable file → Normal file
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|
@ -1,20 +1,22 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597733226 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994398756 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing started: Tue Sep 14 01:35:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:38 2023 " "Processing started: Tue Mar 28 05:06:38 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1631597733306 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679994398866 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597733426 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679994399077 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679994399077 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""}
|
||||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1631597733536 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""}
|
||||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1631597733876 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679994399175 ""}
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1631597733926 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679994399581 ""}
|
||||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1631597733926 ""}
|
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1679994399659 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679994399659 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1679994399690 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.472 " "Worst-case setup slack is 12.472" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.472 0.000 C25M " " 12.472 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.383 " "Worst-case hold slack is 1.383" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.383 0.000 C25M " " 1.383 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.331 " "Worst-case recovery slack is 33.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.331 0.000 C25M " " 33.331 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631597733996 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.115 " "Worst-case removal slack is 6.115" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.115 0.000 C25M " " 6.115 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
|
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1679994399769 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:34 2021 " "Processing ended: Tue Sep 14 01:35:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13052 " "Peak virtual memory: 13052 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:39 2023 " "Processing ended: Tue Mar 28 05:06:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679994399847 ""}
|
||||||
|
|
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|
@ -1,91 +1,11 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994334673 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:05:34 2023 " "Processing started: Tue Mar 28 05:05:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(103) " "Verilog HDL warning at GR8RAM.v(103): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(280) " "Verilog HDL warning at GR8RAM.v(280): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 280 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994351125 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
|
{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW GR8RAM.v(1) " "Verilog HDL error at GR8RAM.v(1): object \"SetFW\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
|
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "13076 " "Peak virtual memory: 13076 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 28 05:05:51 2023 " "Processing ended: Tue Mar 28 05:05:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351157 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
|
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351875 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"}
|
|
||||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""}
|
|
||||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""}
|
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
|
|
||||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""}
|
|
||||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
|
|
||||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""}
|
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
|
|
||||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""}
|
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""}
|
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""}
|
|
||||||
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""}
|
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""}
|
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""}
|
|
||||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""}
|
|
||||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
|
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
|
|
||||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""}
|
|
||||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""}
|
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""}
|
|
||||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}
|
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}
|
|
||||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""}
|
|
||||||
|
|
|
@ -1,3 +1,3 @@
|
||||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Version_Index = 302049280
|
Version_Index = 503488000
|
||||||
Creation_Time = Thu Mar 18 03:51:58 2021
|
Creation_Time = Sat Mar 25 19:21:05 2023
|
||||||
|
|
Binary file not shown.
|
@ -1,6 +1,6 @@
|
||||||
Assembler report for GR8RAM
|
Assembler report for GR8RAM
|
||||||
Tue Sep 14 01:35:32 2021
|
Tue Mar 28 05:06:37 2023
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
2. Assembler Summary
|
2. Assembler Summary
|
||||||
3. Assembler Settings
|
3. Assembler Settings
|
||||||
4. Assembler Generated Files
|
4. Assembler Generated Files
|
||||||
5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
|
5. Assembler Device Options: Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||||
6. Assembler Messages
|
6. Assembler Messages
|
||||||
|
|
||||||
|
|
||||||
|
@ -18,26 +18,27 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
----------------
|
----------------
|
||||||
; Legal Notice ;
|
; Legal Notice ;
|
||||||
----------------
|
----------------
|
||||||
Copyright (C) 1991-2013 Altera Corporation
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and any partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
(including device programming or simulation files), and any
|
(including device programming or simulation files), and any
|
||||||
associated documentation or information are expressly subject
|
associated documentation or information are expressly subject
|
||||||
to the terms and conditions of the Altera Program License
|
to the terms and conditions of the Intel Program License
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
Agreement, or other applicable license agreement, including,
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
without limitation, that your use is for the sole purpose of
|
agreement, including, without limitation, that your use is for
|
||||||
programming logic devices manufactured by Altera and sold by
|
the sole purpose of programming logic devices manufactured by
|
||||||
Altera or its authorized distributors. Please refer to the
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
applicable agreement for further details.
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
; Assembler Summary ;
|
; Assembler Summary ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
; Assembler Status ; Successful - Tue Sep 14 01:35:32 2021 ;
|
; Assembler Status ; Successful - Tue Mar 28 05:06:37 2023 ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
|
@ -45,69 +46,46 @@ applicable agreement for further details.
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------------------+
|
+----------------------------------+
|
||||||
; Assembler Settings ;
|
; Assembler Settings ;
|
||||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
+--------+---------+---------------+
|
||||||
; Option ; Setting ; Default Value ;
|
; Option ; Setting ; Default Value ;
|
||||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
+--------+---------+---------------+
|
||||||
; Use smart compilation ; Off ; Off ;
|
|
||||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
|
||||||
; Enable compact report table ; Off ; Off ;
|
|
||||||
; Compression mode ; Off ; Off ;
|
|
||||||
; Clock source for configuration device ; Internal ; Internal ;
|
|
||||||
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
|
||||||
; Divide clock frequency by ; 1 ; 1 ;
|
|
||||||
; Auto user code ; On ; On ;
|
|
||||||
; Security bit ; Off ; Off ;
|
|
||||||
; Use configuration device ; On ; On ;
|
|
||||||
; Configuration device ; Auto ; Auto ;
|
|
||||||
; Configuration device auto user code ; Off ; Off ;
|
|
||||||
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
|
||||||
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
|
||||||
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
|
||||||
; Hexadecimal Output File start address ; 0 ; 0 ;
|
|
||||||
; Hexadecimal Output File count direction ; Up ; Up ;
|
|
||||||
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
|
||||||
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
|
||||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
|
||||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
|
||||||
; In-System Programming Default Clamp State ; Tri-state ; Tri-state ;
|
|
||||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------+
|
+----------------------------------------------+
|
||||||
; Assembler Generated Files ;
|
; Assembler Generated Files ;
|
||||||
+-------------------------------------------------------------------+
|
+----------------------------------------------+
|
||||||
; File Name ;
|
; File Name ;
|
||||||
+-------------------------------------------------------------------+
|
+----------------------------------------------+
|
||||||
; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
; Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||||
+-------------------------------------------------------------------+
|
+----------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------+
|
||||||
; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
; Assembler Device Options: Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||||
+----------------+----------------------------------------------------------------------------+
|
+----------------+-------------------------------------------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+----------------+----------------------------------------------------------------------------+
|
+----------------+-------------------------------------------------------+
|
||||||
; Device ; EPM240T100C5 ;
|
; JTAG usercode ; 0x001615F8 ;
|
||||||
; JTAG usercode ; 0x00161CF0 ;
|
; Checksum ; 0x001618F8 ;
|
||||||
; Checksum ; 0x001620E8 ;
|
+----------------+-------------------------------------------------------+
|
||||||
+----------------+----------------------------------------------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+--------------------+
|
+--------------------+
|
||||||
; Assembler Messages ;
|
; Assembler Messages ;
|
||||||
+--------------------+
|
+--------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 64-Bit Assembler
|
Info: Running Quartus Prime Assembler
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Sep 14 01:35:31 2021
|
Info: Processing started: Tue Mar 28 05:06:36 2023
|
||||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (115031): Writing out detailed assembly data for power analysis
|
Info (115031): Writing out detailed assembly data for power analysis
|
||||||
Info (115030): Assembler is generating device programming files
|
Info (115030): Assembler is generating device programming files
|
||||||
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 381 megabytes
|
Info: Peak virtual memory: 13057 megabytes
|
||||||
Info: Processing ended: Tue Sep 14 01:35:32 2021
|
Info: Processing ended: Tue Mar 28 05:06:37 2023
|
||||||
Info: Elapsed time: 00:00:01
|
Info: Elapsed time: 00:00:01
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
|
@ -1 +1 @@
|
||||||
Tue Sep 14 01:35:34 2021
|
Tue Mar 28 05:06:40 2023
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,11 +1,11 @@
|
||||||
Fitter Status : Successful - Tue Sep 14 01:35:30 2021
|
Fitter Status : Successful - Tue Mar 28 05:06:35 2023
|
||||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX II
|
Family : MAX II
|
||||||
Device : EPM240T100C5
|
Device : EPM240T100C5
|
||||||
Timing Models : Final
|
Timing Models : Final
|
||||||
Total logic elements : 234 / 240 ( 98 % )
|
Total logic elements : 236 / 240 ( 98 % )
|
||||||
Total pins : 80 / 80 ( 100 % )
|
Total pins : 80 / 80 ( 100 % )
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
UFM blocks : 0 / 1 ( 0 % )
|
UFM blocks : 0 / 1 ( 0 % )
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
Flow report for GR8RAM
|
Flow report for GR8RAM
|
||||||
Tue Sep 14 01:35:34 2021
|
Tue Mar 28 05:06:39 2023
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
@ -21,37 +21,38 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
----------------
|
----------------
|
||||||
; Legal Notice ;
|
; Legal Notice ;
|
||||||
----------------
|
----------------
|
||||||
Copyright (C) 1991-2013 Altera Corporation
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and any partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
(including device programming or simulation files), and any
|
(including device programming or simulation files), and any
|
||||||
associated documentation or information are expressly subject
|
associated documentation or information are expressly subject
|
||||||
to the terms and conditions of the Altera Program License
|
to the terms and conditions of the Intel Program License
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
Agreement, or other applicable license agreement, including,
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
without limitation, that your use is for the sole purpose of
|
agreement, including, without limitation, that your use is for
|
||||||
programming logic devices manufactured by Altera and sold by
|
the sole purpose of programming logic devices manufactured by
|
||||||
Altera or its authorized distributors. Please refer to the
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
applicable agreement for further details.
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------------------------------+
|
+---------------------------------------------------------------------+
|
||||||
; Flow Summary ;
|
; Flow Summary ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+-----------------------+---------------------------------------------+
|
||||||
; Flow Status ; Successful - Tue Sep 14 01:35:32 2021 ;
|
; Flow Status ; Successful - Tue Mar 28 05:06:37 2023 ;
|
||||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Device ; EPM240T100C5 ;
|
; Device ; EPM240T100C5 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Total logic elements ; 234 / 240 ( 98 % ) ;
|
; Total logic elements ; 236 / 240 ( 98 % ) ;
|
||||||
; Total pins ; 80 / 80 ( 100 % ) ;
|
; Total pins ; 80 / 80 ( 100 % ) ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+-----------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------+
|
+-----------------------------------------+
|
||||||
|
@ -59,27 +60,27 @@ applicable agreement for further details.
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Start date & time ; 09/14/2021 01:35:26 ;
|
; Start date & time ; 03/28/2023 05:06:13 ;
|
||||||
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Flow Non-Default Global Settings ;
|
; Flow Non-Default Global Settings ;
|
||||||
+-------------------------------------------------+------------------------------+---------------+-------------+------------+
|
+-------------------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
+-------------------------------------------------+------------------------------+---------------+-------------+------------+
|
+-------------------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||||
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
|
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
|
||||||
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
|
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
|
||||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||||
; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
|
; AUTO_PACKED_REGISTERS_MAX ; Minimize Area ; Auto ; -- ; -- ;
|
||||||
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
|
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
|
||||||
; COMPILER_SIGNATURE_ID ; 962837114763.163159772501756 ; -- ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 121381084694.167999437303928 ; -- ; -- ; -- ;
|
||||||
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
|
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
|
||||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||||
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
|
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
|
||||||
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
|
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
|
||||||
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
|
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
|
||||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||||
|
@ -93,33 +94,33 @@ applicable agreement for further details.
|
||||||
; SEED ; 235 ; 1 ; -- ; -- ;
|
; SEED ; 235 ; 1 ; -- ; -- ;
|
||||||
; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ;
|
; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ;
|
||||||
; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ;
|
; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ;
|
||||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; -- (Not supported for targeted family) ; -- ; -- ; -- ;
|
||||||
+-------------------------------------------------+------------------------------+---------------+-------------+------------+
|
+-------------------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Flow Elapsed Time ;
|
; Flow Elapsed Time ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 422 MB ; 00:00:01 ;
|
; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 13094 MB ; 00:00:39 ;
|
||||||
; Fitter ; 00:00:02 ; 1.0 ; 544 MB ; 00:00:02 ;
|
; Fitter ; 00:00:03 ; 1.0 ; 13733 MB ; 00:00:04 ;
|
||||||
; Assembler ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:01 ;
|
; Assembler ; 00:00:01 ; 1.0 ; 13053 MB ; 00:00:01 ;
|
||||||
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 374 MB ; 00:00:01 ;
|
; Timing Analyzer ; 00:00:01 ; 1.0 ; 13052 MB ; 00:00:01 ;
|
||||||
; Total ; 00:00:07 ; -- ; -- ; 00:00:05 ;
|
; Total ; 00:00:23 ; -- ; -- ; 00:00:45 ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------+
|
||||||
; Flow OS Summary ;
|
; Flow OS Summary ;
|
||||||
+---------------------------+------------------+-----------+------------+----------------+
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||||
+---------------------------+------------------+-----------+------------+----------------+
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
; Analysis & Synthesis ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
; Fitter ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
; Assembler ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
; TimeQuest Timing Analyzer ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
+---------------------------+------------------+-----------+------------+----------------+
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
------------
|
------------
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
<sld_project_info>
|
<sld_project_info>
|
||||||
<project>
|
<project>
|
||||||
<hash md5_digest_80b="5cae6640443712869b47"/>
|
<hash md5_digest_80b="d50e59ac0621234423dc"/>
|
||||||
</project>
|
</project>
|
||||||
<file_info>
|
<file_info>
|
||||||
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
Analysis & Synthesis report for GR8RAM
|
Analysis & Synthesis report for GR8RAM
|
||||||
Tue Sep 14 01:35:27 2021
|
Tue Mar 28 05:06:31 2023
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
@ -26,45 +26,46 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
----------------
|
----------------
|
||||||
; Legal Notice ;
|
; Legal Notice ;
|
||||||
----------------
|
----------------
|
||||||
Copyright (C) 1991-2013 Altera Corporation
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and any partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
(including device programming or simulation files), and any
|
(including device programming or simulation files), and any
|
||||||
associated documentation or information are expressly subject
|
associated documentation or information are expressly subject
|
||||||
to the terms and conditions of the Altera Program License
|
to the terms and conditions of the Intel Program License
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
Agreement, or other applicable license agreement, including,
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
without limitation, that your use is for the sole purpose of
|
agreement, including, without limitation, that your use is for
|
||||||
programming logic devices manufactured by Altera and sold by
|
the sole purpose of programming logic devices manufactured by
|
||||||
Altera or its authorized distributors. Please refer to the
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
applicable agreement for further details.
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Summary ;
|
; Analysis & Synthesis Summary ;
|
||||||
+-----------------------------+-------------------------------------------------+
|
+-----------------------------+---------------------------------------------+
|
||||||
; Analysis & Synthesis Status ; Successful - Tue Sep 14 01:35:27 2021 ;
|
; Analysis & Synthesis Status ; Successful - Tue Mar 28 05:06:31 2023 ;
|
||||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Total logic elements ; 257 ;
|
; Total logic elements ; 256 ;
|
||||||
; Total pins ; 80 ;
|
; Total pins ; 80 ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
+-----------------------------+-------------------------------------------------+
|
+-----------------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Settings ;
|
; Analysis & Synthesis Settings ;
|
||||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
; Option ; Setting ; Default Value ;
|
; Option ; Setting ; Default Value ;
|
||||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
; Device ; EPM240T100C5 ; ;
|
; Device ; EPM240T100C5 ; ;
|
||||||
; Top-level entity name ; GR8RAM ; GR8RAM ;
|
; Top-level entity name ; GR8RAM ; GR8RAM ;
|
||||||
; Family name ; MAX II ; Cyclone IV GX ;
|
; Family name ; MAX II ; Cyclone V ;
|
||||||
; Restructure Multiplexers ; On ; Auto ;
|
; Restructure Multiplexers ; On ; Auto ;
|
||||||
; State Machine Processing ; Minimal Bits ; Auto ;
|
; State Machine Processing ; Minimal Bits ; Auto ;
|
||||||
; Remove Redundant Logic Cells ; On ; Off ;
|
; Remove Redundant Logic Cells ; On ; Off ;
|
||||||
|
@ -72,13 +73,12 @@ applicable agreement for further details.
|
||||||
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
|
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
|
||||||
; Allow Shift Register Merging across Hierarchies ; Always ; Auto ;
|
; Allow Shift Register Merging across Hierarchies ; Always ; Auto ;
|
||||||
; Auto Resource Sharing ; On ; Off ;
|
; Auto Resource Sharing ; On ; Off ;
|
||||||
; Synthesis Seed ; 123 ; 1 ;
|
|
||||||
; Use smart compilation ; Off ; Off ;
|
; Use smart compilation ; Off ; Off ;
|
||||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
||||||
; Enable compact report table ; Off ; Off ;
|
; Enable compact report table ; Off ; Off ;
|
||||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||||
; Preserve fewer node names ; On ; On ;
|
; Preserve fewer node names ; On ; On ;
|
||||||
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
||||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||||
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||||
; Safe State Machine ; Off ; Off ;
|
; Safe State Machine ; Off ; Off ;
|
||||||
|
@ -114,7 +114,7 @@ applicable agreement for further details.
|
||||||
; Report Connectivity Checks ; On ; On ;
|
; Report Connectivity Checks ; On ; On ;
|
||||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
||||||
; HDL message level ; Level2 ; Level2 ;
|
; HDL message level ; Level2 ; Level2 ;
|
||||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||||
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
@ -124,30 +124,34 @@ applicable agreement for further details.
|
||||||
; Block Design Naming ; Auto ; Auto ;
|
; Block Design Naming ; Auto ; Auto ;
|
||||||
; Synthesis Effort ; Auto ; Auto ;
|
; Synthesis Effort ; Auto ; Auto ;
|
||||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||||
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
|
||||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
+------------------------------------------+
|
||||||
+-------------------------------------+
|
|
||||||
; Parallel Compilation ;
|
; Parallel Compilation ;
|
||||||
+----------------------------+--------+
|
+----------------------------+-------------+
|
||||||
; Processors ; Number ;
|
; Processors ; Number ;
|
||||||
+----------------------------+--------+
|
+----------------------------+-------------+
|
||||||
; Number detected on machine ; 12 ;
|
; Number detected on machine ; 4 ;
|
||||||
; Maximum allowed ; 1 ;
|
; Maximum allowed ; 4 ;
|
||||||
+----------------------------+--------+
|
; ; ;
|
||||||
|
; Average used ; 1.00 ;
|
||||||
|
; Maximum used ; 1 ;
|
||||||
|
; ; ;
|
||||||
|
; Usage by Processor ; % Time Used ;
|
||||||
|
; Processor 1 ; 100.0% ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Source Files Read ;
|
; Analysis & Synthesis Source Files Read ;
|
||||||
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
|
||||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||||
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
|
||||||
; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ;
|
; GR8RAM.v ; yes ; User Verilog HDL File ; Y:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
||||||
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+-------------------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------+
|
+-----------------------------------------------------+
|
||||||
|
@ -155,43 +159,43 @@ Parallel compilation was disabled, but you have multiple processors available. E
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
; Total logic elements ; 257 ;
|
; Total logic elements ; 256 ;
|
||||||
; -- Combinational with no register ; 136 ;
|
; -- Combinational with no register ; 139 ;
|
||||||
; -- Register only ; 24 ;
|
; -- Register only ; 21 ;
|
||||||
; -- Combinational with a register ; 97 ;
|
; -- Combinational with a register ; 96 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic element usage by number of LUT inputs ; ;
|
; Logic element usage by number of LUT inputs ; ;
|
||||||
; -- 4 input functions ; 126 ;
|
; -- 4 input functions ; 137 ;
|
||||||
; -- 3 input functions ; 41 ;
|
; -- 3 input functions ; 35 ;
|
||||||
; -- 2 input functions ; 65 ;
|
; -- 2 input functions ; 63 ;
|
||||||
; -- 1 input functions ; 0 ;
|
; -- 1 input functions ; 0 ;
|
||||||
; -- 0 input functions ; 1 ;
|
; -- 0 input functions ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic elements by mode ; ;
|
; Logic elements by mode ; ;
|
||||||
; -- normal mode ; 224 ;
|
; -- normal mode ; 223 ;
|
||||||
; -- arithmetic mode ; 33 ;
|
; -- arithmetic mode ; 33 ;
|
||||||
; -- qfbk mode ; 0 ;
|
; -- qfbk mode ; 0 ;
|
||||||
; -- register cascade mode ; 0 ;
|
; -- register cascade mode ; 0 ;
|
||||||
; -- synchronous clear/load mode ; 45 ;
|
; -- synchronous clear/load mode ; 44 ;
|
||||||
; -- asynchronous clear/load mode ; 29 ;
|
; -- asynchronous clear/load mode ; 29 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Total registers ; 121 ;
|
; Total registers ; 117 ;
|
||||||
; Total logic cells in carry chains ; 37 ;
|
; Total logic cells in carry chains ; 37 ;
|
||||||
; I/O pins ; 80 ;
|
; I/O pins ; 80 ;
|
||||||
; Maximum fan-out node ; C25M ;
|
; Maximum fan-out node ; C25M ;
|
||||||
; Maximum fan-out ; 107 ;
|
; Maximum fan-out ; 103 ;
|
||||||
; Total fan-out ; 1095 ;
|
; Total fan-out ; 1104 ;
|
||||||
; Average fan-out ; 3.25 ;
|
; Average fan-out ; 3.29 ;
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; |GR8RAM ; 257 (257) ; 121 ; 0 ; 80 ; 0 ; 136 (136) ; 24 (24) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
|
; |GR8RAM ; 256 (256) ; 117 ; 0 ; 80 ; 0 ; 139 (139) ; 21 (21) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
||||||
|
@ -210,14 +214,15 @@ Encoding Type: Minimal Bits
|
||||||
+--------+----------------+----------------+----------------+
|
+--------+----------------+----------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------+
|
+--------------------------------------------------------------------------------+
|
||||||
; Registers Removed During Synthesis ;
|
; Registers Removed During Synthesis ;
|
||||||
+---------------------------------------+--------------------+
|
+---------------------------------------+----------------------------------------+
|
||||||
; Register name ; Reason for Removal ;
|
; Register name ; Reason for Removal ;
|
||||||
+---------------------------------------+--------------------+
|
+---------------------------------------+----------------------------------------+
|
||||||
|
; SBA[0]~reg0 ; Stuck at GND due to stuck port data_in ;
|
||||||
; IS~10 ; Lost fanout ;
|
; IS~10 ; Lost fanout ;
|
||||||
; Total Number of Removed Registers = 1 ; ;
|
; Total Number of Removed Registers = 2 ; ;
|
||||||
+---------------------------------------+--------------------+
|
+---------------------------------------+----------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------+
|
+------------------------------------------------------+
|
||||||
|
@ -225,12 +230,12 @@ Encoding Type: Minimal Bits
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
; Statistic ; Value ;
|
; Statistic ; Value ;
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
; Total registers ; 121 ;
|
; Total registers ; 117 ;
|
||||||
; Number of registers using Synchronous Clear ; 12 ;
|
; Number of registers using Synchronous Clear ; 11 ;
|
||||||
; Number of registers using Synchronous Load ; 33 ;
|
; Number of registers using Synchronous Load ; 33 ;
|
||||||
; Number of registers using Asynchronous Clear ; 29 ;
|
; Number of registers using Asynchronous Clear ; 29 ;
|
||||||
; Number of registers using Asynchronous Load ; 0 ;
|
; Number of registers using Asynchronous Load ; 0 ;
|
||||||
; Number of registers using Clock Enable ; 24 ;
|
; Number of registers using Clock Enable ; 22 ;
|
||||||
; Number of registers using Preset ; 0 ;
|
; Number of registers using Preset ; 0 ;
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
|
|
||||||
|
@ -247,7 +252,8 @@ Encoding Type: Minimal Bits
|
||||||
; DQML~reg0 ; 1 ;
|
; DQML~reg0 ; 1 ;
|
||||||
; DQMH~reg0 ; 1 ;
|
; DQMH~reg0 ; 1 ;
|
||||||
; RCKE~reg0 ; 1 ;
|
; RCKE~reg0 ; 1 ;
|
||||||
; Total number of inverted registers = 7 ; ;
|
; nFCS~reg0 ; 1 ;
|
||||||
|
; Total number of inverted registers = 8 ; ;
|
||||||
+----------------------------------------+---------+
|
+----------------------------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
|
@ -257,14 +263,13 @@ Encoding Type: Minimal Bits
|
||||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||||
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
|
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
|
||||||
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
|
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[9]~reg0 ;
|
||||||
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ;
|
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[8]~reg0 ;
|
||||||
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
|
; 20:1 ; 2 bits ; 26 LEs ; 12 LEs ; 14 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
|
||||||
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ;
|
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[0] ;
|
||||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
|
; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |GR8RAM|RDD[0] ;
|
||||||
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
|
|
||||||
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
||||||
; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ;
|
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
@ -272,45 +277,50 @@ Encoding Type: Minimal Bits
|
||||||
; Analysis & Synthesis Messages ;
|
; Analysis & Synthesis Messages ;
|
||||||
+-------------------------------+
|
+-------------------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Sep 14 01:35:25 2021
|
Info: Processing started: Tue Mar 28 05:06:13 2023
|
||||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||||
Info (12023): Found entity 1: GR8RAM
|
Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
|
||||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 34
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 39
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 128
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 136
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 143
|
||||||
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
||||||
Warning (13024): Output pins are stuck at VCC or GND
|
Warning (13024): Output pins are stuck at VCC or GND
|
||||||
Warning (13410): Pin "nNMIout" is stuck at VCC
|
Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 559
|
||||||
Warning (13410): Pin "nIRQout" is stuck at VCC
|
Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
|
||||||
Warning (13410): Pin "nRDYout" is stuck at VCC
|
Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
|
||||||
Warning (13410): Pin "nINHout" is stuck at VCC
|
Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 560
|
||||||
Warning (13410): Pin "RWout" is stuck at VCC
|
Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
|
||||||
Warning (13410): Pin "nDMAout" is stuck at VCC
|
Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 558
|
||||||
Warning (13410): Pin "RAdir" is stuck at VCC
|
Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 557
|
||||||
|
Warning (13410): Pin "SBA[0]" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 442
|
||||||
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
||||||
Info (21057): Implemented 337 device resources after synthesis - the final resource count might be different
|
Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
||||||
|
Warning (15610): No output dependent on input pin "SetFW[0]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23
|
||||||
|
Warning (15610): No output dependent on input pin "SetFW[1]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23
|
||||||
|
Info (21057): Implemented 336 device resources after synthesis - the final resource count might be different
|
||||||
Info (21058): Implemented 28 input pins
|
Info (21058): Implemented 28 input pins
|
||||||
Info (21059): Implemented 35 output pins
|
Info (21059): Implemented 35 output pins
|
||||||
Info (21060): Implemented 17 bidirectional pins
|
Info (21060): Implemented 17 bidirectional pins
|
||||||
Info (21061): Implemented 257 logic cells
|
Info (21061): Implemented 256 logic cells
|
||||||
Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||||
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings
|
||||||
Info: Peak virtual memory: 422 megabytes
|
Info: Peak virtual memory: 13094 megabytes
|
||||||
Info: Processing ended: Tue Sep 14 01:35:27 2021
|
Info: Processing ended: Tue Mar 28 05:06:31 2023
|
||||||
Info: Elapsed time: 00:00:02
|
Info: Elapsed time: 00:00:18
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:39
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------+
|
+------------------------------------------+
|
||||||
; Analysis & Synthesis Suppressed Messages ;
|
; Analysis & Synthesis Suppressed Messages ;
|
||||||
+------------------------------------------+
|
+------------------------------------------+
|
||||||
The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
The suppressed messages can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -1,2 +1,2 @@
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z"
|
Warning (10273): Verilog HDL warning at GR8RAM.v(104): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 104
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z"
|
Warning (10273): Verilog HDL warning at GR8RAM.v(281): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 281
|
||||||
|
|
|
@ -1,9 +1,9 @@
|
||||||
Analysis & Synthesis Status : Successful - Tue Sep 14 01:35:27 2021
|
Analysis & Synthesis Status : Successful - Tue Mar 28 05:06:31 2023
|
||||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX II
|
Family : MAX II
|
||||||
Total logic elements : 257
|
Total logic elements : 256
|
||||||
Total pins : 80
|
Total pins : 80
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
UFM blocks : 0 / 1 ( 0 % )
|
UFM blocks : 0 / 1 ( 0 % )
|
||||||
|
|
|
@ -1,21 +1,22 @@
|
||||||
-- Copyright (C) 1991-2013 Altera Corporation
|
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
-- Your use of Intel Corporation's design tools, logic functions
|
||||||
-- and other software and tools, and its AMPP partner logic
|
-- and other software and tools, and any partner logic
|
||||||
-- functions, and any output files from any of the foregoing
|
-- functions, and any output files from any of the foregoing
|
||||||
-- (including device programming or simulation files), and any
|
-- (including device programming or simulation files), and any
|
||||||
-- associated documentation or information are expressly subject
|
-- associated documentation or information are expressly subject
|
||||||
-- to the terms and conditions of the Altera Program License
|
-- to the terms and conditions of the Intel Program License
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
-- Agreement, or other applicable license agreement, including,
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||||
-- without limitation, that your use is for the sole purpose of
|
-- agreement, including, without limitation, that your use is for
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
-- the sole purpose of programming logic devices manufactured by
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
-- Intel and sold by Intel or its authorized distributors. Please
|
||||||
-- applicable agreement for further details.
|
-- refer to the applicable agreement for further details, at
|
||||||
|
-- https://fpgasoftware.intel.com/eula.
|
||||||
--
|
--
|
||||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
|
||||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
-- not intended for use as a Quartus Prime input file. This file cannot be used
|
||||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
-- to make Quartus Prime pin assignments - for instructions on how to make pin
|
||||||
-- assignments, please see Quartus II help.
|
-- assignments, please see Quartus Prime help.
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
@ -57,7 +58,7 @@
|
||||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
|
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
|
||||||
|
|
||||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||||
|
|
Binary file not shown.
|
@ -0,0 +1 @@
|
||||||
|
<sld_project_info/>
|
File diff suppressed because it is too large
Load Diff
|
@ -1,21 +1,21 @@
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
TimeQuest Timing Analyzer Summary
|
Timing Analyzer Summary
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
|
|
||||||
Type : Setup 'C25M'
|
Type : Setup 'C25M'
|
||||||
Slack : 12.419
|
Slack : 12.472
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Hold 'C25M'
|
Type : Hold 'C25M'
|
||||||
Slack : 1.393
|
Slack : 1.383
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Recovery 'C25M'
|
Type : Recovery 'C25M'
|
||||||
Slack : 33.300
|
Slack : 33.331
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Removal 'C25M'
|
Type : Removal 'C25M'
|
||||||
Slack : 6.146
|
Slack : 6.115
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Minimum Pulse Width 'C25M'
|
Type : Minimum Pulse Width 'C25M'
|
||||||
|
|
|
@ -1,6 +1,8 @@
|
||||||
(sym_lib_table
|
(sym_lib_table
|
||||||
|
(version 7)
|
||||||
(lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
|
(lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
|
||||||
(lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
|
(lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
|
||||||
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
|
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
|
||||||
(lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
|
(lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
|
||||||
|
(lib (name "GW_Analog")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Analog.kicad_sym")(options "")(descr ""))
|
||||||
)
|
)
|
||||||
|
|
Loading…
Reference in New Issue