d8a5dc069d
idk
2021-04-11 15:39:19 -04:00
fc2e875ac2
Works?
2021-04-03 03:44:42 -04:00
763861e444
ugh
2021-03-19 16:38:48 -04:00
fdbc92725a
Remove old CPLD stuff
2021-03-15 13:40:41 -04:00
88a4169ab6
Fixed previous problem, working again
2020-02-16 00:11:12 -05:00
3e06d30382
Fixed bugs in new PLD stuff
2019-10-20 22:41:24 -04:00
79dd794f45
New PLD revision
...
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
21f18c14db
Recompiled just to be sure
2019-10-13 21:18:41 -04:00
cf16763591
24-bit counter, CAS fixed
2019-10-11 20:34:51 -04:00
2382fdfda6
Made AddrH high bit variable with mode input
2019-09-07 21:16:23 -04:00
47a4c012d7
Pipelined addition
2019-09-04 21:45:56 -04:00
a73cbf10ef
Clarifications and bugfixes, will try again
2019-09-02 01:42:07 -04:00
5b230c0966
1MB CPLD design seems to work, fails Apple BIST
2019-09-01 21:18:44 -04:00
e78807ce85
CPLD firmware compiles
2019-08-31 22:55:04 -04:00
Zane Kaminski