mirror of
https://github.com/brouhaha/Apple-II_MiSTer.git
synced 2024-10-13 05:23:53 +00:00
Update API.
This commit is contained in:
sorgelig
parent
78415b210d
commit
9ad8db5503
2
.gitignore
vendored
2
.gitignore
vendored
@ -35,3 +35,5 @@ c5_pin_model_dump.txt
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*.bsf
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*~
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*.xml
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*_netlist
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*.cdf
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@ -50,7 +50,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
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set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name FITTER_EFFORT "FAST FIT"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZATION_MODE BALANCED
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set_global_assignment -name SEED 1
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@ -353,9 +353,8 @@ set_location_assignment PIN_W20 -to SW[3]
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
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set_global_assignment -name CDF_FILE jtag_lite.cdf
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set_global_assignment -name CDF_FILE jtag.cdf
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set_global_assignment -name QIP_FILE sys/sys.qip
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set_global_assignment -name QIP_FILE sys/sysmem.qip
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set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd
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set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd
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set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd
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@ -374,5 +373,5 @@ set_global_assignment -name VHDL_FILE vga_controller.vhd
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set_global_assignment -name VHDL_FILE PS2_Ctrl.vhd
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set_global_assignment -name VHDL_FILE roms.vhd
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set_global_assignment -name VHDL_FILE apple2_top.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE Apple-II.sv
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set_global_assignment -name SYSTEMVERILOG_FILE "Apple-II.sv"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -49,7 +49,7 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
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set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZATION_MODE BALANCED
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set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
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set_global_assignment -name SEED 1
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#============================================================
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@ -353,7 +353,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
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set_global_assignment -name CDF_FILE jtag.cdf
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set_global_assignment -name QIP_FILE sys/sys.qip
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set_global_assignment -name QIP_FILE sys/vip.qip
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set_global_assignment -name QSYS_FILE sys/vip.qsys
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set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd
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set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd
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set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd
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62
Apple-II.srf
62
Apple-II.srf
@ -1,51 +1,29 @@
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{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_mode_banks.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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10
Apple-II.sv
10
Apple-II.sv
@ -2,7 +2,7 @@
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// Apple II+
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//
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// Port to MiSTer
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// Copyright (C) 2017 Sorgelig
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// Copyright (C) 2017,2018 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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@ -29,7 +29,7 @@ module emu
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input RESET,
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//Must be passed to hps_io module
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inout [43:0] HPS_BUS,
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inout [44:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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@ -51,7 +51,7 @@ module emu
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status ORed with b[0]
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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@ -60,6 +60,7 @@ module emu
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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input TAPE_IN,
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// SD-SPI
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@ -67,6 +68,7 @@ module emu
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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@ -116,6 +118,7 @@ parameter CONF_STR = {
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"O23,Display,Color,B&W,Green,Amber;",
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"-;",
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"O4,Mocking board,Yes,No;",
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"O78,Stereo mix,none,25%,50%,100%;",
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"-;",
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"T6,Reset;",
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"J,Fire 1,Fire 2;",
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@ -205,6 +208,7 @@ wire speaker;
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assign AUDIO_L = {1'b0, audio_l, 7'd0} + {2'b0, speaker, 13'd0};
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assign AUDIO_R = {1'b0, audio_r, 7'd0} + {2'b0, speaker, 13'd0};
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assign AUDIO_S = 0;
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assign AUDIO_MIX = status[8:7];
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assign CLK_VIDEO = clk_vid;
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assign CE_PIXEL = 1;
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@ -13,8 +13,6 @@ rmdir /s /q .qsys_edit
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rmdir /s /q hps_isw_handoff
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rmdir /s /q sys\.qsys_edit
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rmdir /s /q sys\vip
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rmdir /s /q diskemu\.qsys_edit
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rmdir /s /q diskemu\diskemu
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cd sys
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for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
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cd ..
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@ -33,7 +31,8 @@ del /s *.bsf
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del /s *.f
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del /s *.sopcinfo
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del /s *.xml
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del *.cdf
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del *.rpt
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del /s new_rtl_netlist
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del /s old_rtl_netlist
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pause
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15
jtag.cdf
15
jtag.cdf
@ -1,15 +0,0 @@
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/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
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JedecChain;
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FileRevision(JESD32A);
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DefaultMfr(6E);
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P ActionCode(Ign)
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Device PartName(SOCVHPS) MfrSpec(OpMask(0));
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P ActionCode(Cfg)
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Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II.sof") MfrSpec(OpMask(1));
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ChainEnd;
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AlteraBegin;
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ChainType(JTAG);
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AlteraEnd;
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@ -1,15 +0,0 @@
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/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
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JedecChain;
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FileRevision(JESD32A);
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DefaultMfr(6E);
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P ActionCode(Ign)
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Device PartName(SOCVHPS) MfrSpec(OpMask(0));
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P ActionCode(Cfg)
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Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II-lite.sof") MfrSpec(OpMask(1));
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ChainEnd;
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AlteraBegin;
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ChainType(JTAG);
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AlteraEnd;
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90
spram.vhd
90
spram.vhd
@ -1,90 +0,0 @@
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY spram IS
|
||||
GENERIC
|
||||
(
|
||||
init_file : string := "";
|
||||
widthad_a : natural;
|
||||
width_a : natural := 8;
|
||||
outdata_reg_a : string := "UNREGISTERED"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
wren : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END spram;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF spram IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
init_file : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
power_up_uninitialized : STRING;
|
||||
read_during_write_mode_port_a : STRING;
|
||||
widthad_a : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_byteena_a : NATURAL
|
||||
);
|
||||
PORT (
|
||||
wren_a : IN STD_LOGIC ;
|
||||
clock0 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(width_a-1 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 49152,
|
||||
operation_mode => "SINGLE_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => outdata_reg_a,
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => widthad_a,
|
||||
width_a => width_a,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
wren_a => wren,
|
||||
clock0 => clock,
|
||||
address_a => address,
|
||||
data_a => data,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
@ -1,15 +1,6 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
# Build TimeStamp Verilog Module
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
@ -31,5 +22,48 @@ proc generateBuildID_Verilog {} {
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
# Build CDF file
|
||||
# Sorgelig - 17/2/2018
|
||||
proc generateCDF {revision device outpath} {
|
||||
|
||||
set outputFileName "jtag.cdf"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
puts $outputFile "JedecChain;"
|
||||
puts $outputFile " FileRevision(JESD32A);"
|
||||
puts $outputFile " DefaultMfr(6E);"
|
||||
puts $outputFile ""
|
||||
puts $outputFile " P ActionCode(Ign)"
|
||||
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
|
||||
puts $outputFile " P ActionCode(Cfg)"
|
||||
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
|
||||
puts $outputFile "ChainEnd;"
|
||||
puts $outputFile ""
|
||||
puts $outputFile "AlteraBegin;"
|
||||
puts $outputFile " ChainType(JTAG);"
|
||||
puts $outputFile "AlteraEnd;"
|
||||
}
|
||||
|
||||
set project_name [lindex $quartus(args) 1]
|
||||
set revision [lindex $quartus(args) 2]
|
||||
|
||||
if {[project_exists $project_name]} {
|
||||
if {[string equal "" $revision]} {
|
||||
project_open $project_name -revision [get_current_revision $project_name]
|
||||
} else {
|
||||
project_open $project_name -revision $revision
|
||||
}
|
||||
} else {
|
||||
post_message -type error "Project $project_name does not exist"
|
||||
exit
|
||||
}
|
||||
|
||||
set device [get_global_assignment -name DEVICE]
|
||||
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
|
||||
|
||||
if [is_project_open] {
|
||||
project_close
|
||||
}
|
||||
|
||||
generateBuildID_Verilog
|
||||
generateCDF $revision $device $outpath
|
||||
|
||||
132
sys/ddram.sv
132
sys/ddram.sv
@ -1,132 +0,0 @@
|
||||
//
|
||||
// ddram.v
|
||||
//
|
||||
// DE10-nano DDR3 memory interface
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// ------------------------------------------
|
||||
//
|
||||
|
||||
// 8-bit version
|
||||
|
||||
module ddram
|
||||
(
|
||||
input reset,
|
||||
input DDRAM_CLK,
|
||||
|
||||
input DDRAM_BUSY,
|
||||
output [7:0] DDRAM_BURSTCNT,
|
||||
output [28:0] DDRAM_ADDR,
|
||||
input [63:0] DDRAM_DOUT,
|
||||
input DDRAM_DOUT_READY,
|
||||
output DDRAM_RD,
|
||||
output [63:0] DDRAM_DIN,
|
||||
output [7:0] DDRAM_BE,
|
||||
output DDRAM_WE,
|
||||
|
||||
input [27:0] addr, // 256MB at the end of 1GB
|
||||
output [7:0] dout, // data output to cpu
|
||||
input [7:0] din, // data input from cpu
|
||||
input we, // cpu requests write
|
||||
input rd, // cpu requests read
|
||||
output ready // dout is valid. Ready to accept new read/write.
|
||||
);
|
||||
|
||||
assign DDRAM_BURSTCNT = 1;
|
||||
assign DDRAM_BE = (8'd1<<ram_address[2:0]) | {8{ram_read}};
|
||||
assign DDRAM_ADDR = {4'b0011, ram_address[27:3]}; // RAM at 0x30000000
|
||||
assign DDRAM_RD = ram_read;
|
||||
assign DDRAM_DIN = ram_cache;
|
||||
assign DDRAM_WE = ram_write;
|
||||
|
||||
assign dout = ram_q;
|
||||
assign ready = ~busy;
|
||||
|
||||
reg [7:0] ram_q;
|
||||
reg [27:0] ram_address;
|
||||
reg ram_read;
|
||||
reg [63:0] ram_cache;
|
||||
reg ram_write;
|
||||
reg [7:0] cached;
|
||||
reg busy;
|
||||
|
||||
|
||||
always @(posedge DDRAM_CLK)
|
||||
begin
|
||||
reg old_rd, old_we;
|
||||
reg old_reset;
|
||||
reg state;
|
||||
|
||||
old_reset <= reset;
|
||||
if(old_reset && ~reset)
|
||||
begin
|
||||
busy <= 0;
|
||||
state <= 0;
|
||||
cached <= 0;
|
||||
end
|
||||
|
||||
if(!DDRAM_BUSY)
|
||||
begin
|
||||
ram_write <= 0;
|
||||
ram_read <= 0;
|
||||
if(state)
|
||||
begin
|
||||
if(DDRAM_DOUT_READY)
|
||||
begin
|
||||
ram_q <= DDRAM_DOUT[{ram_address[2:0], 3'b000} +:8];
|
||||
ram_cache <= DDRAM_DOUT;
|
||||
cached <= 8'hFF;
|
||||
state <= 0;
|
||||
busy <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
old_rd <= rd;
|
||||
old_we <= we;
|
||||
busy <= 0;
|
||||
|
||||
if(~old_we && we)
|
||||
begin
|
||||
ram_cache[{addr[2:0], 3'b000} +:8] <= din;
|
||||
ram_address <= addr;
|
||||
busy <= 1;
|
||||
ram_write <= 1;
|
||||
cached <= ((ram_address[27:3] == addr[27:3]) ? cached : 8'h00) | (8'd1<<addr[2:0]);
|
||||
end
|
||||
|
||||
if(~old_rd && rd)
|
||||
begin
|
||||
busy <= 1;
|
||||
if((ram_address[27:3] == addr[27:3]) && (cached & (8'd1<<addr[2:0])))
|
||||
begin
|
||||
ram_q <= ram_cache[{addr[2:0], 3'b000} +:8];
|
||||
end
|
||||
else
|
||||
begin
|
||||
ram_address <= addr;
|
||||
ram_read <= 1;
|
||||
state <= 1;
|
||||
cached <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -5,19 +5,8 @@ module hdmi_config
|
||||
input iCLK,
|
||||
input iRST_N,
|
||||
|
||||
// 0 - 480i
|
||||
// 1 - 480p
|
||||
// 2 - 576i
|
||||
// 3 - 576p
|
||||
// 4 - 720p
|
||||
// 5-7 - reserved
|
||||
input [2:0] iRES,
|
||||
|
||||
// 0 - 4:3
|
||||
// 1 - 16:9
|
||||
input iAR,
|
||||
|
||||
input audio_48k,
|
||||
input dvi_mode,
|
||||
input audio_96k,
|
||||
|
||||
// I2C Side
|
||||
output I2C_SCL,
|
||||
@ -31,7 +20,7 @@ wire mI2C_ACK;
|
||||
reg [15:0] LUT_DATA;
|
||||
reg [7:0] LUT_INDEX = 0;
|
||||
|
||||
I2C_Controller #(50_000_000, 400_000) i2c_av
|
||||
i2c #(50_000_000, 20_000) i2c_av
|
||||
(
|
||||
.CLK(iCLK),
|
||||
|
||||
@ -72,32 +61,20 @@ always@(posedge iCLK or negedge iRST_N) begin
|
||||
end
|
||||
end
|
||||
|
||||
wire [15:0] res480i[6] = '{'h35_1D, 'h36_92, 'h37_05, 'h38_A0, 'h39_0F, 'h3A_00};
|
||||
wire [15:0] res480p[6] = '{'h35_1F, 'h36_E8, 'h37_05, 'h38_A0, 'h39_1E, 'h3A_00};
|
||||
wire [15:0] res576i[6] = '{'h35_20, 'h36_D6, 'h37_05, 'h38_A0, 'h39_12, 'h3A_00};
|
||||
wire [15:0] res576p[6] = '{'h35_20, 'h36_EC, 'h37_05, 'h38_A0, 'h39_24, 'h3A_00};
|
||||
wire [15:0] res720p[6] = '{'h35_40, 'h36_D9, 'h37_0A, 'h38_00, 'h39_2D, 'h3A_00};
|
||||
|
||||
reg [15:0] resVar[6];
|
||||
always_comb begin
|
||||
case(iRES)
|
||||
0: resVar <= res480i;
|
||||
1: resVar <= res480p;
|
||||
2: resVar <= res576i;
|
||||
3: resVar <= res576p;
|
||||
4: resVar <= res720p;
|
||||
default: resVar <= res720p;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
///////////////////// Config Data LUT //////////////////////////
|
||||
///////////////////// Config Data LUT //////////////////////////
|
||||
|
||||
wire [15:0] init_data[58] =
|
||||
'{
|
||||
16'h4110, // Power Down control
|
||||
16'h9803, // ADI required Write.
|
||||
|
||||
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
|
||||
// 00 = HPD is from both HPD pin or CDC HPD
|
||||
// 01 = HPD is from CDC HPD
|
||||
// 10 = HPD is from HPD pin
|
||||
// 11 = HPD is always high
|
||||
|
||||
16'h4110, // Power Down control
|
||||
16'h9A70, // ADI required Write.
|
||||
16'h9C30, // ADI required Write.
|
||||
{8'h9D, 8'b0110_0001}, // [7:4] must be b0110!.
|
||||
@ -108,13 +85,13 @@ wire [15:0] init_data[58] =
|
||||
16'hE0D0, // ADI required Write.
|
||||
|
||||
|
||||
resVar[0],
|
||||
resVar[1],
|
||||
resVar[2],
|
||||
resVar[3],
|
||||
resVar[4],
|
||||
resVar[5],
|
||||
|
||||
16'h35_40,
|
||||
16'h36_D9,
|
||||
16'h37_0A,
|
||||
16'h38_00,
|
||||
16'h39_2D,
|
||||
16'h3A_00,
|
||||
|
||||
{8'h16, 8'b0011_1000}, // Output Format 444 [7]=0.
|
||||
// [6] must be 0!
|
||||
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
|
||||
@ -122,39 +99,15 @@ wire [15:0] init_data[58] =
|
||||
// DDR Input Edge falling [1]=0 (not using DDR atm).
|
||||
// Output Colour Space RGB [0]=0.
|
||||
|
||||
// {8'h16, 8'b1011_0101}, // Output Format 422 [7]=1.
|
||||
// [6] must be 0!
|
||||
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
|
||||
// Input Style [3:2] b01 = Style 2.
|
||||
// DDR Input Edge falling [1]=0 (not using DDR atm).
|
||||
// Output Colour Space YPrPb [0]=1.
|
||||
|
||||
// {8'h17, 8'b0110_0000}, // Aspect ratio 4:3 [1]=0. DE Generation DISabled [0]=0.
|
||||
// Vsync polarity HIGH [6]=0, LOW [6]=1.
|
||||
// Hsync polarity HIGH [5]=0, LOW [5]=1.
|
||||
|
||||
// {8'h17, 8'b0110_0001}, // Aspect ratio 4:3 [1]=0. DE Generation ENabled [0]=1.
|
||||
|
||||
// {8'h17, 8'b0110_0011}, // Aspect ratio 16:9 [1]=1. DE Generation ENabled [0]=1.
|
||||
|
||||
{8'h17, 6'b011000, iAR, 1'b0}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
|
||||
{8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
|
||||
|
||||
{8'h18, 8'b0100_0110}, // CSC disabled [7]=0.
|
||||
// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
|
||||
// CSC Equation 3 [4:0] b00110.
|
||||
|
||||
|
||||
// {8'h3B, 8'b0000_1010}, // Pixel repetition [6:5] b00 AUTO. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
|
||||
|
||||
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
|
||||
|
||||
// {8'h3B, 8'b0110_1010}, // Pixel repetition [6:5] b11 MANUAL. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
|
||||
|
||||
// {8'h3C, 8'b0000_0110}, // VIC#6 480i-60, 2x clk, 4:3.
|
||||
// {8'h3C, 8'b0000_0001}, // VIC#1 VGA (640x480), 2x clk, 4:3.
|
||||
|
||||
// {8'h3C, 8'b0000_0010}, // VIC#2 480p (720x480), 2x clk, 4:3.
|
||||
|
||||
16'h4000, // General Control Packet Enable
|
||||
|
||||
{8'h48, 8'b0000_1000}, // [6]=0 Normal bus order!
|
||||
@ -165,24 +118,20 @@ wire [15:0] init_data[58] =
|
||||
16'h4C00, // ADI required Write.
|
||||
|
||||
{8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
|
||||
// {8'h55, 8'b0101_0000}, // [7] must be 0!. Set YCbCr 444 in AVinfo Frame [6:5], Set active format [4].
|
||||
// {8'h55, 8'b0011_0001}, // [7] must be 0!. Set YCbCr 422 in AVinfo Frame [6:5].
|
||||
// AVI InfoFrame Valid [4].
|
||||
// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
|
||||
// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
|
||||
|
||||
// {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
|
||||
|
||||
16'h7301,
|
||||
|
||||
16'h9400, // HPD Interrupt disabled.
|
||||
{8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
|
||||
|
||||
16'h9902, // ADI required Write.
|
||||
16'h9B18, // ADI required Write.
|
||||
|
||||
16'h9F00, // ADI required Write.
|
||||
|
||||
{8'hA1, 8'b0100_0000}, // [6]=1 Monitor Sense Power Down DISabled.
|
||||
{8'hA1, 8'b0000_0000}, // [6]=1 Monitor Sense Power Down DISabled.
|
||||
|
||||
16'hA408, // ADI required Write.
|
||||
16'hA504, // ADI required Write.
|
||||
@ -193,7 +142,7 @@ wire [15:0] init_data[58] =
|
||||
16'hAA00, // ADI required Write.
|
||||
16'hAB40, // ADI required Write.
|
||||
|
||||
{8'hAF, 8'b0001_0110}, // [7]=0 HDCP Disabled.
|
||||
{8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
|
||||
// [6:5] must be b00!
|
||||
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
|
||||
// [3:2] must be b01!
|
||||
@ -214,12 +163,6 @@ wire [15:0] init_data[58] =
|
||||
|
||||
16'hBB00, // ADI required Write.
|
||||
|
||||
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
|
||||
// 00 = HPD is from both HPD pin or CDC HPD
|
||||
// 01 = HPD is from CDC HPD
|
||||
// 10 = HPD is from HPD pin
|
||||
// 11 = HPD is always high
|
||||
|
||||
16'hDE9C, // ADI required Write.
|
||||
16'hE460, // ADI required Write.
|
||||
16'hFA7D, // Nbr of times to search for good phase
|
||||
@ -239,18 +182,12 @@ wire [15:0] init_data[58] =
|
||||
|
||||
{8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified.
|
||||
{8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits.
|
||||
{8'h15, ~audio_48k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
|
||||
{8'h15, audio_96k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
|
||||
// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
|
||||
|
||||
// {8'h15, 8'b0010_0001}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
|
||||
// Input ID [3:0] b0001 (1) = 16, 20, 24 bit YCbCr 4:2:2 with Separate Syncs.
|
||||
|
||||
// {8'h15, 8'b0010_0011}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
|
||||
// Input ID [3:0] b0011 (3) = 16, 20, 24 bit YCbCr 4:2:2 (2x Pixel Clock, with Separate Syncs).
|
||||
|
||||
// Audio Clock Config
|
||||
16'h0100, //
|
||||
audio_48k ? 16'h0218 : 16'h0230, // Set N Value 12288/6144
|
||||
audio_96k ? 16'h0230 : 16'h0218, // Set N Value 12288/6144
|
||||
16'h0300, //
|
||||
|
||||
16'h0701, //
|
||||
|
||||
395
sys/hdmi_lite.sv
Normal file
395
sys/hdmi_lite.sv
Normal file
@ -0,0 +1,395 @@
|
||||
//============================================================================
|
||||
//
|
||||
// HDMI Lite output module
|
||||
// Copyright (C) 2017 Sorgelig
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
|
||||
module hdmi_lite
|
||||
(
|
||||
input reset,
|
||||
|
||||
input clk_video,
|
||||
input ce_pixel,
|
||||
input video_vs,
|
||||
input video_de,
|
||||
input [23:0] video_d,
|
||||
|
||||
input clk_hdmi,
|
||||
input hdmi_hde,
|
||||
input hdmi_vde,
|
||||
output reg hdmi_de,
|
||||
output [23:0] hdmi_d,
|
||||
|
||||
input [11:0] screen_w,
|
||||
input [11:0] screen_h,
|
||||
input quadbuf,
|
||||
|
||||
// 0-3 => scale 1-4
|
||||
input [1:0] scale_x,
|
||||
input [1:0] scale_y,
|
||||
input scale_auto,
|
||||
|
||||
input clk_vbuf,
|
||||
output [27:0] vbuf_address,
|
||||
input [127:0] vbuf_readdata,
|
||||
output [127:0] vbuf_writedata,
|
||||
output [7:0] vbuf_burstcount,
|
||||
output [15:0] vbuf_byteenable,
|
||||
input vbuf_waitrequest,
|
||||
input vbuf_readdatavalid,
|
||||
output reg vbuf_read,
|
||||
output reg vbuf_write
|
||||
);
|
||||
|
||||
localparam [7:0] burstsz = 64;
|
||||
|
||||
reg [1:0] nbuf = 0;
|
||||
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
|
||||
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
|
||||
|
||||
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
|
||||
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
|
||||
|
||||
wire [95:0] hf_out;
|
||||
wire [7:0] hf_usedw;
|
||||
reg hf_reset = 0;
|
||||
|
||||
vbuf_fifo out_fifo
|
||||
(
|
||||
.aclr(hf_reset),
|
||||
|
||||
.wrclk(clk_vbuf),
|
||||
.wrreq(vbuf_readdatavalid),
|
||||
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
|
||||
.wrusedw(hf_usedw),
|
||||
|
||||
.rdclk(~clk_hdmi),
|
||||
.rdreq(hf_rdreq),
|
||||
.q(hf_out)
|
||||
);
|
||||
|
||||
reg [11:0] rd_stride;
|
||||
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
|
||||
|
||||
reg [27:0] vbuf_raddress;
|
||||
reg [7:0] vbuf_rburstcount;
|
||||
always @(posedge clk_vbuf) begin
|
||||
reg [18:0] rdcnt;
|
||||
reg [7:0] bcnt;
|
||||
reg vde1, vde2;
|
||||
reg [1:0] mcnt;
|
||||
reg [1:0] my;
|
||||
reg [18:0] fsz;
|
||||
reg [11:0] strd;
|
||||
|
||||
vde1 <= hdmi_vde;
|
||||
vde2 <= vde1;
|
||||
|
||||
if(vbuf_readdatavalid) begin
|
||||
rdcnt <= rdcnt + 1'd1;
|
||||
if(bcnt) bcnt <= bcnt - 1'd1;
|
||||
vbuf_raddress <= vbuf_raddress + 1'd1;
|
||||
end
|
||||
|
||||
if(!bcnt && reading) reading <= 0;
|
||||
|
||||
vbuf_read <= 0;
|
||||
if(~vbuf_waitrequest) begin
|
||||
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
|
||||
vbuf_read <= 1;
|
||||
reading <= 1;
|
||||
bcnt <= rd_burst;
|
||||
vbuf_rburstcount <= rd_burst;
|
||||
rd_stride <= rd_stride - rd_burst;
|
||||
if(!(rd_stride - rd_burst)) rd_stride <= strd;
|
||||
|
||||
if(!rdcnt) begin
|
||||
vbuf_raddress <= read_buf;
|
||||
mcnt <= my;
|
||||
end
|
||||
else if (rd_stride == strd) begin
|
||||
mcnt <= mcnt - 1'd1;
|
||||
if(!mcnt) mcnt <= my;
|
||||
else vbuf_raddress <= vbuf_raddress - strd;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
hf_reset <= 0;
|
||||
if(vde2 & ~vde1) begin
|
||||
hf_reset <= 1;
|
||||
rdcnt <= 0;
|
||||
bcnt <= 0;
|
||||
rd_stride <= stride;
|
||||
strd <= stride;
|
||||
fsz <= framesz;
|
||||
my <= mult_y;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [11:0] off_x, off_y;
|
||||
reg [11:0] x, y;
|
||||
reg [11:0] vh_height;
|
||||
reg [11:0] vh_width;
|
||||
reg [1:0] pcnt;
|
||||
reg [1:0] hload;
|
||||
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
|
||||
wire de_in = hdmi_hde & hdmi_vde;
|
||||
|
||||
always @(posedge clk_hdmi) begin
|
||||
reg [71:0] px_out;
|
||||
reg [1:0] mx;
|
||||
reg vde;
|
||||
|
||||
vde <= hdmi_vde;
|
||||
|
||||
if(vde & ~hdmi_vde) begin
|
||||
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
|
||||
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
|
||||
vh_height <= v_height;
|
||||
vh_width <= v_width;
|
||||
mx <= mult_x;
|
||||
end
|
||||
|
||||
pcnt <= pcnt + 1'd1;
|
||||
if(pcnt == mx) begin
|
||||
pcnt <= 0;
|
||||
hload <= hload + 1'd1;
|
||||
end
|
||||
|
||||
if(~de_in || x<off_x || y<off_y) begin
|
||||
hload <= 0;
|
||||
pcnt <= 0;
|
||||
end
|
||||
|
||||
hdmi_de <= de_in;
|
||||
|
||||
x <= x + 1'd1;
|
||||
if(~hdmi_de & de_in) x <= 0;
|
||||
if(hdmi_de & ~de_in) y <= y + 1'd1;
|
||||
if(~hdmi_vde) y <= 0;
|
||||
|
||||
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
|
||||
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
|
||||
end
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
reg reading = 0;
|
||||
reg writing = 0;
|
||||
|
||||
reg op_split = 0;
|
||||
always @(posedge clk_vbuf) op_split <= ~op_split;
|
||||
|
||||
wire allow_rd = ~reading & ~writing & op_split & ~reset;
|
||||
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
reg vf_rdreq = 0;
|
||||
wire [95:0] vf_out;
|
||||
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
|
||||
|
||||
vbuf_fifo in_fifo
|
||||
(
|
||||
.aclr(video_vs),
|
||||
|
||||
.rdclk(clk_vbuf),
|
||||
.rdreq(vf_rdreq & ~vbuf_waitrequest),
|
||||
.q(vf_out),
|
||||
|
||||
.wrclk(clk_video),
|
||||
.wrreq(infifo_wr),
|
||||
.data({video_de ? video_d : 24'd0, pix_acc})
|
||||
);
|
||||
|
||||
assign vbuf_byteenable = '1;
|
||||
|
||||
reg [35:0] addrque[3:0] = '{0,0,0,0};
|
||||
|
||||
reg [7:0] flush_size;
|
||||
reg [27:0] flush_addr;
|
||||
reg flush_req = 0;
|
||||
reg flush_ack = 0;
|
||||
|
||||
reg [27:0] vbuf_waddress;
|
||||
reg [7:0] vbuf_wburstcount;
|
||||
|
||||
always @(posedge clk_vbuf) begin
|
||||
reg [7:0] ibcnt = 0;
|
||||
reg reqd = 0;
|
||||
|
||||
reqd <= flush_req;
|
||||
|
||||
if(~vbuf_waitrequest) begin
|
||||
vbuf_write <= vf_rdreq;
|
||||
if(~vf_rdreq && writing) writing <= 0;
|
||||
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
|
||||
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
|
||||
ibcnt <= addrque[0][7:0];
|
||||
addrque[0] <= addrque[1];
|
||||
addrque[1] <= addrque[2];
|
||||
addrque[2] <= addrque[3];
|
||||
addrque[3] <= 0;
|
||||
vf_rdreq <= 1;
|
||||
writing <= 1;
|
||||
end
|
||||
else if(flush_ack != reqd) begin
|
||||
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
|
||||
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
|
||||
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
|
||||
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
|
||||
flush_ack <= reqd;
|
||||
end
|
||||
|
||||
if(vf_rdreq) begin
|
||||
if(ibcnt == 1) vf_rdreq <= 0;
|
||||
ibcnt <= ibcnt - 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [11:0] stride;
|
||||
reg [18:0] framesz;
|
||||
reg [11:0] v_height;
|
||||
reg [11:0] v_width;
|
||||
reg [1:0] mult_x;
|
||||
reg [1:0] mult_y;
|
||||
|
||||
reg [71:0] pix_acc;
|
||||
wire pix_wr = ce_pixel && video_de;
|
||||
|
||||
reg [27:0] cur_addr;
|
||||
reg [11:0] video_x;
|
||||
reg [11:0] video_y;
|
||||
|
||||
wire infifo_tail = ~video_de && video_x[1:0];
|
||||
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
|
||||
|
||||
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
|
||||
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
|
||||
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
|
||||
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
|
||||
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
|
||||
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
|
||||
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
|
||||
wire [23:0] t_fsz = l1_stride * t_height;
|
||||
|
||||
reg [11:0] l1_width;
|
||||
reg [11:0] l1_stride;
|
||||
always @(posedge clk_video) begin
|
||||
reg [7:0] loaded = 0;
|
||||
reg [11:0] strd = 0;
|
||||
reg old_de = 0;
|
||||
reg old_vs = 0;
|
||||
|
||||
old_vs <= video_vs;
|
||||
if(~old_vs & video_vs) begin
|
||||
cur_addr<= write_buf;
|
||||
video_x <= 0;
|
||||
video_y <= 0;
|
||||
loaded <= 0;
|
||||
strd <= 0;
|
||||
nbuf <= nbuf + 1'd1;
|
||||
|
||||
stride <= l1_stride;
|
||||
framesz <= t_fsz[18:0];
|
||||
v_height<= t_height;
|
||||
v_width <= t_width;
|
||||
mult_x <= tmf_x;
|
||||
mult_y <= tmf_y;
|
||||
end
|
||||
|
||||
if(pix_wr) begin
|
||||
case(video_x[1:0])
|
||||
0: pix_acc <= video_d; // zeroes upper bits too
|
||||
1: pix_acc[47:24] <= video_d;
|
||||
2: pix_acc[71:48] <= video_d;
|
||||
3: loaded <= loaded + 1'd1;
|
||||
endcase
|
||||
if(video_x<screen_w) video_x <= video_x + 1'd1;
|
||||
end
|
||||
|
||||
old_de <= video_de;
|
||||
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
|
||||
if(loaded + infifo_tail) begin
|
||||
flush_size <= loaded + infifo_tail;
|
||||
flush_addr <= cur_addr;
|
||||
flush_req <= ~flush_req;
|
||||
loaded <= 0;
|
||||
strd <= strd + loaded;
|
||||
end
|
||||
|
||||
cur_addr <= cur_addr + loaded + infifo_tail;
|
||||
if(~video_de) begin
|
||||
if(video_y<screen_h) video_y <= video_y + 1'd1;
|
||||
video_x <= 0;
|
||||
strd <= 0;
|
||||
|
||||
// measure width by first line (same as VIP)
|
||||
if(!video_y) begin
|
||||
l1_width <= video_x;
|
||||
l1_stride <= strd + loaded + infifo_tail;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module vbuf_fifo
|
||||
(
|
||||
input aclr,
|
||||
|
||||
input rdclk,
|
||||
input rdreq,
|
||||
output [95:0] q,
|
||||
|
||||
input wrclk,
|
||||
input wrreq,
|
||||
input [95:0] data,
|
||||
output [7:0] wrusedw
|
||||
);
|
||||
|
||||
dcfifo dcfifo_component
|
||||
(
|
||||
.aclr (aclr),
|
||||
.data (data),
|
||||
.rdclk (rdclk),
|
||||
.rdreq (rdreq),
|
||||
.wrclk (wrclk),
|
||||
.wrreq (wrreq),
|
||||
.q (q),
|
||||
.wrusedw (wrusedw),
|
||||
.eccstatus (),
|
||||
.rdempty (),
|
||||
.rdfull (),
|
||||
.rdusedw (),
|
||||
.wrempty (),
|
||||
.wrfull ()
|
||||
);
|
||||
|
||||
defparam
|
||||
dcfifo_component.intended_device_family = "Cyclone V",
|
||||
dcfifo_component.lpm_numwords = 256,
|
||||
dcfifo_component.lpm_showahead = "OFF",
|
||||
dcfifo_component.lpm_type = "dcfifo",
|
||||
dcfifo_component.lpm_width = 96,
|
||||
dcfifo_component.lpm_widthu = 8,
|
||||
dcfifo_component.overflow_checking = "ON",
|
||||
dcfifo_component.rdsync_delaypipe = 5,
|
||||
dcfifo_component.read_aclr_synch = "OFF",
|
||||
dcfifo_component.underflow_checking = "ON",
|
||||
dcfifo_component.use_eab = "ON",
|
||||
dcfifo_component.write_aclr_synch = "OFF",
|
||||
dcfifo_component.wrsync_delaypipe = 5;
|
||||
|
||||
endmodule
|
||||
46
sys/hps_io.v
46
sys/hps_io.v
@ -33,7 +33,7 @@
|
||||
module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
|
||||
(
|
||||
input clk_sys,
|
||||
inout [43:0] HPS_BUS,
|
||||
inout [44:0] HPS_BUS,
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
@ -99,7 +99,11 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
|
||||
input ps2_mouse_data_in,
|
||||
|
||||
// ps2 alternative interface.
|
||||
output reg [65:0] ps2_key = 0, // up to 8 bytes per key (pause)
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0
|
||||
);
|
||||
|
||||
@ -151,6 +155,7 @@ wire ce_pix = HPS_BUS[41];
|
||||
wire de = HPS_BUS[40];
|
||||
wire hs = HPS_BUS[39];
|
||||
wire vs = HPS_BUS[38];
|
||||
wire vs_hdmi = HPS_BUS[44];
|
||||
|
||||
reg [31:0] vid_hcnt = 0;
|
||||
reg [31:0] vid_vcnt = 0;
|
||||
@ -222,8 +227,29 @@ always @(posedge clk_100) begin
|
||||
if(old_de2 & ~old_de) calch <= 0;
|
||||
end
|
||||
|
||||
reg [31:0] vid_vtime_hdmi;
|
||||
always @(posedge clk_100) begin
|
||||
integer vtime;
|
||||
reg old_vs, old_vs2;
|
||||
|
||||
old_vs <= vs_hdmi;
|
||||
old_vs2 <= old_vs;
|
||||
|
||||
vtime <= vtime + 1'd1;
|
||||
|
||||
if(~old_vs2 & old_vs) begin
|
||||
vid_vtime_hdmi <= vtime;
|
||||
vtime <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
always@(posedge clk_sys) begin
|
||||
reg [15:0] cmd;
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
@ -236,11 +262,15 @@ always@(posedge clk_sys) begin
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
|
||||
ps2_key[65] <= kbd_txempty;
|
||||
|
||||
if(~io_enable) begin
|
||||
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5 && !ps2skip) ps2_key[64] <= ~ps2_key[64];
|
||||
if(cmd == 5 && !ps2skip) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
if(cmd == 'h22) RTC[64] <= ~RTC[64];
|
||||
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
|
||||
cmd <= 0;
|
||||
@ -266,7 +296,7 @@ always@(posedge clk_sys) begin
|
||||
|
||||
sd_buff_addr <= 0;
|
||||
img_mounted <= 0;
|
||||
if(io_din == 5) ps2_key[63:0] <= 0;
|
||||
if(io_din == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
@ -292,7 +322,7 @@ always@(posedge clk_sys) begin
|
||||
// store incoming ps2 keyboard bytes
|
||||
'h05: begin
|
||||
if(&io_din[15:8]) ps2skip <= 1;
|
||||
if(~&io_din[15:8] & ~ps2skip) ps2_key[63:0] <= {ps2_key[55:0], io_din[7:0]};
|
||||
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
|
||||
kbd_data <= io_din[7:0];
|
||||
kbd_we <= 1;
|
||||
end
|
||||
@ -385,6 +415,8 @@ always@(posedge clk_sys) begin
|
||||
9: io_dout <= vid_vtime[31:16];
|
||||
10: io_dout <= vid_pix[15:0];
|
||||
11: io_dout <= vid_pix[31:16];
|
||||
12: io_dout <= vid_vtime_hdmi[15:0];
|
||||
13: io_dout <= vid_vtime_hdmi[31:16];
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -412,7 +444,6 @@ reg [7:0] kbd_data;
|
||||
reg kbd_we;
|
||||
wire [8:0] kbd_data_host;
|
||||
reg kbd_rd;
|
||||
wire kbd_txempty;
|
||||
|
||||
ps2_device keyboard
|
||||
(
|
||||
@ -424,7 +455,6 @@ ps2_device keyboard
|
||||
.ps2_clk(clk_ps2),
|
||||
.ps2_clk_out(ps2_kbd_clk_out),
|
||||
.ps2_dat_out(ps2_kbd_data_out),
|
||||
.tx_empty(kbd_txempty),
|
||||
|
||||
.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
|
||||
.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
|
||||
|
||||
61
sys/i2s.v
61
sys/i2s.v
@ -22,16 +22,39 @@ localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
|
||||
localparam ERROR_BASE = 10000;
|
||||
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
|
||||
|
||||
reg lpf_ce;
|
||||
wire [AUDIO_DW-1:0] al, ar;
|
||||
|
||||
lpf_i2s lpf_l
|
||||
(
|
||||
.CLK(clk_sys),
|
||||
.CE(lpf_ce),
|
||||
.IDATA(left_chan),
|
||||
.ODATA(al)
|
||||
);
|
||||
|
||||
lpf_i2s lpf_r
|
||||
(
|
||||
.CLK(clk_sys),
|
||||
.CE(lpf_ce),
|
||||
|
||||
.IDATA(right_chan),
|
||||
.ODATA(ar)
|
||||
);
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg [31:0] count_q;
|
||||
reg [31:0] error_q;
|
||||
reg [7:0] bit_cnt;
|
||||
reg [31:0] count_q;
|
||||
reg [31:0] error_q;
|
||||
reg [7:0] bit_cnt;
|
||||
reg skip = 0;
|
||||
|
||||
reg [AUDIO_DW-1:0] left;
|
||||
reg [AUDIO_DW-1:0] right;
|
||||
|
||||
reg msclk;
|
||||
reg ce;
|
||||
|
||||
lpf_ce <= 0;
|
||||
|
||||
if (reset) begin
|
||||
count_q <= 0;
|
||||
@ -64,12 +87,14 @@ always @(posedge clk_sys) begin
|
||||
if(~half_rate || ce) begin
|
||||
msclk <= ~msclk;
|
||||
if(msclk) begin
|
||||
skip <= ~skip;
|
||||
if(skip) lpf_ce <= 1;
|
||||
if(bit_cnt >= AUDIO_DW) begin
|
||||
bit_cnt <= 1;
|
||||
lrclk <= ~lrclk;
|
||||
if(lrclk) begin
|
||||
left <= left_chan;
|
||||
right <= right_chan;
|
||||
left <= al;
|
||||
right <= ar;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
@ -83,3 +108,29 @@ always @(posedge clk_sys) begin
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module lpf_i2s
|
||||
(
|
||||
input CLK,
|
||||
input CE,
|
||||
input [15:0] IDATA,
|
||||
output reg [15:0] ODATA
|
||||