2016-01-24 19:26:06 +00:00
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
117 "number of signals after reading design file"
|
2016-08-18 22:22:24 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 340 7 3 2 4 6 79 -1 4 0 21
|
|
|
|
|
68 A_0_ 5 346 6 2 2 6 68 -1 3 0 21
|
|
|
|
|
70 RW 5 345 6 2 5 7 70 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 343 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 342 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 344 3 0 34 -1 3 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 341 3 0 28 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
315 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
316 CLK_000_D_1_ 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
326 SM_AMIGA_6_ 3 -1 1 5 1 2 5 6 7 -1 -1 3 0 21
|
|
|
|
|
317 CLK_000_D_0_ 3 -1 1 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 0 4 0 1 3 5 -1 -1 7 0 21
|
|
|
|
|
337 SM_AMIGA_i_7_ 3 -1 5 3 0 1 7 -1 -1 13 1 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 6 3 0 2 6 -1 -1 1 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21
|
|
|
|
|
344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
333 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
325 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
310 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
319 inst_CLK_OUT_PRE_25 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
|
|
|
309 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
|
|
|
318 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_2_ 3 -1 4 2 1 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
|
|
|
348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
332 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
|
|
|
343 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
336 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
335 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
329 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
334 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
331 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
|
|
|
330 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
323 CLK_000_D_4_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
|
|
|
322 IPL_D0_2_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
|
|
|
321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
|
|
|
313 CLK_000_D_3_ 3 -1 1 1 7 -1 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 4 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 2 2 6 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
|
|
|
121 "number of signals after reading design file"
|
2016-08-18 22:22:24 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21
|
|
|
|
|
79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 350 6 2 0 1 68 -1 3 0 21
|
|
|
|
|
70 RW 5 349 6 2 5 7 70 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 347 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 346 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 348 3 0 34 -1 3 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 345 3 0 28 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
317 CLK_000_D_0_ 3 -1 4 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
|
|
|
346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
315 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
316 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
330 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 5 4 0 3 5 6 -1 -1 4 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 0 4 0 3 5 6 -1 -1 1 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
|
|
|
|
|
293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
304 CYCLE_DMA_0_ 3 -1 6 3 0 1 6 -1 -1 3 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 3 3 0 3 5 -1 -1 3 0 21
|
|
|
|
|
311 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 4 3 0 2 6 -1 -1 1 0 21
|
|
|
|
|
341 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 4 0 21
|
|
|
|
|
348 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
337 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
309 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
318 inst_CLK_OUT_PRE_50 3 -1 2 2 2 3 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_6_ 3 -1 2 2 0 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
|
|
|
352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
347 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
333 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
|
|
|
350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
331 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
349 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
335 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
|
|
|
334 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
|
|
|
|
319 inst_CLK_OUT_PRE_25 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
327 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
|
|
|
326 CLK_000_D_5_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
|
|
|
325 CLK_000_D_4_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_3_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_2_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
|
|
|
322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
|
|
|
313 CLK_000_D_7_ 3 -1 0 1 7 -1 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 2 0 2 59 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 4 10 -1
|
|
|
|
|
122 "number of signals after reading design file"
|
2016-08-18 22:22:24 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
|
|
|
79 RW_000 5 345 7 3 1 4 6 79 -1 4 0 21
|
|
|
|
|
40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 351 6 2 2 6 68 -1 3 0 21
|
|
|
|
|
70 RW 5 350 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 348 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 347 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 349 3 0 34 -1 3 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 346 3 0 28 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
347 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
315 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
331 SM_AMIGA_6_ 3 -1 0 5 0 2 5 6 7 -1 -1 3 0 21
|
|
|
|
|
317 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
316 CLK_000_D_1_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 2 4 2 3 5 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_3_ 3 -1 3 4 2 3 5 6 -1 -1 4 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
294 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
2016-08-25 20:30:49 +00:00
|
|
|
342 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
|
|
|
|
349 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
338 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
333 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
330 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
310 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
304 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 3 0 21
|
|
|
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
319 inst_CLK_OUT_PRE_25 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
|
|
|
309 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
318 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_7_ 3 -1 3 2 4 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 1 2 0 6 -1 -1 1 0 21
|
|
|
|
|
353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
337 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
|
|
|
348 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
341 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
340 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
339 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
350 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
343 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
|
|
|
335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
|
|
|
328 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
|
|
|
327 CLK_000_D_6_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
|
|
|
326 CLK_000_D_5_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
|
|
|
325 CLK_000_D_4_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
|
|
|
322 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
321 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
320 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
314 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
|
|
|
313 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 1 7 63 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
|
|
|
124 "number of signals after reading design file"
|
2016-08-18 22:22:24 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 3 4 6 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 347 7 2 4 6 79 -1 4 0 21
|
|
|
|
|
68 A_0_ 5 353 6 2 0 5 68 -1 3 0 21
|
|
|
|
|
70 RW 5 352 6 2 0 7 70 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 20
|
|
|
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 350 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 349 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 351 3 0 34 -1 3 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 348 3 0 28 -1 2 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
315 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
317 CLK_000_D_0_ 3 -1 5 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
316 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
332 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 6 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21
|
|
|
|
|
311 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
|
|
|
297 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
344 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
|
|
|
351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
341 SM_AMIGA_5_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
|
|
|
340 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
334 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
333 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
331 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
310 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 3 2 3 6 -1 -1 3 0 21
|
|
|
|
|
338 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
|
|
|
319 inst_CLK_OUT_PRE_25 3 -1 1 2 0 1 -1 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
313 CLK_000_D_8_ 3 -1 4 2 3 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_7_ 3 -1 5 2 4 7 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
|
|
|
355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
339 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
|
|
|
350 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
335 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
|
|
|
353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
352 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
337 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
336 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21
|
|
|
|
|
330 inst_UDS_000_e 3 -1 3 1 3 -1 -1 1 0 20
|
|
|
|
|
328 CLK_000_D_9_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
|
|
|
327 CLK_000_D_6_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
|
|
|
326 CLK_000_D_5_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
|
|
|
325 CLK_000_D_4_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_2_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
|
|
|
322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
|
|
|
321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
|
|
|
293 un1_as_000 3 -1 7 1 3 -1 -1 1 0 21
|
2016-08-18 22:22:24 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 6 7 63 -1
|
2016-08-18 22:22:24 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 1 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
|
|
|
122 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-24 21:34:13 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
79 RW_000 5 345 7 3 1 4 6 79 -1 4 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
68 A_0_ 5 351 6 2 2 6 68 -1 3 0 21
|
|
|
|
|
70 RW 5 350 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 348 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 347 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 349 3 0 34 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 346 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
347 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
313 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
331 SM_AMIGA_6_ 3 -1 0 5 0 2 5 6 7 -1 -1 3 0 21
|
|
|
|
|
315 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
314 CLK_000_D_1_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 3 4 2 3 5 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 2 4 2 3 5 6 -1 -1 1 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
309 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
342 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
349 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
338 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
333 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
328 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 3 0 21
|
|
|
|
|
330 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
317 inst_CLK_OUT_PRE_25 3 -1 2 2 2 4 -1 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
|
|
|
310 CLK_000_D_7_ 3 -1 3 2 4 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 1 2 0 6 -1 -1 1 0 21
|
|
|
|
|
353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
337 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
|
|
|
348 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
341 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
340 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
339 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
350 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
343 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
|
|
|
335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
|
|
|
326 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
|
|
|
325 CLK_000_D_6_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_5_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_4_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
|
|
|
322 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
|
|
|
321 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
|
|
|
311 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
63 CLK_030 1 -1 -1 2 1 7 63 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
|
|
|
123 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
79 RW_000 5 346 7 3 2 4 6 79 -1 4 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 352 6 2 1 3 68 -1 3 0 21
|
|
|
|
|
70 RW 5 351 6 2 5 7 70 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
8 IPL_030_2_ 5 345 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 354 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 349 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 348 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 350 3 0 34 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 347 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
348 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
315 CLK_000_D_0_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
314 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
332 SM_AMIGA_6_ 3 -1 0 5 0 1 3 5 7 -1 -1 3 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 3 5 0 3 4 5 7 -1 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
309 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 5 3 0 2 6 -1 -1 1 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
343 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21
|
2016-08-18 22:42:01 +00:00
|
|
|
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
350 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
339 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
330 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
329 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
317 inst_CLK_OUT_PRE_25 3 -1 0 2 0 1 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
|
|
|
311 CLK_000_D_9_ 3 -1 7 2 5 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
345 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
338 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
|
|
|
349 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
342 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
341 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
2016-08-25 20:30:49 +00:00
|
|
|
335 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
352 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
340 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
333 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
351 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
337 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
|
|
|
336 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
|
|
|
|
331 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
327 CLK_000_D_10_ 3 -1 5 1 7 -1 -1 1 0 21
|
|
|
|
|
326 CLK_000_D_7_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
325 CLK_000_D_6_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_5_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_4_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
322 CLK_000_D_3_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
|
|
|
321 CLK_000_D_2_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
|
|
|
312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
|
|
|
310 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
59 A_1_ 1 -1 -1 2 2 6 59 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 4 10 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
121 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
70 RW 5 349 6 2 5 7 70 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 350 6 1 0 68 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 347 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 346 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 348 3 0 34 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 345 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
315 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
314 CLK_000_D_1_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 4 1 2 3 5 -1 -1 7 0 21
|
|
|
|
|
330 SM_AMIGA_6_ 3 -1 1 4 0 1 5 7 -1 -1 3 0 21
|
|
|
|
|
341 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
337 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
309 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 7 3 2 3 6 -1 -1 1 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
348 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
328 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21
|
|
|
|
|
311 CLK_000_D_7_ 3 -1 7 2 4 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
|
|
|
352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
347 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
333 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
331 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
|
|
|
349 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
335 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
|
|
|
334 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
|
|
|
|
326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
317 inst_CLK_OUT_PRE_25 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
325 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
322 CLK_000_D_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
|
|
|
321 CLK_000_D_2_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
|
|
|
310 CLK_000_D_6_ 3 -1 3 1 7 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 2 3 6 59 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 4 10 -1
|
|
|
|
|
121 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
|
|
|
|
70 RW 5 349 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 350 6 1 0 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 347 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 346 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 348 3 0 34 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 345 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
315 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
314 CLK_000_D_1_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 4 1 2 3 5 -1 -1 7 0 21
|
|
|
|
|
330 SM_AMIGA_6_ 3 -1 1 4 0 1 5 7 -1 -1 3 0 21
|
|
|
|
|
341 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
337 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
309 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 7 3 2 3 6 -1 -1 1 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
348 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
328 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21
|
|
|
|
|
311 CLK_000_D_7_ 3 -1 7 2 4 7 -1 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
347 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
333 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
331 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
|
|
|
349 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
335 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
|
|
|
334 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
|
|
|
|
326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
317 inst_CLK_OUT_PRE_25 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
325 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
322 CLK_000_D_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
|
|
|
321 CLK_000_D_2_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
|
|
|
310 CLK_000_D_6_ 3 -1 3 1 7 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 2 3 6 59 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 4 10 -1
|
|
|
|
|
119 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 2 4 6 7 41 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21
|
|
|
|
|
70 RW 5 347 6 2 0 7 70 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
68 A_0_ 5 348 6 1 2 68 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 350 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 349 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 345 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 344 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 346 3 0 34 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 343 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
344 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
314 CLK_000_D_1_ 3 -1 3 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
|
|
|
315 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 1 4 0 1 3 5 -1 -1 7 0 21
|
|
|
|
|
328 SM_AMIGA_6_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 7 4 0 1 3 6 -1 -1 1 0 21
|
|
|
|
|
339 SM_AMIGA_i_7_ 3 -1 5 3 0 1 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
309 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
331 RST_DLY_0_ 3 -1 6 2 0 6 -1 -1 4 0 21
|
|
|
|
|
346 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
335 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
330 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
329 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
326 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
325 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
304 CYCLE_DMA_0_ 3 -1 6 2 2 6 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
333 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21
|
|
|
|
|
332 RST_DLY_1_ 3 -1 6 2 0 6 -1 -1 2 1 21
|
|
|
|
|
327 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
310 CLK_000_D_4_ 3 -1 0 2 0 7 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
|
|
|
350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
334 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
|
|
|
345 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
338 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
337 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
336 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
347 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
317 inst_CLK_OUT_PRE_25 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
323 CLK_000_D_6_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
|
|
|
322 CLK_000_D_3_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
|
|
|
321 CLK_000_D_2_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
312 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
|
|
|
311 CLK_000_D_5_ 3 -1 0 1 7 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
59 A_1_ 1 -1 -1 2 0 3 59 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
125 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-24 21:34:13 +00:00
|
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 348 7 3 2 4 6 79 -1 4 0 21
|
|
|
|
|
81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21
|
|
|
|
|
70 RW 5 353 6 2 2 7 70 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
68 A_0_ 5 354 6 1 1 68 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 347 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 356 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 355 1 0 6 -1 10 0 21
|
|
|
|
|
80 DSACK1 5 351 7 0 80 -1 5 0 21
|
|
|
|
|
82 BGACK_030 5 350 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 352 3 0 34 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 349 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
350 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
315 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
314 CLK_000_D_1_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
334 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 0 5 0 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 2 4 0 2 3 6 -1 -1 1 0 21
|
|
|
|
|
345 SM_AMIGA_i_7_ 3 -1 5 3 0 5 7 -1 -1 13 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
309 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
2016-08-24 21:34:13 +00:00
|
|
|
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
352 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
342 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21
|
|
|
|
|
341 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
336 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
|
|
|
332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
331 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
333 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
311 CLK_000_D_11_ 3 -1 7 2 1 7 -1 -1 1 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
308 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
340 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
|
|
|
351 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21
|
|
|
|
|
348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
344 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
343 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
337 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
354 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
353 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
346 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
339 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
|
|
|
338 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
|
|
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
317 inst_CLK_OUT_PRE_25 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
329 CLK_000_D_12_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
|
|
|
328 CLK_000_D_9_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
|
|
|
327 CLK_000_D_8_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
|
|
|
326 CLK_000_D_7_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
|
|
|
325 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
324 CLK_000_D_5_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
|
|
|
323 CLK_000_D_4_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
|
|
|
322 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
|
|
|
321 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
|
|
|
320 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
312 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
|
|
|
310 CLK_000_D_10_ 3 -1 5 1 7 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
59 A_1_ 1 -1 -1 2 3 6 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21
|
|
|
|
|
68 A_0_ 5 341 6 2 3 5 68 -1 3 0 21
|
|
|
|
|
70 RW 5 346 6 2 5 7 70 -1 2 0 21
|
2016-08-24 21:34:13 +00:00
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 345 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 344 7 0 80 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21
|
|
|
|
|
297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 0 2 2 7 -1 -1 13 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
|
|
|
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21
|
|
|
|
|
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
346 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 2 0 21
|
|
|
|
|
336 CIIN_0 3 -1 6 1 4 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 6 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 4 55 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 1 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
2016-08-18 22:42:01 +00:00
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
2016-08-25 20:30:49 +00:00
|
|
|
41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21
|
|
|
|
|
68 A_0_ 5 341 6 2 3 5 68 -1 3 0 21
|
|
|
|
|
70 RW 5 346 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 345 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 344 7 0 80 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
2016-08-25 20:30:49 +00:00
|
|
|
340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21
|
|
|
|
|
297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 0 2 2 7 -1 -1 13 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
|
|
|
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21
|
|
|
|
|
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
346 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 2 0 21
|
|
|
|
|
336 CIIN_0 3 -1 6 1 4 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 6 -1 -1 1 0 21
|
2016-08-18 22:42:01 +00:00
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 4 55 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 1 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
2016-08-24 21:34:13 +00:00
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
2016-08-25 20:30:49 +00:00
|
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
2016-08-18 22:42:01 +00:00
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
2016-09-15 17:20:42 +00:00
|
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
|
|
|
114 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 337 7 2 4 6 79 -1 4 0 21
|
|
|
|
|
70 RW 5 345 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 340 6 1 5 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 339 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 344 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 343 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 338 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21
|
|
|
|
|
334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
|
|
|
327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21
|
|
|
|
|
344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
|
|
|
297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
|
|
|
329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
|
|
|
328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21
|
|
|
|
|
322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
|
|
|
342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
|
|
|
337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 6 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21
|
|
|
|
|
68 A_0_ 5 341 6 2 3 5 68 -1 3 0 21
|
|
|
|
|
70 RW 5 346 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 345 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 344 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21
|
|
|
|
|
297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 0 2 2 7 -1 -1 13 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
|
|
|
345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
316 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21
|
|
|
|
|
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
346 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 2 0 21
|
|
|
|
|
336 CIIN_0 3 -1 6 1 4 -1 -1 1 0 21
|
|
|
|
|
319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 6 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 4 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 1 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
|
|
|
114 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 337 7 2 4 6 79 -1 4 0 21
|
|
|
|
|
70 RW 5 345 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 340 6 1 5 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 339 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 344 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 343 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 338 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21
|
|
|
|
|
334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
|
|
|
327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21
|
|
|
|
|
344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
|
|
|
297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
|
|
|
329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
|
|
|
328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21
|
|
|
|
|
322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
|
|
|
342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
|
|
|
337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 6 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
|
|
|
111 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 334 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
|
|
|
70 RW 5 342 6 2 0 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 336 6 1 1 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 333 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 339 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 338 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 337 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 341 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 340 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 335 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21
|
|
|
|
|
337 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 3 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
320 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21
|
|
|
|
|
311 CLK_000_D_1_ 3 -1 4 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
331 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
330 SM_AMIGA_2_ 3 -1 5 2 5 7 -1 -1 4 0 21
|
|
|
|
|
341 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
328 SM_AMIGA_5_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
322 SM_AMIGA_1_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
|
|
|
316 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21
|
|
|
|
|
339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
338 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
333 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
327 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
334 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
329 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
324 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
336 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
|
|
|
342 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
335 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
332 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
326 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
|
|
|
|
325 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21
|
|
|
|
|
315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
309 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 0 1 63 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
|
|
|
114 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 337 7 2 4 6 79 -1 4 0 21
|
|
|
|
|
70 RW 5 345 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 340 6 1 5 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 339 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 344 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 343 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 338 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21
|
|
|
|
|
334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
|
|
|
327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21
|
|
|
|
|
344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
|
|
|
297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
|
|
|
329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
|
|
|
328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21
|
|
|
|
|
322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
|
|
|
342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
|
|
|
337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 6 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
|
|
|
111 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 334 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
|
|
|
70 RW 5 342 6 2 0 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 336 6 1 1 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 333 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 339 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 338 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 337 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 341 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 340 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 335 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21
|
|
|
|
|
337 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 3 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
320 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21
|
|
|
|
|
311 CLK_000_D_1_ 3 -1 4 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
331 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
330 SM_AMIGA_2_ 3 -1 5 2 5 7 -1 -1 4 0 21
|
|
|
|
|
341 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
328 SM_AMIGA_5_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
322 SM_AMIGA_1_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
|
|
|
318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
|
|
|
316 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21
|
|
|
|
|
339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
338 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
333 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
327 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
334 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
329 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
324 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
336 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
|
|
|
342 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
335 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
332 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
326 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
|
|
|
|
325 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21
|
|
|
|
|
315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
309 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 0 1 63 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
|
|
|
114 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 337 7 2 4 6 79 -1 4 0 21
|
|
|
|
|
70 RW 5 345 6 2 5 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 340 6 1 5 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 339 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 344 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 343 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 338 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21
|
|
|
|
|
334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21
|
|
|
|
|
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21
|
|
|
|
|
323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
|
|
|
303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
|
|
|
327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21
|
|
|
|
|
306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21
|
|
|
|
|
344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
|
|
|
297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
|
|
|
329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
|
|
|
328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21
|
|
|
|
|
322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21
|
|
|
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
|
|
|
342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
|
|
|
337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21
|
|
|
|
|
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
|
|
|
293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 6 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
|
|
|
114 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
|
|
|
41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21
|
|
|
|
|
79 RW_000 5 337 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 3 0 2 6 30 -1 1 0 21
|
|
|
|
|
70 RW 5 345 6 2 1 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 340 6 1 0 68 -1 3 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 339 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 344 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 341 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 338 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
309 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 5 1 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
323 SM_AMIGA_6_ 3 -1 5 4 0 1 5 7 -1 -1 3 0 21
|
|
|
|
|
334 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 13 1 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21
|
|
|
|
|
296 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
327 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21
|
|
|
|
|
344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
331 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
324 SM_AMIGA_4_ 3 -1 5 2 1 5 -1 -1 3 0 21
|
|
|
|
|
321 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
|
|
|
320 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
|
|
|
293 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
329 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21
|
|
|
|
|
328 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 2 1 21
|
|
|
|
|
322 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
|
|
|
319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21
|
|
|
|
|
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
318 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 0 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 5 0 1 3 4 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21
|
|
|
|
|
68 A_0_ 5 341 6 2 2 6 68 -1 3 0 21
|
|
|
|
|
70 RW 5 346 6 2 2 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 345 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 344 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
340 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 0 5 0 2 5 6 7 -1 -1 3 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
309 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 4 3 0 2 6 -1 -1 1 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 3 2 1 3 -1 -1 4 0 21
|
|
|
|
|
345 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 3 2 1 3 -1 -1 3 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_25 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
|
|
|
319 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
313 inst_CLK_OUT_PRE_50 3 -1 6 2 2 6 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
|
|
|
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
|
|
|
346 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 4 66 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 1 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
81 AS_030 5 -1 7 3 4 5 7 81 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 3 1 5 7 40 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 344 6 2 1 2 68 -1 3 0 21
|
|
|
|
|
70 RW 5 343 6 2 1 7 70 -1 2 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 342 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 341 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
309 CLK_000_D_1_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 0 5 0 1 2 5 7 -1 -1 3 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 5 5 1 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
342 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_25 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 3 2 5 6 -1 -1 1 0 21
|
|
|
|
|
346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
343 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
|
|
|
|
319 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
313 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 2 5 6 59 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 0 63 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 7 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21
|
|
|
|
|
81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 344 6 2 2 3 68 -1 3 0 21
|
|
|
|
|
70 RW 5 343 6 2 2 7 70 -1 2 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 342 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 341 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 4 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 3 5 2 3 4 5 7 -1 -1 1 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 4 0 21
|
|
|
|
|
342 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21
|
|
|
|
|
294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 5 2 1 5 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 5 2 1 5 -1 -1 2 1 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21
|
|
|
|
|
313 inst_CLK_OUT_PRE_50 3 -1 6 2 1 6 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 5 2 5 6 -1 -1 1 0 21
|
|
|
|
|
346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21
|
|
|
|
|
343 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
336 N_262 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
319 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
|
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 1 0 63 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 4 10 -1
|
|
|
|
|
115 "number of signals after reading design file"
|
|
|
|
|
|
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
|
|
|
"num name type sig num out pin node cnt PT type"
|
|
|
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
|
|
|
|
|
|
41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21
|
|
|
|
|
79 RW_000 5 338 7 3 4 5 6 79 -1 4 0 21
|
|
|
|
|
31 UDS_000 5 -1 3 3 2 5 6 31 -1 1 0 21
|
|
|
|
|
30 LDS_000 5 -1 3 3 2 5 6 30 -1 1 0 21
|
|
|
|
|
68 A_0_ 5 344 6 2 3 5 68 -1 3 0 21
|
|
|
|
|
70 RW 5 343 6 2 3 7 70 -1 2 0 21
|
|
|
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
|
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
|
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
|
|
|
40 BERR 5 -1 4 1 0 40 -1 1 0 21
|
|
|
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
|
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
|
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
|
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
|
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
|
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
|
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
|
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
|
|
|
8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21
|
|
|
|
|
7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21
|
|
|
|
|
6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21
|
|
|
|
|
82 BGACK_030 5 340 7 0 82 -1 3 0 21
|
|
|
|
|
34 VMA 5 342 3 0 34 -1 3 0 21
|
|
|
|
|
80 DSACK1 5 341 7 0 80 -1 2 0 21
|
|
|
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
|
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
|
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
|
|
|
28 BG_000 5 339 3 0 28 -1 2 0 21
|
|
|
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
|
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
|
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
|
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
|
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
|
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
|
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
|
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
|
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
|
|
|
340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
|
|
|
311 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
|
|
|
309 CLK_000_D_1_ 3 -1 7 6 0 1 3 4 6 7 -1 -1 1 0 21
|
|
|
|
|
312 CLK_000_D_0_ 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21
|
|
|
|
|
324 SM_AMIGA_6_ 3 -1 1 4 1 3 5 7 -1 -1 3 0 21
|
|
|
|
|
295 cpu_est_0_ 3 -1 1 4 0 1 3 6 -1 -1 3 0 21
|
|
|
|
|
299 inst_AS_030_D0 3 -1 4 4 2 3 4 7 -1 -1 1 0 21
|
|
|
|
|
302 inst_AS_000_DMA 3 -1 2 3 2 5 7 -1 -1 7 0 21
|
|
|
|
|
300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21
|
|
|
|
|
305 CYCLE_DMA_1_ 3 -1 6 3 2 5 6 -1 -1 4 0 21
|
|
|
|
|
296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
|
|
|
|
335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21
|
|
|
|
|
325 SM_AMIGA_4_ 3 -1 6 3 0 3 6 -1 -1 3 0 21
|
|
|
|
|
306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
|
|
|
304 CYCLE_DMA_0_ 3 -1 6 3 2 5 6 -1 -1 3 0 21
|
|
|
|
|
301 inst_BGACK_030_INT_D 3 -1 4 3 2 5 6 -1 -1 1 0 21
|
|
|
|
|
293 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21
|
|
|
|
|
303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21
|
|
|
|
|
331 inst_CLK_030_H 3 -1 2 2 2 5 -1 -1 8 0 21
|
|
|
|
|
342 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
|
|
|
332 SM_AMIGA_5_ 3 -1 3 2 3 6 -1 -1 3 0 21
|
|
|
|
|
327 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21
|
|
|
|
|
326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
|
|
|
|
|
321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
|
|
|
307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
|
|
|
320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
|
|
|
314 inst_CLK_OUT_PRE_25 3 -1 6 2 6 7 -1 -1 2 0 21
|
|
|
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
|
|
|
297 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21
|
|
|
|
|
315 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21
|
|
|
|
|
313 inst_CLK_OUT_PRE_50 3 -1 0 2 0 6 -1 -1 1 0 21
|
|
|
|
|
308 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21
|
|
|
|
|
346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
|
|
|
345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
|
|
|
337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
|
|
|
334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
|
|
|
|
|
333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
|
|
|
|
|
338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
|
|
|
328 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
|
|
|
344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
|
|
|
322 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21
|
|
|
|
|
343 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
|
|
|
341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
|
|
|
339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
|
|
|
336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
|
|
|
330 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
|
|
|
329 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
|
|
|
323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
|
|
|
319 CLK_000_D_2_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
|
|
|
318 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
317 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
|
|
|
316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
|
|
|
310 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21
|
|
|
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
|
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
|
|
|
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
|
|
|
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
|
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
|
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
|
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
|
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
|
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
|
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
|
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
|
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
|
|
|
63 CLK_030 1 -1 -1 2 2 5 63 -1
|
|
|
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
|
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
|
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
|
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
|
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
|
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
|
|
|
59 A_1_ 1 -1 -1 1 5 59 -1
|
|
|
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
|
|
|
29 DTACK 1 -1 -1 1 7 29 -1
|
|
|
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
|
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
