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68030tk
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Clarified some thing Timing can be adjusted with constants

This commit is contained in:
MHeinrichs 2016-08-19 00:22:24 +02:00
parent 0c2122cd7f
commit 23323633f9
59 changed files with 40637 additions and 16688 deletions
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98
Logic/68030-68000-bus.vhd
View File

@ -20,9 +20,11 @@ port(
UDS_000: inout std_logic;
LDS_000: inout std_logic;
SIZE: inout std_logic_vector ( 1 downto 0 );
A: in std_logic_vector ( 31 downto 2 );
A0: inout std_logic;
A1: in std_logic;
AHIGH: inout std_logic_vector ( 31 downto 24 );
A_DECODE: in std_logic_vector ( 23 downto 2 );
A: inout std_logic_vector ( 1 downto 0 );
--A0: inout std_logic;
--A1: in std_logic;
nEXP_SPACE: in std_logic ;
BERR: inout std_logic ;
BG_030: in std_logic ;
@ -59,6 +61,10 @@ end BUS68030;
architecture Behavioral of BUS68030 is
-- values are determined empiracally for 7.09 MHz Clock with a base clock of 100Mhz
constant PE_CLK : integer := 10;
constant NE_CLK : integer := 12;
constant DS_SAMPLE : integer := 12;
@ -96,7 +102,6 @@ signal SM_AMIGA : SM_68000;
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal AS_000_INT:STD_LOGIC := '1';
signal RW_000_INT:STD_LOGIC := '1';
signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
signal AS_030_D0:STD_LOGIC := '1';
@ -126,9 +131,9 @@ signal CLK_OUT_PRE_D: STD_LOGIC := '1';
signal CLK_OUT_INT: STD_LOGIC := '1';
signal CLK_OUT_EXP_INT: STD_LOGIC := '1';
signal CLK_030_H: STD_LOGIC := '1';
signal CLK_000_D: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000";
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
signal CLK_000_D: STD_LOGIC_VECTOR ( DS_SAMPLE downto 0 );
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( PE_CLK downto 0 );
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( NE_CLK downto 0 );
signal CLK_000_PE: STD_LOGIC := '0';
signal CLK_000_NE: STD_LOGIC := '0';
signal CLK_000_NE_D0: STD_LOGIC := '0';
@ -139,8 +144,15 @@ signal CLK_030_D0: STD_LOGIC := '0';
signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000";
--signal RST_DLY_AMIGA: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000";
--signal RESET_OUT_AMIGA: STD_LOGIC := '0';
begin
CLK_000_PE <= CLK_000_P_SYNC(PE_CLK);
CLK_000_NE <= CLK_000_N_SYNC(NE_CLK);
--CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1);
--CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2);
--pos edge clock process
--no ansynchronious reset! the reset is sampled synchroniously
--this mut be because of the e-clock: The E-Clock has to run CONSTANTLY
@ -166,20 +178,14 @@ begin
CLK_OUT_EXP_INT <= CLK_OUT_PRE_50;
--delayed Clocks and signals for edge detection
CLK_000_D(0) <= CLK_000;
CLK_000_D(7 downto 1) <= CLK_000_D(6 downto 0);
CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0);
--shift registers for edge detection
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
CLK_000_P_SYNC( PE_CLK downto 1 ) <= CLK_000_P_SYNC( (PE_CLK-1) downto 0 );
CLK_000_P_SYNC(0) <= CLK_000_D(0) AND NOT CLK_000_D(1);
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
CLK_000_N_SYNC( NE_CLK downto 1 ) <= CLK_000_N_SYNC( (NE_CLK-1) downto 0 );
CLK_000_N_SYNC(0) <= NOT CLK_000_D(0) AND CLK_000_D(1);
-- values are determined empiracally for 7.09 MHz Clock
-- since the clock is not symmetrically these values differ!
CLK_000_PE <= CLK_000_P_SYNC(9);
CLK_000_NE <= CLK_000_N_SYNC(11);
--CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1) AND NOT CLK_000_D(2);
--CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2);
CLK_000_NE_D0 <= CLK_000_NE;
-- e-clock is changed on the FALLING edge!
@ -237,7 +243,6 @@ begin
DS_000_DMA <= '1';
SIZE_DMA <= "11";
A0_DMA <= '1';
AMIGA_BUS_ENABLE_INT <= '1';
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
AS_030_D0 <= '1';
@ -285,7 +290,7 @@ begin
if(BG_030= '1')then
BG_000 <= '1';
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
and nEXP_SPACE = '1' and AS_030_D0='1'
and CLK_000_D(0)='1'
) then --bus granted no local access and no AS_030 running!
BG_000 <= '0';
@ -313,8 +318,8 @@ begin
AS_030_D0 = '0' AND --as set
BGACK_030_INT='1' AND
BGACK_030_INT_D='1' AND --no dma -cycle
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
NOT (FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0') AND --FPU-Select
nEXP_SPACE ='1' and --not an expansion space cycle
SM_AMIGA = IDLE_P --last amiga cycle terminated
) then
AS_030_000_SYNC <= '0';
@ -330,12 +335,12 @@ begin
--uds/lds precalculation
if (SM_AMIGA = IDLE_N) then --DS: set udl/lds
if(A0='0') then
if(A(0)='0') then
UDS_000_INT <= '0';
else
UDS_000_INT <= '1';
end if;
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
LDS_000_INT <= '0';
else
LDS_000_INT <= '1';
@ -352,12 +357,10 @@ begin
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
RW_000_INT <= '1';
AMIGA_BUS_ENABLE_INT <= CLK_000_D(1);
if( CLK_000_D(0)='0' and CLK_000_D(1)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
if( CLK_000_D(1)='0' and CLK_000_D(2)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
SM_AMIGA<=IDLE_N; --go to s1
end if;
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
if(CLK_000_PE='1')then --go to s2
SM_AMIGA <= AS_SET_P; --as for amiga set!
end if;
@ -392,8 +395,8 @@ begin
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
DS_000_ENABLE <= '1';
if( (CLK_000_N_SYNC( 9)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
DSACK1_INT <='0';
end if;
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
@ -403,14 +406,11 @@ begin
if(CLK_000_PE='1')then --go to s0
SM_AMIGA<=IDLE_P;
RW_000_INT <= '1';
--AMIGA_BUS_ENABLE_INT <= '1';
end if;
end case;
--dma stuff
if(BGACK_030_INT='0')then
--switch amiga bus on for DMA-Cycles
AMIGA_BUS_ENABLE_INT <= '0' ;
--set some signals NOT linked to AS_000='0'
RW_000_DMA <= RW_000;
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
@ -427,11 +427,10 @@ begin
A0_DMA <= UDS_000;
--A1 is set by the amiga side
--here we determine the upper or lower half of the databus
AMIGA_BUS_ENABLE_DMA_HIGH <= A1;
AMIGA_BUS_ENABLE_DMA_LOW <= not A1;
AMIGA_BUS_ENABLE_DMA_HIGH <= A(1);
AMIGA_BUS_ENABLE_DMA_LOW <= not A(1);
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
AMIGA_BUS_ENABLE_INT <= '1' ;
RW_000_DMA <= '1';
SIZE_DMA <= "00";
A0_DMA <= '0';
@ -496,9 +495,8 @@ begin
--RESET <= RESET_OUT;
-- bus drivers
--AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
AMIGA_ADDR_ENABLE <= '0';
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
'1';
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
@ -507,26 +505,26 @@ begin
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
'0'; --Point towarts TK
--dma stuff
DTACK <= 'Z';
--DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
-- '0' when DSACK1 ='0' else
-- '1';
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
DTACK <= 'Z'; --DTACK will be generated by GARY!
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
'0' when AS_000_DMA ='0' and AS_000 ='0' else
'1';
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
'0' when DS_000_DMA ='0' and AS_000 ='0' else
'1';
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
'0' when A0_DMA ='0' else
'1';
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
A(1) <= 'Z';
AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else x"00";
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else
"10" when SIZE_DMA ="10" else
"01" when SIZE_DMA ="01" else
"00";
@ -538,19 +536,17 @@ begin
BGACK_030 <= BGACK_030_INT;
--fpu
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
else '1';
--if no copro is installed:
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
else 'Z';
--BERR <= 'Z';
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
CIIN <= '1' WHEN AHIGH(31 downto 24) = x"00" and A_DECODE(23 downto 20) = x"F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
'Z' WHEN nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
'0'; --off for the Amiga
--e and VMA
@ -584,7 +580,7 @@ begin
'1';
--dsack
DSACK1 <= 'Z' when nEXP_SPACE_D0 = '0' else -- output on amiga cycle
DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
'0' when DSACK1_INT ='0' else
'1';

6
Logic/68030_TK.STY
View File

@ -1,4 +1,6 @@
[STRATEGY-LIST]
Normal=True, 1412327082
[synthesis-type]
tool=Synplify
[STRATEGY-LIST]
Normal=True, 1412327082
[TOUCHED-REPORT]
Design.tt4File=1471555574

8
Logic/68030_TK.cmi
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@ -1,15 +1,15 @@
[WINDOWS]
MAIN_WINDOW_POSITION=2,26,1922,1041
LEFT_PANE_WIDTH=634
MAIN_WINDOW_POSITION=-7,0,967,1167
LEFT_PANE_WIDTH=245
CHILD_FRAME_STATE=Maximal
CHILD_WINDOW_SIZE=1920,789
CHILD_WINDOW_SIZE=974,941
CHILD_WINDOW_POS=-8,-31
[GUI SETTING]
Remember_Setting=1
Open_PV_Opt=2
Open_PV=0
PV_IS_ACTIVE=0
ACTIVE_SHEET=Global Constraints
ACTIVE_SHEET=Pin Attributes
Show_Def_Opt=2
Show_Def_Val=1
Expand_All_Column=0

22
Logic/68030_TK.lci
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 03/16/2015;
TIME = 21:53:52;
DATE = 08/18/2016;
TIME = 23:26:14;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -100,6 +100,24 @@ FPU_SENSE = Pin, 91, -, A, -;
A1 = Pin, 60, -, F, -;
A_3_ = Pin, 44, -, E, -;
A_2_ = Pin, 43, -, E, -;
AHIGH_24_ = Pin, 19, -, C, -;
AHIGH_25_ = Pin, 18, -, C, -;
AHIGH_26_ = Pin, 17, -, C, -;
AHIGH_27_ = Pin, 16, -, C, -;
AHIGH_28_ = Pin, 15, -, C, -;
AHIGH_29_ = Pin, 6, -, B, -;
AHIGH_30_ = Pin, 5, -, B, -;
AHIGH_31_ = Pin, 4, -, B, -;
A_1_ = Pin, 60, -, F, -;
A_0_ = Pin, 69, -, G, -;
A_DECODE_16_ = Pin, 96, -, A, -;
A_DECODE_17_ = Pin, 59, -, F, -;
A_DECODE_18_ = Pin, 95, -, A, -;
A_DECODE_19_ = Pin, 97, -, A, -;
A_DECODE_20_ = Pin, 93, -, A, -;
A_DECODE_21_ = Pin, 94, -, A, -;
A_DECODE_22_ = Pin, 84, -, H, -;
A_DECODE_23_ = Pin, 85, -, H, -;
[Group Assignments]
layer = OFF;

22
Logic/68030_TK.lct
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 03/16/2015;
TIME = 21:53:52;
DATE = 08/18/2016;
TIME = 23:26:14;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -100,6 +100,24 @@ FPU_SENSE = Pin, 91, -, A, -;
A1 = Pin, 60, -, F, -;
A_3_ = Pin, 44, -, E, -;
A_2_ = Pin, 43, -, E, -;
AHIGH_24_ = Pin, 19, -, C, -;
AHIGH_25_ = Pin, 18, -, C, -;
AHIGH_26_ = Pin, 17, -, C, -;
AHIGH_27_ = Pin, 16, -, C, -;
AHIGH_28_ = Pin, 15, -, C, -;
AHIGH_29_ = Pin, 6, -, B, -;
AHIGH_30_ = Pin, 5, -, B, -;
AHIGH_31_ = Pin, 4, -, B, -;
A_1_ = Pin, 60, -, F, -;
A_0_ = Pin, 69, -, G, -;
A_DECODE_16_ = Pin, 96, -, A, -;
A_DECODE_17_ = Pin, 59, -, F, -;
A_DECODE_18_ = Pin, 95, -, A, -;
A_DECODE_19_ = Pin, 97, -, A, -;
A_DECODE_20_ = Pin, 93, -, A, -;
A_DECODE_21_ = Pin, 94, -, A, -;
A_DECODE_22_ = Pin, 84, -, H, -;
A_DECODE_23_ = Pin, 85, -, H, -;
[Group Assignments]
layer = OFF;

2
Logic/68030_TK.syn
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@ -1,5 +1,5 @@
JDF B
// Created by Version 1.8
// Created by Version 2.0
PROJECT 68030_TK
DESIGN 68030_tk Normal
DEVKIT M4A5-128/64-10VC

13975
Logic/68030_TK.tcl
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Logic/68030_tk.bl2
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Logic/68030_tk.bl3
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2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 2.0.00.17.20.15
// Design '68030_tk' created Wed Aug 17 17:45:46 2016
// Design '68030_tk' created Fri Aug 19 00:20:41 2016
// LEGEND: '>' Functional Block Port Separator

414
Logic/68030_tk.eq3
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@ -2,13 +2,15 @@
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Wed Aug 17 17:45:46 2016
Design bus68030 created Fri Aug 19 00:20:41 2016
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
1 2 1 Pin SIZE_1_
1 2 1 Pin SIZE_1_.OE
0 0 1 Pin AHIGH_31_
1 3 1 Pin AHIGH_31_.OE
1 2 1 Pin AS_030-
1 3 1 Pin AS_030.OE
1 2 1 Pin AS_000-
@ -29,25 +31,39 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
0 0 1 Pin RESET
1 1 1 Pin RESET.OE
0 0 1 Pin AMIGA_ADDR_ENABLE
1 2 1 Pin SIZE_0_
1 2 1 Pin SIZE_0_.OE
2 4 1 Pin AMIGA_BUS_DATA_DIR
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
3 5 1 Pin AMIGA_BUS_ENABLE_HIGH
1 13 1 Pin CIIN
1 1 1 Pin CIIN.OE
1 2 1 Pin SIZE_0_
1 2 1 Pin SIZE_0_.OE
0 0 1 Pin AHIGH_30_
1 3 1 Pin AHIGH_30_.OE
0 0 1 Pin AHIGH_29_
1 3 1 Pin AHIGH_29_.OE
0 0 1 Pin AHIGH_28_
1 3 1 Pin AHIGH_28_.OE
0 0 1 Pin AHIGH_27_
1 3 1 Pin AHIGH_27_.OE
0 0 1 Pin AHIGH_26_
1 3 1 Pin AHIGH_26_.OE
0 0 1 Pin AHIGH_25_
1 3 1 Pin AHIGH_25_.OE
0 0 1 Pin AHIGH_24_
1 3 1 Pin AHIGH_24_.OE
10 8 1 Pin IPL_030_2_.D-
1 1 1 Pin IPL_030_2_.C
1 2 1 Pin RW_000.OE
3 7 1 Pin RW_000.D-
1 1 1 Pin RW_000.C
1 3 1 Pin A_0_.OE
3 5 1 Pin A_0_.D
1 1 1 Pin A_0_.C
10 8 1 Pin IPL_030_1_.D-
1 1 1 Pin IPL_030_1_.C
10 8 1 Pin IPL_030_0_.D-
1 1 1 Pin IPL_030_0_.C
1 2 1 Pin RW_000.OE
3 7 1 Pin RW_000.D-
1 1 1 Pin RW_000.C
1 3 1 Pin A0.OE
3 5 1 Pin A0.D
1 1 1 Pin A0.C
2 6 1 Pin BG_000.D-
1 1 1 Pin BG_000.C
3 5 1 Pin BGACK_030.D
@ -55,14 +71,14 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
1 1 1 Pin DSACK1.OE
4 9 1 Pin DSACK1.D-
4 10 1 Pin DSACK1.D-
1 1 1 Pin DSACK1.C
3 9 1 Pin VMA.T
1 1 1 Pin VMA.C
1 2 1 Pin RW.OE
2 5 1 Pin RW.D-
1 1 1 Pin RW.C
4 11 1 Node N_317_i-
3 10 1 Node N_226
4 4 1 Node cpu_est_2_.D
1 1 1 Node cpu_est_2_.C
3 5 1 Node cpu_est_3_.D
@ -73,14 +89,10 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Node cpu_est_1_.C
2 5 1 Node inst_AS_000_INT.D-
1 1 1 Node inst_AS_000_INT.C
3 6 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
1 2 1 Node inst_AS_030_D0.D-
1 1 1 Node inst_AS_030_D0.C
1 2 1 Node inst_nEXP_SPACE_D0reg.D-
1 1 1 Node inst_nEXP_SPACE_D0reg.C
7 14 1 Node inst_AS_030_000_SYNC.D-
1 1 1 Node inst_AS_030_000_SYNC.C
1 2 1 Node inst_BGACK_030_INT_D.D-
@ -105,6 +117,10 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Node inst_LDS_000_INT.C
1 1 1 Node inst_CLK_OUT_PRE_D.D
1 1 1 Node inst_CLK_OUT_PRE_D.C
1 1 1 Node CLK_000_D_10_.D
1 1 1 Node CLK_000_D_10_.C
1 1 1 Node CLK_000_D_11_.D
1 1 1 Node CLK_000_D_11_.C
1 2 1 Node inst_DTACK_D0.D-
1 1 1 Node inst_DTACK_D0.C
2 6 1 Node inst_RESET_OUT.D
@ -115,30 +131,44 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_0_.D
1 1 1 Node CLK_000_D_0_.C
1 1 1 Node inst_CLK_000_PE.D
1 1 1 Node inst_CLK_000_PE.C
1 1 1 Node CLK_000_P_SYNC_9_.D
1 1 1 Node CLK_000_P_SYNC_9_.C
1 1 1 Node inst_CLK_000_NE.D
1 1 1 Node inst_CLK_000_NE.C
1 1 1 Node CLK_000_N_SYNC_11_.D
1 1 1 Node CLK_000_N_SYNC_11_.C
1 1 1 Node CLK_000_P_SYNC_10_.D
1 1 1 Node CLK_000_P_SYNC_10_.C
3 6 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
1 2 1 Node IPL_D0_0_.D-
1 1 1 Node IPL_D0_0_.C
1 2 1 Node IPL_D0_1_.D-
1 1 1 Node IPL_D0_1_.C
1 2 1 Node IPL_D0_2_.D-
1 1 1 Node IPL_D0_2_.C
1 1 1 Node inst_CLK_000_NE_D0.D
1 1 1 Node inst_CLK_000_NE_D0.C
1 1 1 Node CLK_000_D_2_.D
1 1 1 Node CLK_000_D_2_.C
1 1 1 Node CLK_000_D_3_.D
1 1 1 Node CLK_000_D_3_.C
1 1 1 Node CLK_000_D_4_.D
1 1 1 Node CLK_000_D_4_.C
1 1 1 Node CLK_000_D_5_.D
1 1 1 Node CLK_000_D_5_.C
1 1 1 Node CLK_000_D_6_.D
1 1 1 Node CLK_000_D_6_.C
1 1 1 Node CLK_000_D_7_.D
1 1 1 Node CLK_000_D_7_.C
1 1 1 Node CLK_000_D_8_.D
1 1 1 Node CLK_000_D_8_.C
1 1 1 Node CLK_000_D_9_.D
1 1 1 Node CLK_000_D_9_.C
1 1 1 Node CLK_000_D_12_.D
1 1 1 Node CLK_000_D_12_.C
2 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
1 2 1 Node CLK_000_N_SYNC_0_.D
1 1 1 Node CLK_000_N_SYNC_0_.C
3 6 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
5 11 1 Node inst_DS_000_ENABLE.D
1 1 1 Node inst_DS_000_ENABLE.C
1 1 1 Node CLK_000_N_SYNC_12_.D
1 1 1 Node CLK_000_N_SYNC_12_.C
3 5 1 Node RST_DLY_0_.D
1 1 1 Node RST_DLY_0_.C
4 5 1 Node RST_DLY_1_.D
@ -163,8 +193,8 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Node CLK_000_P_SYNC_7_.C
1 1 1 Node CLK_000_P_SYNC_8_.D
1 1 1 Node CLK_000_P_SYNC_8_.C
1 2 1 Node CLK_000_N_SYNC_0_.D
1 1 1 Node CLK_000_N_SYNC_0_.C
1 1 1 Node CLK_000_P_SYNC_9_.D
1 1 1 Node CLK_000_P_SYNC_9_.C
1 1 1 Node CLK_000_N_SYNC_1_.D
1 1 1 Node CLK_000_N_SYNC_1_.C
1 1 1 Node CLK_000_N_SYNC_2_.D
@ -185,7 +215,13 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Node CLK_000_N_SYNC_9_.C
1 1 1 Node CLK_000_N_SYNC_10_.D
1 1 1 Node CLK_000_N_SYNC_10_.C
3 9 1 Node SM_AMIGA_6_.D
1 1 1 Node CLK_000_N_SYNC_11_.D
1 1 1 Node CLK_000_N_SYNC_11_.C
1 1 1 Node inst_CLK_000_NE_D0.D
1 1 1 Node inst_CLK_000_NE_D0.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
3 8 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
8 10 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
@ -199,9 +235,9 @@ Design bus68030 created Wed Aug 17 17:45:46 2016
1 1 1 Node SM_AMIGA_i_7_.C
2 14 1 Node CIIN_0
=========
323 P-Term Total: 323
351 P-Term Total: 351
Total Pins: 61
Total Nodes: 69
Total Nodes: 79
Average P-Term/Output: 2
@ -209,11 +245,15 @@ Equations:
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
AHIGH_31_ = (0);
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
@ -221,7 +261,7 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
@ -233,13 +273,13 @@ LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AVEC = (1);
@ -252,22 +292,51 @@ RESET.OE = (!inst_RESET_OUT.Q);
AMIGA_ADDR_ENABLE = (0);
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
# !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN);
!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
# BGACK_030.Q & !SM_AMIGA_i_7_.Q);
# BGACK_030.Q & !SM_AMIGA_i_7_.Q
# CLK_000 & BGACK_030.Q & SM_AMIGA_0_.Q);
CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
CIIN.OE = (CIIN_0);
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
AHIGH_30_ = (0);
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_29_ = (0);
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_28_ = (0);
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_27_ = (0);
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_26_ = (0);
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_25_ = (0);
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_24_ = (0);
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
@ -281,6 +350,22 @@ CIIN.OE = (CIIN_0);
IPL_030_2_.C = (CLK_OSZI);
RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
# RST & !CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
RW_000.C = (CLK_OSZI);
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
A_0_.D = (!RST
# !BGACK_030.Q & UDS_000.PIN
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q);
A_0_.C = (CLK_OSZI);
!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
@ -307,30 +392,14 @@ IPL_030_1_.C = (CLK_OSZI);
IPL_030_0_.C = (CLK_OSZI);
RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
# RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
RW_000.C = (CLK_OSZI);
A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
A0.D = (!RST
# !BGACK_030.Q & UDS_000.PIN
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);
A0.C = (CLK_OSZI);
!BG_000.D = (!BG_030 & RST & !BG_000.Q
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q);
# nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q);
BG_000.C = (CLK_OSZI);
BGACK_030.D = (!RST
# BGACK_000 & BGACK_030.Q
# BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN);
# BGACK_000 & CLK_000_P_SYNC_10_.Q & AS_000.PIN);
BGACK_030.C = (CLK_OSZI);
@ -338,18 +407,18 @@ CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
CLK_EXP.C = (CLK_OSZI);
DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
DSACK1.OE = (nEXP_SPACE);
!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
# !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
# RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN
# !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q
# RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q);
DSACK1.C = (CLK_OSZI);
VMA.T = (!RST & !VMA.Q
# !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_PE.Q
# RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q);
# !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_P_SYNC_10_.Q
# RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_N_SYNC_12_.Q);
VMA.C = (CLK_OSZI);
@ -360,10 +429,9 @@ RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
RW.C = (CLK_OSZI);
!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
N_226 = (!nEXP_SPACE & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !CLK_000_N_SYNC_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q
# cpu_est_2_.Q & !cpu_est_1_.Q
@ -394,13 +462,7 @@ cpu_est_1_.C = (CLK_OSZI);
inst_AS_000_INT.C = (CLK_OSZI);
SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
# RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
# RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
SM_AMIGA_5_.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
@ -409,17 +471,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
inst_AS_030_D0.C = (CLK_OSZI);
!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);
inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
# !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
# !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
inst_AS_030_000_SYNC.C = (CLK_OSZI);
@ -449,14 +507,14 @@ inst_DS_000_DMA.D = (!RST
inst_DS_000_DMA.C = (CLK_OSZI);
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN);
CYCLE_DMA_0_.C = (CLK_OSZI);
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN);
CYCLE_DMA_1_.C = (CLK_OSZI);
@ -477,13 +535,13 @@ SIZE_DMA_1_.C = (CLK_OSZI);
inst_VPA_D.C = (CLK_OSZI);
!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
# RST & SM_AMIGA_6_.Q & !A0.PIN);
# RST & SM_AMIGA_6_.Q & !A_0_.PIN);
inst_UDS_000_INT.C = (CLK_OSZI);
inst_LDS_000_INT.D = (!RST
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN);
inst_LDS_000_INT.C = (CLK_OSZI);
@ -491,12 +549,20 @@ inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
CLK_000_D_10_.D = (CLK_000_D_9_.Q);
CLK_000_D_10_.C = (CLK_OSZI);
CLK_000_D_11_.D = (CLK_000_D_10_.Q);
CLK_000_D_11_.C = (CLK_OSZI);
!inst_DTACK_D0.D = (!DTACK & RST);
inst_DTACK_D0.C = (CLK_OSZI);
inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
# RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
inst_RESET_OUT.C = (CLK_OSZI);
@ -512,21 +578,15 @@ CLK_000_D_0_.D = (CLK_000);
CLK_000_D_0_.C = (CLK_OSZI);
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
CLK_000_P_SYNC_10_.D = (CLK_000_P_SYNC_9_.Q);
inst_CLK_000_PE.C = (CLK_OSZI);
CLK_000_P_SYNC_10_.C = (CLK_OSZI);
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
SM_AMIGA_5_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_6_.Q
# RST & SM_AMIGA_5_.Q & !CLK_000_N_SYNC_12_.Q & BERR.PIN
# RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
inst_CLK_000_NE.C = (CLK_OSZI);
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
SM_AMIGA_5_.C = (CLK_OSZI);
!IPL_D0_0_.D = (RST & !IPL_0_);
@ -540,49 +600,84 @@ IPL_D0_1_.C = (CLK_OSZI);
IPL_D0_2_.C = (CLK_OSZI);
inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
CLK_000_D_2_.D = (CLK_000_D_1_.Q);
inst_CLK_000_NE_D0.C = (CLK_OSZI);
CLK_000_D_2_.C = (CLK_OSZI);
SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
CLK_000_D_3_.D = (CLK_000_D_2_.Q);
CLK_000_D_3_.C = (CLK_OSZI);
CLK_000_D_4_.D = (CLK_000_D_3_.Q);
CLK_000_D_4_.C = (CLK_OSZI);
CLK_000_D_5_.D = (CLK_000_D_4_.Q);
CLK_000_D_5_.C = (CLK_OSZI);
CLK_000_D_6_.D = (CLK_000_D_5_.Q);
CLK_000_D_6_.C = (CLK_OSZI);
CLK_000_D_7_.D = (CLK_000_D_6_.Q);
CLK_000_D_7_.C = (CLK_OSZI);
CLK_000_D_8_.D = (CLK_000_D_7_.Q);
CLK_000_D_8_.C = (CLK_OSZI);
CLK_000_D_9_.D = (CLK_000_D_8_.Q);
CLK_000_D_9_.C = (CLK_OSZI);
CLK_000_D_12_.D = (CLK_000_D_11_.Q);
CLK_000_D_12_.C = (CLK_OSZI);
SM_AMIGA_0_.D = (RST & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q
# RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_0_.Q & BERR.PIN);
SM_AMIGA_0_.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
# RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
# RST & SM_AMIGA_5_.Q & CLK_000_N_SYNC_12_.Q
# RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & BERR.PIN);
SM_AMIGA_4_.C = (CLK_OSZI);
inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
# RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
# RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
# RST & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN
# RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN
# RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN);
inst_DS_000_ENABLE.C = (CLK_OSZI);
RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
# RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
CLK_000_N_SYNC_12_.D = (CLK_000_N_SYNC_11_.Q);
CLK_000_N_SYNC_12_.C = (CLK_OSZI);
RST_DLY_0_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q
# RST & CLK_000_N_SYNC_12_.Q & !RST_DLY_0_.Q
# RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
RST_DLY_0_.C = (CLK_OSZI);
RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
RST_DLY_1_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_1_.Q
# RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
# RST & RST_DLY_1_.Q & RST_DLY_2_.Q
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q);
# RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q);
RST_DLY_1_.C = (CLK_OSZI);
RST_DLY_2_.D = (RST & RST_DLY_2_.Q
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
# RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
RST_DLY_2_.C = (CLK_OSZI);
@ -622,9 +717,9 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
@ -666,9 +761,22 @@ CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
CLK_000_N_SYNC_10_.C = (CLK_OSZI);
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
inst_CLK_000_NE_D0.D = (CLK_000_N_SYNC_12_.Q);
inst_CLK_000_NE_D0.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
# RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_6_.Q & BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_N_SYNC_0_.Q & !SM_AMIGA_i_7_.Q);
SM_AMIGA_6_.C = (CLK_OSZI);
@ -683,46 +791,46 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst
inst_CLK_030_H.C = (CLK_OSZI);
SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
# RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
SM_AMIGA_1_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
# RST & !CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q & BERR.PIN
# RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
# SM_AMIGA_3_.Q & !BERR.PIN
# RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q
# !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q);
# RST & CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q
# !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q
# RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
SM_AMIGA_i_7_.D = (RST & N_317_i & !inst_CLK_000_PE.Q & BERR.PIN
# RST & N_317_i & !SM_AMIGA_0_.Q & BERR.PIN
# RST & N_317_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q
# RST & N_317_i & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
# RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
# RST & N_317_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
# RST & N_317_i & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
# RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
SM_AMIGA_i_7_.D = (RST & !N_226 & !CLK_000_P_SYNC_10_.Q & BERR.PIN
# RST & !N_226 & !SM_AMIGA_0_.Q & BERR.PIN
# RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_3_.Q
# RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
# RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q
# RST & !N_226 & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q
# RST & !N_226 & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
# RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
# RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q
# RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q
# RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
# RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
SM_AMIGA_i_7_.C = (CLK_OSZI);
CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
# !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
CIIN_0 = (nEXP_SPACE
# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
Reverse-Polarity Equations:

386
Logic/68030_tk.fti
View File

@ -1,150 +1,166 @@
#PLAFILE 68030_tk.tt4
#DATE 03/16/2015
#DATE 08/18/2016
#DESIGN <no design name>
#DEVICE mach447a
DATA LOCATION A0:G_8_69 // IO {RN_A0}
DATA LOCATION A1:F_*_60 // INP
DATA LOCATION AHIGH_24_:C_8_19 // IO
DATA LOCATION AHIGH_25_:C_12_18 // IO
DATA LOCATION AHIGH_26_:C_5_17 // IO
DATA LOCATION AHIGH_27_:C_4_16 // IO
DATA LOCATION AHIGH_28_:C_0_15 // IO
DATA LOCATION AHIGH_29_:B_13_6 // IO
DATA LOCATION AHIGH_30_:B_0_5 // IO
DATA LOCATION AHIGH_31_:B_12_4 // IO
DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT
DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_0_20 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT
DATA LOCATION AS_000:E_4_42 // IO
DATA LOCATION AS_030:H_8_82 // IO
DATA LOCATION AVEC:A_4_92 // OUT
DATA LOCATION A_16_:A_*_96 // INP
DATA LOCATION A_17_:F_*_59 // INP
DATA LOCATION A_18_:A_*_95 // INP
DATA LOCATION A_19_:A_*_97 // INP
DATA LOCATION A_20_:A_*_93 // INP
DATA LOCATION A_21_:A_*_94 // INP
DATA LOCATION A_22_:H_*_84 // INP
DATA LOCATION A_23_:H_*_85 // INP
DATA LOCATION A_24_:C_*_19 // INP
DATA LOCATION A_25_:C_*_18 // INP
DATA LOCATION A_26_:C_*_17 // INP
DATA LOCATION A_27_:C_*_16 // INP
DATA LOCATION A_28_:C_*_15 // INP
DATA LOCATION A_29_:B_*_6 // INP
DATA LOCATION A_30_:B_*_5 // INP
DATA LOCATION A_31_:B_*_4 // INP
DATA LOCATION A_0_:G_8_69 // IO {RN_A_0_}
DATA LOCATION A_1_:F_*_60 // INP
DATA LOCATION A_DECODE_16_:A_*_96 // INP
DATA LOCATION A_DECODE_17_:F_*_59 // INP
DATA LOCATION A_DECODE_18_:A_*_95 // INP
DATA LOCATION A_DECODE_19_:A_*_97 // INP
DATA LOCATION A_DECODE_20_:A_*_93 // INP
DATA LOCATION A_DECODE_21_:A_*_94 // INP
DATA LOCATION A_DECODE_22_:H_*_84 // INP
DATA LOCATION A_DECODE_23_:H_*_85 // INP
DATA LOCATION BERR:E_0_41 // IO
DATA LOCATION BGACK_000:D_*_28 // INP
DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
DATA LOCATION BGACK_030:H_6_83 // IO {RN_BGACK_030}
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
DATA LOCATION BG_030:C_*_21 // INP
DATA LOCATION CIIN:E_12_47 // OUT
DATA LOCATION CIIN_0:E_5 // NOD
DATA LOCATION CIIN_0:E_10 // NOD
DATA LOCATION CLK_000:*_*_11 // INP
DATA LOCATION CLK_000_D_0_:B_9 // NOD
DATA LOCATION CLK_000_D_1_:E_8 // NOD
DATA LOCATION CLK_000_N_SYNC_0_:E_9 // NOD
DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD
DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD
DATA LOCATION CLK_000_N_SYNC_1_:A_14 // NOD
DATA LOCATION CLK_000_N_SYNC_2_:B_14 // NOD
DATA LOCATION CLK_000_N_SYNC_3_:B_10 // NOD
DATA LOCATION CLK_000_N_SYNC_4_:B_6 // NOD
DATA LOCATION CLK_000_N_SYNC_5_:D_11 // NOD
DATA LOCATION CLK_000_N_SYNC_6_:G_6 // NOD
DATA LOCATION CLK_000_N_SYNC_7_:F_3 // NOD
DATA LOCATION CLK_000_N_SYNC_8_:A_10 // NOD
DATA LOCATION CLK_000_N_SYNC_9_:A_6 // NOD
DATA LOCATION CLK_000_P_SYNC_0_:E_2 // NOD
DATA LOCATION CLK_000_P_SYNC_1_:B_7 // NOD
DATA LOCATION CLK_000_P_SYNC_2_:G_7 // NOD
DATA LOCATION CLK_000_P_SYNC_3_:E_13 // NOD
DATA LOCATION CLK_000_P_SYNC_4_:G_3 // NOD
DATA LOCATION CLK_000_D_0_:G_13 // NOD
DATA LOCATION CLK_000_D_10_:G_15 // NOD
DATA LOCATION CLK_000_D_11_:H_10 // NOD
DATA LOCATION CLK_000_D_12_:H_2 // NOD
DATA LOCATION CLK_000_D_1_:C_6 // NOD
DATA LOCATION CLK_000_D_2_:G_11 // NOD
DATA LOCATION CLK_000_D_3_:G_7 // NOD
DATA LOCATION CLK_000_D_4_:C_11 // NOD
DATA LOCATION CLK_000_D_5_:E_13 // NOD
DATA LOCATION CLK_000_D_6_:B_11 // NOD
DATA LOCATION CLK_000_D_7_:G_3 // NOD
DATA LOCATION CLK_000_D_8_:B_7 // NOD
DATA LOCATION CLK_000_D_9_:D_11 // NOD
DATA LOCATION CLK_000_N_SYNC_0_:D_2 // NOD
DATA LOCATION CLK_000_N_SYNC_10_:C_14 // NOD
DATA LOCATION CLK_000_N_SYNC_11_:C_10 // NOD
DATA LOCATION CLK_000_N_SYNC_12_:D_13 // NOD
DATA LOCATION CLK_000_N_SYNC_1_:E_9 // NOD
DATA LOCATION CLK_000_N_SYNC_2_:A_3 // NOD
DATA LOCATION CLK_000_N_SYNC_3_:F_7 // NOD
DATA LOCATION CLK_000_N_SYNC_4_:A_14 // NOD
DATA LOCATION CLK_000_N_SYNC_5_:A_6 // NOD
DATA LOCATION CLK_000_N_SYNC_6_:B_3 // NOD
DATA LOCATION CLK_000_N_SYNC_7_:G_6 // NOD
DATA LOCATION CLK_000_N_SYNC_8_:B_14 // NOD
DATA LOCATION CLK_000_N_SYNC_9_:F_3 // NOD
DATA LOCATION CLK_000_P_SYNC_0_:D_7 // NOD
DATA LOCATION CLK_000_P_SYNC_10_:A_8 // NOD
DATA LOCATION CLK_000_P_SYNC_1_:A_15 // NOD
DATA LOCATION CLK_000_P_SYNC_2_:F_11 // NOD
DATA LOCATION CLK_000_P_SYNC_3_:C_7 // NOD
DATA LOCATION CLK_000_P_SYNC_4_:A_11 // NOD
DATA LOCATION CLK_000_P_SYNC_5_:G_14 // NOD
DATA LOCATION CLK_000_P_SYNC_6_:A_3 // NOD
DATA LOCATION CLK_000_P_SYNC_7_:B_3 // NOD
DATA LOCATION CLK_000_P_SYNC_8_:G_10 // NOD
DATA LOCATION CLK_000_P_SYNC_9_:G_15 // NOD
DATA LOCATION CLK_000_P_SYNC_6_:G_10 // NOD
DATA LOCATION CLK_000_P_SYNC_7_:D_3 // NOD
DATA LOCATION CLK_000_P_SYNC_8_:A_7 // NOD
DATA LOCATION CLK_000_P_SYNC_9_:C_3 // NOD
DATA LOCATION CLK_030:*_*_64 // INP
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
DATA LOCATION CLK_EXP:B_0_10 // OUT
DATA LOCATION CLK_EXP:B_1_10 // OUT
DATA LOCATION CLK_OSZI:*_*_61 // Cin
DATA LOCATION CYCLE_DMA_0_:B_5 // NOD
DATA LOCATION CYCLE_DMA_1_:C_12 // NOD
DATA LOCATION CYCLE_DMA_0_:A_10 // NOD
DATA LOCATION CYCLE_DMA_1_:A_2 // NOD
DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1}
DATA LOCATION DS_030:A_0_98 // OUT
DATA LOCATION DTACK:D_*_30 // INP
DATA LOCATION E:G_4_66 // OUT
DATA LOCATION FC_0_:F_*_57 // INP
DATA LOCATION FC_1_:F_*_58 // INP
DATA LOCATION FPU_CS:H_1_78 // OUT
DATA LOCATION FPU_CS:H_4_78 // OUT
DATA LOCATION FPU_SENSE:A_*_91 // INP
DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_}
DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_}
DATA LOCATION IPL_030_1_:B_9_7 // IO {RN_IPL_030_1_}
DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
DATA LOCATION IPL_0_:G_*_67 // INP
DATA LOCATION IPL_1_:F_*_56 // INP
DATA LOCATION IPL_2_:G_*_68 // INP
DATA LOCATION IPL_D0_0_:G_11 // NOD
DATA LOCATION IPL_D0_1_:D_15 // NOD
DATA LOCATION IPL_D0_2_:B_11 // NOD
DATA LOCATION IPL_D0_0_:D_15 // NOD
DATA LOCATION IPL_D0_1_:F_15 // NOD
DATA LOCATION IPL_D0_2_:B_15 // NOD
DATA LOCATION LDS_000:D_12_31 // IO
DATA LOCATION N_317_i:F_14 // NOD
DATA LOCATION RESET:B_1_3 // OUT
DATA LOCATION RN_A0:G_8 // NOD {A0}
DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030}
DATA LOCATION N_226:F_14 // NOD
DATA LOCATION RESET:B_5_3 // OUT
DATA LOCATION RN_A_0_:G_8 // NOD {A_0_}
DATA LOCATION RN_BGACK_030:H_6 // NOD {BGACK_030}
DATA LOCATION RN_BG_000:D_1 // NOD {BG_000}
DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1}
DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_}
DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_}
DATA LOCATION RN_IPL_030_1_:B_9 // NOD {IPL_030_1_}
DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_}
DATA LOCATION RN_RW:G_0 // NOD {RW}
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
DATA LOCATION RST:*_*_86 // INP
DATA LOCATION RST_DLY_0_:D_3 // NOD
DATA LOCATION RST_DLY_1_:D_14 // NOD
DATA LOCATION RST_DLY_2_:D_7 // NOD
DATA LOCATION RST_DLY_0_:D_10 // NOD
DATA LOCATION RST_DLY_1_:D_6 // NOD
DATA LOCATION RST_DLY_2_:D_14 // NOD
DATA LOCATION RW:G_0_71 // IO {RN_RW}
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
DATA LOCATION SIZE_0_:G_12_70 // IO
DATA LOCATION SIZE_1_:H_12_79 // IO
DATA LOCATION SIZE_DMA_0_:G_13 // NOD
DATA LOCATION SIZE_DMA_1_:G_9 // NOD
DATA LOCATION SM_AMIGA_0_:F_1 // NOD
DATA LOCATION SM_AMIGA_1_:F_5 // NOD
DATA LOCATION SM_AMIGA_2_:F_10 // NOD
DATA LOCATION SM_AMIGA_3_:F_6 // NOD
DATA LOCATION SM_AMIGA_4_:F_9 // NOD
DATA LOCATION SIZE_DMA_0_:G_9 // NOD
DATA LOCATION SIZE_DMA_1_:G_5 // NOD
DATA LOCATION SM_AMIGA_0_:F_5 // NOD
DATA LOCATION SM_AMIGA_1_:F_13 // NOD
DATA LOCATION SM_AMIGA_2_:F_6 // NOD
DATA LOCATION SM_AMIGA_3_:F_2 // NOD
DATA LOCATION SM_AMIGA_4_:F_10 // NOD
DATA LOCATION SM_AMIGA_5_:F_8 // NOD
DATA LOCATION SM_AMIGA_6_:F_4 // NOD
DATA LOCATION SM_AMIGA_6_:C_9 // NOD
DATA LOCATION SM_AMIGA_i_7_:F_0 // NOD
DATA LOCATION UDS_000:D_8_32 // IO
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
DATA LOCATION VPA:*_*_36 // INP
DATA LOCATION cpu_est_0_:D_6 // NOD
DATA LOCATION cpu_est_1_:D_2 // NOD
DATA LOCATION cpu_est_2_:D_13 // NOD
DATA LOCATION cpu_est_3_:F_12 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:B_13 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_2 // NOD
DATA LOCATION inst_AS_000_DMA:A_1 // NOD
DATA LOCATION inst_AS_000_INT:C_1 // NOD
DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD
DATA LOCATION inst_AS_030_D0:H_3 // NOD
DATA LOCATION cpu_est_0_:B_2 // NOD
DATA LOCATION cpu_est_1_:F_12 // NOD
DATA LOCATION cpu_est_2_:F_4 // NOD
DATA LOCATION cpu_est_3_:F_1 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_2 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_10 // NOD
DATA LOCATION inst_AS_000_DMA:A_12 // NOD
DATA LOCATION inst_AS_000_INT:G_2 // NOD
DATA LOCATION inst_AS_030_000_SYNC:C_13 // NOD
DATA LOCATION inst_AS_030_D0:H_1 // NOD
DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD
DATA LOCATION inst_CLK_000_NE:G_2 // NOD
DATA LOCATION inst_CLK_000_NE_D0:D_10 // NOD
DATA LOCATION inst_CLK_000_PE:G_5 // NOD
DATA LOCATION inst_CLK_030_H:A_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:F_13 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:A_12 // NOD
DATA LOCATION inst_DS_000_DMA:A_13 // NOD
DATA LOCATION inst_DS_000_ENABLE:C_8 // NOD
DATA LOCATION inst_DTACK_D0:B_15 // NOD
DATA LOCATION inst_LDS_000_INT:A_5 // NOD
DATA LOCATION inst_CLK_000_NE_D0:E_5 // NOD
DATA LOCATION inst_CLK_030_H:A_13 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:E_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD
DATA LOCATION inst_DS_000_DMA:A_9 // NOD
DATA LOCATION inst_DS_000_ENABLE:F_9 // NOD
DATA LOCATION inst_DTACK_D0:C_15 // NOD
DATA LOCATION inst_LDS_000_INT:A_1 // NOD
DATA LOCATION inst_RESET_OUT:D_9 // NOD
DATA LOCATION inst_UDS_000_INT:A_9 // NOD
DATA LOCATION inst_VPA_D:F_2 // NOD
DATA LOCATION inst_nEXP_SPACE_D0reg:A_8 // NOD
DATA LOCATION inst_UDS_000_INT:B_6 // NOD
DATA LOCATION inst_VPA_D:A_5 // NOD
DATA LOCATION nEXP_SPACE:*_*_14 // INP
DATA IO_DIR A0:BI
DATA IO_DIR A1:IN
DATA IO_DIR AHIGH_24_:BI
DATA IO_DIR AHIGH_25_:BI
DATA IO_DIR AHIGH_26_:BI
DATA IO_DIR AHIGH_27_:BI
DATA IO_DIR AHIGH_28_:BI
DATA IO_DIR AHIGH_29_:BI
DATA IO_DIR AHIGH_30_:BI
DATA IO_DIR AHIGH_31_:BI
DATA IO_DIR AMIGA_ADDR_ENABLE:OUT
DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT
DATA IO_DIR AMIGA_BUS_ENABLE_HIGH:OUT
@ -152,22 +168,16 @@ DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT
DATA IO_DIR AS_000:BI
DATA IO_DIR AS_030:BI
DATA IO_DIR AVEC:OUT
DATA IO_DIR A_16_:IN
DATA IO_DIR A_17_:IN
DATA IO_DIR A_18_:IN
DATA IO_DIR A_19_:IN
DATA IO_DIR A_20_:IN
DATA IO_DIR A_21_:IN
DATA IO_DIR A_22_:IN
DATA IO_DIR A_23_:IN
DATA IO_DIR A_24_:IN
DATA IO_DIR A_25_:IN
DATA IO_DIR A_26_:IN
DATA IO_DIR A_27_:IN
DATA IO_DIR A_28_:IN
DATA IO_DIR A_29_:IN
DATA IO_DIR A_30_:IN
DATA IO_DIR A_31_:IN
DATA IO_DIR A_0_:BI
DATA IO_DIR A_1_:IN
DATA IO_DIR A_DECODE_16_:IN
DATA IO_DIR A_DECODE_17_:IN
DATA IO_DIR A_DECODE_18_:IN
DATA IO_DIR A_DECODE_19_:IN
DATA IO_DIR A_DECODE_20_:IN
DATA IO_DIR A_DECODE_21_:IN
DATA IO_DIR A_DECODE_22_:IN
DATA IO_DIR A_DECODE_23_:IN
DATA IO_DIR BERR:BI
DATA IO_DIR BGACK_000:IN
DATA IO_DIR BGACK_030:OUT
@ -205,22 +215,32 @@ DATA IO_DIR VMA:OUT
DATA IO_DIR VPA:IN
DATA IO_DIR nEXP_SPACE:IN
DATA GLB_CLOCK CLK_OSZI
DATA PW_LEVEL A_DECODE_22_:1
DATA SLEW A_DECODE_22_:1
DATA PW_LEVEL A_DECODE_21_:1
DATA SLEW A_DECODE_21_:1
DATA PW_LEVEL SIZE_1_:1
DATA SLEW SIZE_1_:1
DATA PW_LEVEL A_31_:1
DATA SLEW A_31_:1
DATA PW_LEVEL A_DECODE_20_:1
DATA SLEW A_DECODE_20_:1
DATA PW_LEVEL A_DECODE_19_:1
DATA SLEW A_DECODE_19_:1
DATA PW_LEVEL AHIGH_31_:1
DATA SLEW AHIGH_31_:1
DATA PW_LEVEL A_DECODE_18_:1
DATA SLEW A_DECODE_18_:1
DATA PW_LEVEL A_DECODE_17_:1
DATA SLEW A_DECODE_17_:1
DATA PW_LEVEL A_DECODE_23_:1
DATA SLEW A_DECODE_23_:1
DATA PW_LEVEL A_DECODE_16_:1
DATA SLEW A_DECODE_16_:1
DATA PW_LEVEL IPL_2_:1
DATA SLEW IPL_2_:1
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL FC_1_:1
DATA SLEW FC_1_:1
DATA PW_LEVEL IPL_0_:1
DATA SLEW IPL_0_:1
DATA PW_LEVEL AS_030:1
DATA SLEW AS_030:1
DATA PW_LEVEL FC_0_:1
DATA SLEW FC_0_:1
DATA PW_LEVEL AS_000:1
DATA SLEW AS_000:1
DATA PW_LEVEL DS_030:1
@ -229,16 +249,22 @@ DATA PW_LEVEL UDS_000:1
DATA SLEW UDS_000:1
DATA PW_LEVEL LDS_000:1
DATA SLEW LDS_000:1
DATA PW_LEVEL A1:1
DATA SLEW A1:1
DATA SLEW nEXP_SPACE:1
DATA PW_LEVEL BERR:1
DATA SLEW BERR:1
DATA PW_LEVEL BG_030:1
DATA SLEW BG_030:1
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL IPL_0_:1
DATA SLEW IPL_0_:1
DATA PW_LEVEL BGACK_000:1
DATA SLEW BGACK_000:1
DATA PW_LEVEL FC_0_:1
DATA SLEW FC_0_:1
DATA SLEW CLK_030:1
DATA PW_LEVEL A_1_:1
DATA SLEW A_1_:1
DATA SLEW CLK_000:1
DATA SLEW CLK_OSZI:1
DATA PW_LEVEL CLK_DIV_OUT:1
@ -259,56 +285,40 @@ DATA PW_LEVEL RESET:1
DATA SLEW RESET:1
DATA PW_LEVEL AMIGA_ADDR_ENABLE:1
DATA SLEW AMIGA_ADDR_ENABLE:0
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:1
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
DATA SLEW AMIGA_BUS_DATA_DIR:0
DATA PW_LEVEL A_30_:1
DATA SLEW A_30_:1
DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1
DATA SLEW AMIGA_BUS_ENABLE_LOW:0
DATA PW_LEVEL A_29_:1
DATA SLEW A_29_:1
DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
DATA PW_LEVEL A_28_:1
DATA SLEW A_28_:1
DATA PW_LEVEL CIIN:1
DATA SLEW CIIN:1
DATA PW_LEVEL A_27_:1
DATA SLEW A_27_:1
DATA PW_LEVEL A_26_:1
DATA SLEW A_26_:1
DATA PW_LEVEL A_25_:1
DATA SLEW A_25_:1
DATA PW_LEVEL A_24_:1
DATA SLEW A_24_:1
DATA PW_LEVEL A_23_:1
DATA SLEW A_23_:1
DATA PW_LEVEL A_22_:1
DATA SLEW A_22_:1
DATA PW_LEVEL A_21_:1
DATA SLEW A_21_:1
DATA PW_LEVEL A_20_:1
DATA SLEW A_20_:1
DATA PW_LEVEL A_19_:1
DATA SLEW A_19_:1
DATA PW_LEVEL A_18_:1
DATA SLEW A_18_:1
DATA PW_LEVEL A_17_:1
DATA SLEW A_17_:1
DATA PW_LEVEL A_16_:1
DATA SLEW A_16_:1
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:1
DATA PW_LEVEL AHIGH_30_:1
DATA SLEW AHIGH_30_:1
DATA PW_LEVEL AHIGH_29_:1
DATA SLEW AHIGH_29_:1
DATA PW_LEVEL AHIGH_28_:1
DATA SLEW AHIGH_28_:1
DATA PW_LEVEL AHIGH_27_:1
DATA SLEW AHIGH_27_:1
DATA PW_LEVEL AHIGH_26_:1
DATA SLEW AHIGH_26_:1
DATA PW_LEVEL AHIGH_25_:1
DATA SLEW AHIGH_25_:1
DATA PW_LEVEL AHIGH_24_:1
DATA SLEW AHIGH_24_:1
DATA PW_LEVEL IPL_030_2_:1
DATA SLEW IPL_030_2_:1
DATA PW_LEVEL RW_000:1
DATA SLEW RW_000:1
DATA PW_LEVEL A_0_:1
DATA SLEW A_0_:1
DATA PW_LEVEL IPL_030_1_:1
DATA SLEW IPL_030_1_:1
DATA PW_LEVEL IPL_030_0_:1
DATA SLEW IPL_030_0_:1
DATA PW_LEVEL RW_000:1
DATA SLEW RW_000:1
DATA PW_LEVEL A0:1
DATA SLEW A0:1
DATA PW_LEVEL BG_000:1
DATA SLEW BG_000:1
DATA PW_LEVEL BGACK_030:1
@ -321,8 +331,8 @@ DATA PW_LEVEL VMA:1
DATA SLEW VMA:1
DATA PW_LEVEL RW:1
DATA SLEW RW:1
DATA PW_LEVEL N_317_i:1
DATA SLEW N_317_i:1
DATA PW_LEVEL N_226:1
DATA SLEW N_226:1
DATA PW_LEVEL cpu_est_2_:1
DATA SLEW cpu_est_2_:1
DATA PW_LEVEL cpu_est_3_:1
@ -333,14 +343,10 @@ DATA PW_LEVEL cpu_est_1_:1
DATA SLEW cpu_est_1_:1
DATA PW_LEVEL inst_AS_000_INT:1
DATA SLEW inst_AS_000_INT:1
DATA PW_LEVEL SM_AMIGA_5_:1
DATA SLEW SM_AMIGA_5_:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1
DATA PW_LEVEL inst_AS_030_D0:1
DATA SLEW inst_AS_030_D0:1
DATA PW_LEVEL inst_nEXP_SPACE_D0reg:1
DATA SLEW inst_nEXP_SPACE_D0reg:1
DATA PW_LEVEL inst_AS_030_000_SYNC:1
DATA SLEW inst_AS_030_000_SYNC:1
DATA PW_LEVEL inst_BGACK_030_INT_D:1
@ -365,6 +371,10 @@ DATA PW_LEVEL inst_LDS_000_INT:1
DATA SLEW inst_LDS_000_INT:1
DATA PW_LEVEL inst_CLK_OUT_PRE_D:1
DATA SLEW inst_CLK_OUT_PRE_D:1
DATA PW_LEVEL CLK_000_D_10_:1
DATA SLEW CLK_000_D_10_:1
DATA PW_LEVEL CLK_000_D_11_:1
DATA SLEW CLK_000_D_11_:1
DATA PW_LEVEL inst_DTACK_D0:1
DATA SLEW inst_DTACK_D0:1
DATA PW_LEVEL inst_RESET_OUT:1
@ -375,30 +385,44 @@ DATA PW_LEVEL CLK_000_D_1_:1
DATA SLEW CLK_000_D_1_:1
DATA PW_LEVEL CLK_000_D_0_:1
DATA SLEW CLK_000_D_0_:1
DATA PW_LEVEL inst_CLK_000_PE:1
DATA SLEW inst_CLK_000_PE:1
DATA PW_LEVEL CLK_000_P_SYNC_9_:1
DATA SLEW CLK_000_P_SYNC_9_:1
DATA PW_LEVEL inst_CLK_000_NE:1
DATA SLEW inst_CLK_000_NE:1
DATA PW_LEVEL CLK_000_N_SYNC_11_:1
DATA SLEW CLK_000_N_SYNC_11_:1
DATA PW_LEVEL CLK_000_P_SYNC_10_:1
DATA SLEW CLK_000_P_SYNC_10_:1
DATA PW_LEVEL SM_AMIGA_5_:1
DATA SLEW SM_AMIGA_5_:1
DATA PW_LEVEL IPL_D0_0_:1
DATA SLEW IPL_D0_0_:1
DATA PW_LEVEL IPL_D0_1_:1
DATA SLEW IPL_D0_1_:1
DATA PW_LEVEL IPL_D0_2_:1
DATA SLEW IPL_D0_2_:1
DATA PW_LEVEL inst_CLK_000_NE_D0:1
DATA SLEW inst_CLK_000_NE_D0:1
DATA PW_LEVEL CLK_000_D_2_:1
DATA SLEW CLK_000_D_2_:1
DATA PW_LEVEL CLK_000_D_3_:1
DATA SLEW CLK_000_D_3_:1
DATA PW_LEVEL CLK_000_D_4_:1
DATA SLEW CLK_000_D_4_:1
DATA PW_LEVEL CLK_000_D_5_:1
DATA SLEW CLK_000_D_5_:1
DATA PW_LEVEL CLK_000_D_6_:1
DATA SLEW CLK_000_D_6_:1
DATA PW_LEVEL CLK_000_D_7_:1
DATA SLEW CLK_000_D_7_:1
DATA PW_LEVEL CLK_000_D_8_:1
DATA SLEW CLK_000_D_8_:1
DATA PW_LEVEL CLK_000_D_9_:1
DATA SLEW CLK_000_D_9_:1
DATA PW_LEVEL CLK_000_D_12_:1
DATA SLEW CLK_000_D_12_:1
DATA PW_LEVEL SM_AMIGA_0_:1
DATA SLEW SM_AMIGA_0_:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA PW_LEVEL CLK_000_N_SYNC_0_:1
DATA SLEW CLK_000_N_SYNC_0_:1
DATA PW_LEVEL SM_AMIGA_4_:1
DATA SLEW SM_AMIGA_4_:1
DATA PW_LEVEL inst_DS_000_ENABLE:1
DATA SLEW inst_DS_000_ENABLE:1
DATA PW_LEVEL CLK_000_N_SYNC_12_:1
DATA SLEW CLK_000_N_SYNC_12_:1
DATA PW_LEVEL RST_DLY_0_:1
DATA SLEW RST_DLY_0_:1
DATA PW_LEVEL RST_DLY_1_:1
@ -423,8 +447,8 @@ DATA PW_LEVEL CLK_000_P_SYNC_7_:1
DATA SLEW CLK_000_P_SYNC_7_:1
DATA PW_LEVEL CLK_000_P_SYNC_8_:1
DATA SLEW CLK_000_P_SYNC_8_:1
DATA PW_LEVEL CLK_000_N_SYNC_0_:1
DATA SLEW CLK_000_N_SYNC_0_:1
DATA PW_LEVEL CLK_000_P_SYNC_9_:1
DATA SLEW CLK_000_P_SYNC_9_:1
DATA PW_LEVEL CLK_000_N_SYNC_1_:1
DATA SLEW CLK_000_N_SYNC_1_:1
DATA PW_LEVEL CLK_000_N_SYNC_2_:1
@ -445,6 +469,12 @@ DATA PW_LEVEL CLK_000_N_SYNC_9_:1
DATA SLEW CLK_000_N_SYNC_9_:1
DATA PW_LEVEL CLK_000_N_SYNC_10_:1
DATA SLEW CLK_000_N_SYNC_10_:1
DATA PW_LEVEL CLK_000_N_SYNC_11_:1
DATA SLEW CLK_000_N_SYNC_11_:1
DATA PW_LEVEL inst_CLK_000_NE_D0:1
DATA SLEW inst_CLK_000_NE_D0:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA PW_LEVEL SM_AMIGA_6_:1
DATA SLEW SM_AMIGA_6_:1
DATA PW_LEVEL inst_CLK_030_H:1
@ -460,10 +490,10 @@ DATA SLEW SM_AMIGA_i_7_:1
DATA PW_LEVEL CIIN_0:1
DATA SLEW CIIN_0:1
DATA PW_LEVEL RN_IPL_030_2_:1
DATA PW_LEVEL RN_RW_000:1
DATA PW_LEVEL RN_A_0_:1
DATA PW_LEVEL RN_IPL_030_1_:1
DATA PW_LEVEL RN_IPL_030_0_:1
DATA PW_LEVEL RN_RW_000:1
DATA PW_LEVEL RN_A0:1
DATA PW_LEVEL RN_BG_000:1
DATA PW_LEVEL RN_BGACK_030:1
DATA PW_LEVEL RN_DSACK1:1

48
Logic/68030_tk.grp
View File

@ -1,28 +1,30 @@
GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT
inst_UDS_000_INT inst_nEXP_SPACE_D0reg CLK_000_P_SYNC_6_ CLK_000_N_SYNC_1_
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ inst_CLK_OUT_PRE_D DS_030 AVEC
CYCLE_DMA_1_ CYCLE_DMA_0_ inst_VPA_D CLK_000_P_SYNC_10_ CLK_000_P_SYNC_1_
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_4_
CLK_000_N_SYNC_5_ DS_030 AVEC
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ CLK_000_D_0_ CLK_000_P_SYNC_1_
CLK_000_P_SYNC_7_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_
RESET
GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE CYCLE_DMA_1_ inst_AS_000_INT
AMIGA_BUS_ENABLE_LOW
RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_UDS_000_INT
cpu_est_0_ IPL_D0_2_ CLK_000_D_6_ CLK_000_D_8_ CLK_000_N_SYNC_6_
CLK_000_N_SYNC_8_ AHIGH_31_ AHIGH_30_ AHIGH_29_ RESET
GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DTACK_D0 CLK_000_D_4_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_10_
CLK_000_N_SYNC_11_ CLK_000_D_1_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_
AHIGH_24_ AMIGA_BUS_ENABLE_LOW
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_RESET_OUT RST_DLY_0_
RST_DLY_1_ RST_DLY_2_ cpu_est_2_ cpu_est_1_ cpu_est_0_ IPL_D0_1_
CLK_000_N_SYNC_5_ inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
AMIGA_ADDR_ENABLE
GROUP MACH_SEG_E CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_3_
CLK_000_D_1_ CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_6_ SM_AMIGA_1_
SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ inst_VPA_D CLK_000_N_SYNC_7_
inst_CLK_OUT_PRE_50 N_317_i
GROUP MACH_SEG_G A0 RN_A0 RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_
IPL_D0_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_P_SYNC_2_
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_6_
SIZE_0_ E
RST_DLY_1_ RST_DLY_2_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_0_ IPL_D0_0_
CLK_000_D_9_ CLK_000_N_SYNC_12_ CLK_000_P_SYNC_7_ AMIGA_BUS_ENABLE_HIGH
LDS_000 UDS_000 AMIGA_ADDR_ENABLE
GROUP MACH_SEG_E CLK_000_D_5_ inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 CLK_000_N_SYNC_1_
inst_CLK_000_NE_D0 CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE
SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ cpu_est_2_
cpu_est_1_ IPL_D0_1_ CLK_000_P_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_9_
N_226
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_
inst_AS_000_INT CLK_000_D_10_ CLK_000_D_3_ CLK_000_D_7_ CLK_000_P_SYNC_5_
CLK_000_P_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_D_0_ CLK_000_D_2_ SIZE_0_
E
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030
inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_
FPU_CS AS_030 SIZE_1_
inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_D_11_ CLK_000_D_12_ FPU_CS
AS_030 SIZE_1_

2
Logic/68030_tk.ipr
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@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>755;017}nxñA.c
<LATTICE_ENCRYPTED_BLIF>15:;107B74eO

1217
Logic/68030_tk.jed
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190
Logic/68030_tk.lco
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@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 8/17/16;
TIME = 17:45:51;
DATE = 8/19/16;
TIME = 00:20:46;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -76,24 +76,32 @@ Usercode_Format = Hex;
[LOCATION ASSIGNMENTS]
Layer = OFF;
A_DECODE_22_ = pin,84,-,H,-;
A_DECODE_21_ = pin,94,-,A,-;
SIZE_1_ = pin,79,-,H,-;
A_31_ = pin,4,-,B,-;
A_DECODE_20_ = pin,93,-,A,-;
A_DECODE_19_ = pin,97,-,A,-;
AHIGH_31_ = pin,4,-,B,-;
A_DECODE_18_ = pin,95,-,A,-;
A_DECODE_17_ = pin,59,-,F,-;
A_DECODE_23_ = pin,85,-,H,-;
A_DECODE_16_ = pin,96,-,A,-;
IPL_2_ = pin,68,-,G,-;
IPL_1_ = pin,56,-,F,-;
FC_1_ = pin,58,-,F,-;
IPL_0_ = pin,67,-,G,-;
AS_030 = pin,82,-,H,-;
FC_0_ = pin,57,-,F,-;
AS_000 = pin,42,-,E,-;
DS_030 = pin,98,-,A,-;
UDS_000 = pin,32,-,D,-;
LDS_000 = pin,31,-,D,-;
A1 = pin,60,-,F,-;
nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
IPL_1_ = pin,56,-,F,-;
IPL_0_ = pin,67,-,G,-;
BGACK_000 = pin,28,-,D,-;
FC_0_ = pin,57,-,F,-;
CLK_030 = pin,64,-,-,-;
A_1_ = pin,60,-,F,-;
CLK_000 = pin,11,-,-,-;
CLK_OSZI = pin,61,-,-,-;
CLK_DIV_OUT = pin,65,-,G,-;
@ -106,106 +114,108 @@ VPA = pin,36,-,-,-;
RST = pin,86,-,-,-;
RESET = pin,3,-,B,-;
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
SIZE_0_ = pin,70,-,G,-;
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
A_30_ = pin,5,-,B,-;
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
A_29_ = pin,6,-,B,-;
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
A_28_ = pin,15,-,C,-;
CIIN = pin,47,-,E,-;
A_27_ = pin,16,-,C,-;
A_26_ = pin,17,-,C,-;
A_25_ = pin,18,-,C,-;
A_24_ = pin,19,-,C,-;
A_23_ = pin,85,-,H,-;
A_22_ = pin,84,-,H,-;
A_21_ = pin,94,-,A,-;
A_20_ = pin,93,-,A,-;
A_19_ = pin,97,-,A,-;
A_18_ = pin,95,-,A,-;
A_17_ = pin,59,-,F,-;
A_16_ = pin,96,-,A,-;
SIZE_0_ = pin,70,-,G,-;
AHIGH_30_ = pin,5,-,B,-;
AHIGH_29_ = pin,6,-,B,-;
AHIGH_28_ = pin,15,-,C,-;
AHIGH_27_ = pin,16,-,C,-;
AHIGH_26_ = pin,17,-,C,-;
AHIGH_25_ = pin,18,-,C,-;
AHIGH_24_ = pin,19,-,C,-;
IPL_030_2_ = pin,9,-,B,-;
RW_000 = pin,80,-,H,-;
A_0_ = pin,69,-,G,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
RW_000 = pin,80,-,H,-;
A0 = pin,69,-,G,-;
BG_000 = pin,29,-,D,-;
BGACK_030 = pin,83,-,H,-;
CLK_EXP = pin,10,-,B,-;
DSACK1 = pin,81,-,H,-;
VMA = pin,35,-,D,-;
RW = pin,71,-,G,-;
N_317_i = node,-,-,F,14;
cpu_est_2_ = node,-,-,D,13;
cpu_est_3_ = node,-,-,F,12;
cpu_est_0_ = node,-,-,D,6;
cpu_est_1_ = node,-,-,D,2;
inst_AS_000_INT = node,-,-,C,1;
SM_AMIGA_5_ = node,-,-,F,8;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,2;
inst_AS_030_D0 = node,-,-,H,3;
inst_nEXP_SPACE_D0reg = node,-,-,A,8;
inst_AS_030_000_SYNC = node,-,-,C,4;
N_226 = node,-,-,F,14;
cpu_est_2_ = node,-,-,F,4;
cpu_est_3_ = node,-,-,F,1;
cpu_est_0_ = node,-,-,B,2;
cpu_est_1_ = node,-,-,F,12;
inst_AS_000_INT = node,-,-,G,2;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,10;
inst_AS_030_D0 = node,-,-,H,1;
inst_AS_030_000_SYNC = node,-,-,C,13;
inst_BGACK_030_INT_D = node,-,-,H,13;
inst_AS_000_DMA = node,-,-,A,1;
inst_DS_000_DMA = node,-,-,A,13;
CYCLE_DMA_0_ = node,-,-,B,5;
CYCLE_DMA_1_ = node,-,-,C,12;
SIZE_DMA_0_ = node,-,-,G,13;
SIZE_DMA_1_ = node,-,-,G,9;
inst_VPA_D = node,-,-,F,2;
inst_UDS_000_INT = node,-,-,A,9;
inst_LDS_000_INT = node,-,-,A,5;
inst_CLK_OUT_PRE_D = node,-,-,A,12;
inst_DTACK_D0 = node,-,-,B,15;
inst_AS_000_DMA = node,-,-,A,12;
inst_DS_000_DMA = node,-,-,A,9;
CYCLE_DMA_0_ = node,-,-,A,10;
CYCLE_DMA_1_ = node,-,-,A,2;
SIZE_DMA_0_ = node,-,-,G,9;
SIZE_DMA_1_ = node,-,-,G,5;
inst_VPA_D = node,-,-,A,5;
inst_UDS_000_INT = node,-,-,B,6;
inst_LDS_000_INT = node,-,-,A,1;
inst_CLK_OUT_PRE_D = node,-,-,E,8;
CLK_000_D_10_ = node,-,-,G,15;
CLK_000_D_11_ = node,-,-,H,10;
inst_DTACK_D0 = node,-,-,C,15;
inst_RESET_OUT = node,-,-,D,9;
inst_CLK_OUT_PRE_50 = node,-,-,F,13;
CLK_000_D_1_ = node,-,-,E,8;
CLK_000_D_0_ = node,-,-,B,9;
inst_CLK_000_PE = node,-,-,G,5;
CLK_000_P_SYNC_9_ = node,-,-,G,15;
inst_CLK_000_NE = node,-,-,G,2;
CLK_000_N_SYNC_11_ = node,-,-,H,6;
IPL_D0_0_ = node,-,-,G,11;
IPL_D0_1_ = node,-,-,D,15;
IPL_D0_2_ = node,-,-,B,11;
inst_CLK_000_NE_D0 = node,-,-,D,10;
SM_AMIGA_0_ = node,-,-,F,1;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,B,13;
SM_AMIGA_4_ = node,-,-,F,9;
inst_DS_000_ENABLE = node,-,-,C,8;
RST_DLY_0_ = node,-,-,D,3;
RST_DLY_1_ = node,-,-,D,14;
RST_DLY_2_ = node,-,-,D,7;
CLK_000_P_SYNC_0_ = node,-,-,E,2;
CLK_000_P_SYNC_1_ = node,-,-,B,7;
CLK_000_P_SYNC_2_ = node,-,-,G,7;
CLK_000_P_SYNC_3_ = node,-,-,E,13;
CLK_000_P_SYNC_4_ = node,-,-,G,3;
inst_CLK_OUT_PRE_50 = node,-,-,E,2;
CLK_000_D_1_ = node,-,-,C,6;
CLK_000_D_0_ = node,-,-,G,13;
CLK_000_P_SYNC_10_ = node,-,-,A,8;
SM_AMIGA_5_ = node,-,-,F,8;
IPL_D0_0_ = node,-,-,D,15;
IPL_D0_1_ = node,-,-,F,15;
IPL_D0_2_ = node,-,-,B,15;
CLK_000_D_2_ = node,-,-,G,11;
CLK_000_D_3_ = node,-,-,G,7;
CLK_000_D_4_ = node,-,-,C,11;
CLK_000_D_5_ = node,-,-,E,13;
CLK_000_D_6_ = node,-,-,B,11;
CLK_000_D_7_ = node,-,-,G,3;
CLK_000_D_8_ = node,-,-,B,7;
CLK_000_D_9_ = node,-,-,D,11;
CLK_000_D_12_ = node,-,-,H,2;
SM_AMIGA_0_ = node,-,-,F,5;
CLK_000_N_SYNC_0_ = node,-,-,D,2;
SM_AMIGA_4_ = node,-,-,F,10;
inst_DS_000_ENABLE = node,-,-,F,9;
CLK_000_N_SYNC_12_ = node,-,-,D,13;
RST_DLY_0_ = node,-,-,D,10;
RST_DLY_1_ = node,-,-,D,6;
RST_DLY_2_ = node,-,-,D,14;
CLK_000_P_SYNC_0_ = node,-,-,D,7;
CLK_000_P_SYNC_1_ = node,-,-,A,15;
CLK_000_P_SYNC_2_ = node,-,-,F,11;
CLK_000_P_SYNC_3_ = node,-,-,C,7;
CLK_000_P_SYNC_4_ = node,-,-,A,11;
CLK_000_P_SYNC_5_ = node,-,-,G,14;
CLK_000_P_SYNC_6_ = node,-,-,A,3;
CLK_000_P_SYNC_7_ = node,-,-,B,3;
CLK_000_P_SYNC_8_ = node,-,-,G,10;
CLK_000_N_SYNC_0_ = node,-,-,E,9;
CLK_000_N_SYNC_1_ = node,-,-,A,14;
CLK_000_N_SYNC_2_ = node,-,-,B,14;
CLK_000_N_SYNC_3_ = node,-,-,B,10;
CLK_000_N_SYNC_4_ = node,-,-,B,6;
CLK_000_N_SYNC_5_ = node,-,-,D,11;
CLK_000_N_SYNC_6_ = node,-,-,G,6;
CLK_000_N_SYNC_7_ = node,-,-,F,3;
CLK_000_N_SYNC_8_ = node,-,-,A,10;
CLK_000_N_SYNC_9_ = node,-,-,A,6;
CLK_000_N_SYNC_10_ = node,-,-,H,2;
SM_AMIGA_6_ = node,-,-,F,4;
inst_CLK_030_H = node,-,-,A,2;
SM_AMIGA_1_ = node,-,-,F,5;
SM_AMIGA_3_ = node,-,-,F,6;
SM_AMIGA_2_ = node,-,-,F,10;
CLK_000_P_SYNC_6_ = node,-,-,G,10;
CLK_000_P_SYNC_7_ = node,-,-,D,3;
CLK_000_P_SYNC_8_ = node,-,-,A,7;
CLK_000_P_SYNC_9_ = node,-,-,C,3;
CLK_000_N_SYNC_1_ = node,-,-,E,9;
CLK_000_N_SYNC_2_ = node,-,-,A,3;
CLK_000_N_SYNC_3_ = node,-,-,F,7;
CLK_000_N_SYNC_4_ = node,-,-,A,14;
CLK_000_N_SYNC_5_ = node,-,-,A,6;
CLK_000_N_SYNC_6_ = node,-,-,B,3;
CLK_000_N_SYNC_7_ = node,-,-,G,6;
CLK_000_N_SYNC_8_ = node,-,-,B,14;
CLK_000_N_SYNC_9_ = node,-,-,F,3;
CLK_000_N_SYNC_10_ = node,-,-,C,14;
CLK_000_N_SYNC_11_ = node,-,-,C,10;
inst_CLK_000_NE_D0 = node,-,-,E,5;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,2;
SM_AMIGA_6_ = node,-,-,C,9;
inst_CLK_030_H = node,-,-,A,13;
SM_AMIGA_1_ = node,-,-,F,13;
SM_AMIGA_3_ = node,-,-,F,2;
SM_AMIGA_2_ = node,-,-,F,6;
SM_AMIGA_i_7_ = node,-,-,F,0;
CIIN_0 = node,-,-,E,5;
CIIN_0 = node,-,-,E,10;
[GROUP ASSIGNMENTS]
Layer = OFF;

8674
Logic/68030_tk.out
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216
Logic/68030_tk.plc
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@ -8,155 +8,173 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Wed Aug 17 17:45:51 2016
; DATE Fri Aug 19 00:20:46 2016
Pin 84 A_DECODE_22_
Pin 94 A_DECODE_21_
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
Pin 4 A_31_
Pin 93 A_DECODE_20_
Pin 97 A_DECODE_19_
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143
Pin 95 A_DECODE_18_
Pin 59 A_DECODE_17_
Pin 85 A_DECODE_23_
Pin 96 A_DECODE_16_
Pin 68 IPL_2_
Pin 56 IPL_1_
Pin 58 FC_1_
Pin 67 IPL_0_
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
Pin 57 FC_0_
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
Pin 60 A1
Pin 14 nEXP_SPACE
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
Pin 21 BG_030
Pin 56 IPL_1_
Pin 67 IPL_0_
Pin 28 BGACK_000
Pin 57 FC_0_
Pin 64 CLK_030
Pin 60 A_1_
Pin 11 CLK_000
Pin 61 CLK_OSZI
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 275
Pin 91 FPU_SENSE
Pin 30 DTACK
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
Pin 66 E Comb ; S6=1 S9=1 Pair 251
Pin 36 VPA
Pin 86 RST
Pin 3 RESET Comb ; S6=1 S9=1 Pair 127
Pin 3 RESET Comb ; S6=1 S9=1 Pair 133
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
Pin 5 A_30_
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
Pin 6 A_29_
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
Pin 15 A_28_
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
Pin 16 A_27_
Pin 17 A_26_
Pin 18 A_25_
Pin 19 A_24_
Pin 85 A_23_
Pin 84 A_22_
Pin 94 A_21_
Pin 93 A_20_
Pin 97 A_19_
Pin 95 A_18_
Pin 59 A_17_
Pin 96 A_16_
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 145
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 155
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 157
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
Pin 69 A0 Reg ; S6=1 S9=1 Pair 257
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 125
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 278
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283
Pin 35 VMA Reg ; S6=1 S9=1 Pair 173
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1
Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1
Node 281 RN_AS_030 Comb ; S6=1 S9=1
Node 203 RN_AS_000 Comb ; S6=1 S9=1
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
Node 197 RN_BERR Comb ; S6=1 S9=1
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1
Node 145 RN_AHIGH_29_ Comb ; S6=1 S9=1
Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1
Node 155 RN_AHIGH_27_ Comb ; S6=1 S9=1
Node 157 RN_AHIGH_26_ Comb ; S6=1 S9=1
Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1
Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1
Node 269 RN_RW_000 Reg ; S6=1 S9=1
Node 257 RN_A0 Reg ; S6=1 S9=1
Node 257 RN_A_0_ Reg ; S6=1 S9=1
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1
Node 175 RN_BG_000 Reg ; S6=1 S9=1
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
Node 278 RN_BGACK_030 Reg ; S6=1 S9=1
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
Node 173 RN_VMA Reg ; S6=1 S9=1
Node 245 RN_RW Reg ; S6=1 S9=1
Node 242 N_317_i Comb ; S6=1 S9=1
Node 193 cpu_est_2_ Reg ; S6=1 S9=1
Node 239 cpu_est_3_ Reg ; S6=1 S9=1
Node 182 cpu_est_0_ Reg ; S6=1 S9=1
Node 176 cpu_est_1_ Reg ; S6=1 S9=1
Node 151 inst_AS_000_INT Reg ; S6=1 S9=1
Node 233 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 128 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 274 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 113 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1
Node 155 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 242 N_226 Comb ; S6=1 S9=1
Node 227 cpu_est_2_ Reg ; S6=1 S9=1
Node 223 cpu_est_3_ Reg ; S6=1 S9=1
Node 128 cpu_est_0_ Reg ; S6=1 S9=1
Node 239 cpu_est_1_ Reg ; S6=1 S9=1
Node 248 inst_AS_000_INT Reg ; S6=1 S9=1
Node 140 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 271 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 169 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 103 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 133 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 167 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 265 SIZE_DMA_0_ Reg ; S6=1 S9=1
Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1
Node 224 inst_VPA_D Reg ; S6=1 S9=1
Node 115 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 109 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 119 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 148 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 119 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 115 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 116 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 104 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 259 SIZE_DMA_0_ Reg ; S6=1 S9=1
Node 253 SIZE_DMA_1_ Reg ; S6=1 S9=1
Node 109 inst_VPA_D Reg ; S6=1 S9=1
Node 134 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 103 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 268 CLK_000_D_10_ Reg ; S6=1 S9=1
Node 284 CLK_000_D_11_ Reg ; S6=1 S9=1
Node 172 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 187 inst_RESET_OUT Reg ; S6=1 S9=1
Node 241 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 209 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 139 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 253 inst_CLK_000_PE Reg ; S6=1 S9=1
Node 268 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
Node 248 inst_CLK_000_NE Reg ; S6=1 S9=1
Node 278 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
Node 262 IPL_D0_0_ Reg ; S6=1 S9=1
Node 196 IPL_D0_1_ Reg ; S6=1 S9=1
Node 142 IPL_D0_2_ Reg ; S6=1 S9=1
Node 188 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
Node 223 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 145 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
Node 235 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 161 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 178 RST_DLY_0_ Reg ; S6=1 S9=1
Node 194 RST_DLY_1_ Reg ; S6=1 S9=1
Node 184 RST_DLY_2_ Reg ; S6=1 S9=1
Node 200 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
Node 136 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
Node 256 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
Node 217 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
Node 250 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
Node 200 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 158 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 265 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 113 CLK_000_P_SYNC_10_ Reg ; S6=1 S9=1
Node 233 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 196 IPL_D0_0_ Reg ; S6=1 S9=1
Node 244 IPL_D0_1_ Reg ; S6=1 S9=1
Node 148 IPL_D0_2_ Reg ; S6=1 S9=1
Node 262 CLK_000_D_2_ Reg ; S6=1 S9=1
Node 256 CLK_000_D_3_ Reg ; S6=1 S9=1
Node 166 CLK_000_D_4_ Reg ; S6=1 S9=1
Node 217 CLK_000_D_5_ Reg ; S6=1 S9=1
Node 142 CLK_000_D_6_ Reg ; S6=1 S9=1
Node 250 CLK_000_D_7_ Reg ; S6=1 S9=1
Node 136 CLK_000_D_8_ Reg ; S6=1 S9=1
Node 190 CLK_000_D_9_ Reg ; S6=1 S9=1
Node 272 CLK_000_D_12_ Reg ; S6=1 S9=1
Node 229 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 176 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
Node 236 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 235 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 193 CLK_000_N_SYNC_12_ Reg ; S6=1 S9=1
Node 188 RST_DLY_0_ Reg ; S6=1 S9=1
Node 182 RST_DLY_1_ Reg ; S6=1 S9=1
Node 194 RST_DLY_2_ Reg ; S6=1 S9=1
Node 184 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
Node 124 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
Node 238 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
Node 160 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
Node 118 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
Node 266 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
Node 106 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
Node 130 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
Node 260 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
Node 211 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
Node 122 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
Node 146 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
Node 140 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
Node 134 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
Node 190 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
Node 254 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
Node 226 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
Node 116 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
Node 110 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
Node 227 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 104 inst_CLK_030_H Reg ; S6=1 S9=1
Node 229 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 230 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 236 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 260 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
Node 178 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
Node 112 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
Node 154 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
Node 211 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
Node 106 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
Node 232 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
Node 122 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
Node 110 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
Node 130 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
Node 254 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
Node 146 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
Node 226 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
Node 170 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
Node 164 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
Node 205 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
Node 152 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
Node 163 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 121 inst_CLK_030_H Reg ; S6=1 S9=1
Node 241 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 224 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 221 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
Node 205 CIIN_0 Comb ; S6=1 S9=1
Node 212 CIIN_0 Comb ; S6=1 S9=1
; Unused Pins & Nodes
; -> None Found.

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Logic/68030_tk.tal
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@ -39,9 +39,7 @@ SIGNAL NAME min max min max min max min max
AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. ..
BGACK_030 1 2 0 1 .. .. 1 1
RN_BGACK_030 1 2 0 1 .. .. 1 1
SM_AMIGA_5_ 1 1 .. .. .. .. 1 2
inst_AS_030_D0 1 2 1 1 .. .. 1 1
inst_nEXP_SPACE_D0reg 1 1 1 1 .. .. 1 2
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
inst_DS_000_DMA 1 2 1 1 .. .. .. ..
CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1
@ -50,9 +48,9 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
SIZE_DMA_1_ 1 1 1 1 .. .. 2 2
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
CLK_000_D_1_ .. .. .. .. .. .. 1 2
CLK_000_D_0_ 1 1 .. .. .. .. 1 2
SM_AMIGA_0_ 1 1 .. .. .. .. 1 2
SM_AMIGA_5_ 1 1 .. .. .. .. 1 2
SM_AMIGA_0_ 1 1 1 1 .. .. 1 2
CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 2
SM_AMIGA_4_ 1 1 .. .. .. .. 1 2
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
SM_AMIGA_6_ 1 1 .. .. .. .. 1 2
@ -60,19 +58,21 @@ inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
SM_AMIGA_1_ 1 1 .. .. .. .. 1 2
SM_AMIGA_3_ 1 1 .. .. .. .. 1 2
SM_AMIGA_2_ 1 1 .. .. .. .. 1 2
SM_AMIGA_i_7_ 1 2 1 1 .. .. 1 1
AS_030 .. .. .. .. 1 1 .. ..
AS_000 .. .. .. .. 1 1 .. ..
AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 1 .. ..
CIIN .. .. .. .. 1 1 .. ..
IPL_030_2_ 1 1 0 0 .. .. 1 1
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
RW_000 1 1 0 0 .. .. 1 1
RN_RW_000 1 1 0 0 .. .. 1 1
A_0_ 1 1 0 0 .. .. 1 1
RN_A_0_ 1 1 0 0 .. .. 1 1
IPL_030_1_ 1 1 0 0 .. .. 1 1
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
IPL_030_0_ 1 1 0 0 .. .. 1 1
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
RW_000 1 1 0 0 .. .. 1 1
RN_RW_000 1 1 0 0 .. .. 1 1
A0 1 1 0 0 .. .. 1 1
RN_A0 1 1 0 0 .. .. 1 1
BG_000 1 1 0 0 .. .. 1 1
RN_BG_000 1 1 0 0 .. .. 1 1
DSACK1 1 1 0 0 .. .. 1 1
@ -81,6 +81,7 @@ inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
RN_VMA 1 1 0 0 .. .. 1 1
RW 1 1 0 0 .. .. 1 1
RN_RW 1 1 0 0 .. .. 1 1
N_226 .. .. .. .. 1 1 .. ..
cpu_est_2_ .. .. 1 1 .. .. 1 1
cpu_est_3_ .. .. 1 1 .. .. 1 1
cpu_est_0_ .. .. .. .. .. .. 1 1
@ -89,18 +90,27 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. ..
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
inst_VPA_D 1 1 .. .. .. .. 1 1
inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
CLK_000_D_10_ .. .. .. .. .. .. 1 1
CLK_000_D_11_ .. .. .. .. .. .. 1 1
inst_DTACK_D0 1 1 .. .. .. .. 1 1
inst_RESET_OUT 1 1 .. .. .. .. .. ..
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
inst_CLK_000_PE .. .. .. .. .. .. 1 1
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
inst_CLK_000_NE .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
CLK_000_D_1_ .. .. .. .. .. .. 1 1
CLK_000_D_0_ 1 1 .. .. .. .. 1 1
CLK_000_P_SYNC_10_ .. .. .. .. .. .. 1 1
IPL_D0_0_ 1 1 .. .. .. .. 1 1
IPL_D0_1_ 1 1 .. .. .. .. 1 1
IPL_D0_2_ 1 1 .. .. .. .. 1 1
inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
CLK_000_D_2_ .. .. .. .. .. .. 1 1
CLK_000_D_3_ .. .. .. .. .. .. 1 1
CLK_000_D_4_ .. .. .. .. .. .. 1 1
CLK_000_D_5_ .. .. .. .. .. .. 1 1
CLK_000_D_6_ .. .. .. .. .. .. 1 1
CLK_000_D_7_ .. .. .. .. .. .. 1 1
CLK_000_D_8_ .. .. .. .. .. .. 1 1
CLK_000_D_9_ .. .. .. .. .. .. 1 1
CLK_000_D_12_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_12_ .. .. .. .. .. .. 1 1
RST_DLY_0_ 1 1 .. .. .. .. 1 1
RST_DLY_1_ 1 1 .. .. .. .. 1 1
RST_DLY_2_ 1 1 .. .. .. .. 1 1
@ -113,7 +123,7 @@ CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1
CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1
CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1
CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1
@ -124,5 +134,7 @@ CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1
CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1
SM_AMIGA_i_7_ 1 1 1 1 .. .. 1 1
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
CIIN_0 .. .. .. .. 1 1 .. ..

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606
Logic/68030_tk.tt4
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@ -1,314 +1,338 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ DATE Fri Aug 19 00:20:41 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_
AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_
A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000
BGACK_030 CLK_EXP DSACK1 VMA RW
#$ NODES 69 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_
inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_
inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_
CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_
inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_
AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_
AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_
BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK
AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW
AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_
AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_
BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW
#$ NODES 79 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT
inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT
inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_
IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_
CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_
SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_
RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_
CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_
CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_
CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_
CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_
CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0
inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_
SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 121
.o 191
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q
N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q
SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q
inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q
CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q
CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q
CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q
CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q
RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
A0.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE
UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C
FPU_CS% AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE SIZE_0_ SIZE_0_.OE
.i 131
.o 227
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q
inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q
SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q
CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q
CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q
RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q
CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q
CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q
CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q
CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q
CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q
inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q
inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q
BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN
UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN
AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN
AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000%
AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE
CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE
IPL_030_2_.D% IPL_030_2_.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C
RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D
BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D%
RW.C RW.OE N_317_i% cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_AS_000_INT.D%
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D%
SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_
AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D%
RW_000.C RW_000.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D%
IPL_030_0_.C BG_000.D% BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C
DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE N_226 cpu_est_2_.D
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D
cpu_est_1_.C inst_AS_000_INT.D% inst_AS_000_INT.C
inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C
inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_000_SYNC.D%
inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C
inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C
CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D%
SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C
inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_10_.D CLK_000_D_10_.C
CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D% inst_DTACK_D0.C
inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D
inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D
inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D%
IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C
inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D
SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_P_SYNC_10_.D
CLK_000_P_SYNC_10_.C SM_AMIGA_5_.D SM_AMIGA_5_.C IPL_D0_0_.D% IPL_D0_0_.C
IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D
CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C
CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D
CLK_000_D_12_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CLK_000_N_SYNC_0_.D
CLK_000_N_SYNC_0_.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D
inst_DS_000_ENABLE.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C RST_DLY_0_.D
RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C
CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C
CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C
CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C
CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C
CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C
CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D
CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D
CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C
inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D
inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T SM_AMIGA_3_.C
SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0
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.p 221
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.end

606
Logic/68030_tk.tte
View File

@ -1,314 +1,338 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ DATE Fri Aug 19 00:20:41 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_
AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_
A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000
BGACK_030 CLK_EXP DSACK1 VMA RW
#$ NODES 69 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_
inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_
inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_
CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_
inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_
AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_
AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_
BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK
AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW
AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_
AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_
BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW
#$ NODES 79 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT
inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT
inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_
IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_
CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_
SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_
RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_
CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_
CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_
CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_
CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_
CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0
inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_
SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 121
.o 191
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q
N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q
SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q
inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q
CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q
CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q
CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q
CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q
RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
A0.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE
UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C
FPU_CS- AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE SIZE_0_ SIZE_0_.OE
.i 131
.o 227
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q
inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q
SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q
CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q
CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q
RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q
CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q
CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q
CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q
CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q
CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q
inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q
inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q
BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN
UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN
AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN
AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000-
AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE
CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE
IPL_030_2_.D- IPL_030_2_.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C
RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D
BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D-
RW.C RW.OE N_317_i- cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_AS_000_INT.D-
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D-
SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_
AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D-
RW_000.C RW_000.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D-
IPL_030_0_.C BG_000.D- BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C
DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE N_226 cpu_est_2_.D
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D
cpu_est_1_.C inst_AS_000_INT.D- inst_AS_000_INT.C
inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C
inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D-
inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C
inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C
CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D-
SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C
inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_10_.D CLK_000_D_10_.C
CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D- inst_DTACK_D0.C
inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D
inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D
inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D-
IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C
inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D
SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_P_SYNC_10_.D
CLK_000_P_SYNC_10_.C SM_AMIGA_5_.D SM_AMIGA_5_.C IPL_D0_0_.D- IPL_D0_0_.C
IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D
CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C
CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D
CLK_000_D_12_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CLK_000_N_SYNC_0_.D
CLK_000_N_SYNC_0_.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D
inst_DS_000_ENABLE.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C RST_DLY_0_.D
RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C
CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C
CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C
CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C
CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C
CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C
CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D
CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D
CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C
inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D
inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T SM_AMIGA_3_.C
SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 221
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.p 231
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.end

124
Logic/68030_tk.vcl
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/17/16;
TIME = 17:45:51;
DATE = 8/19/16;
TIME = 00:20:46;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -136,25 +136,33 @@ layer = OFF;
[LOCATION ASSIGNMENT]
Layer = OFF
AS_000 = OUTPUT,42,4,-;
RW_000 = BIDIR,80,7,-;
BERR = OUTPUT,41,4,-;
RW_000 = BIDIR,80,7,-;
AS_000 = OUTPUT,42,4,-;
A_0_ = BIDIR,69,6,-;
RW = BIDIR,71,6,-;
AS_030 = OUTPUT,82,7,-;
UDS_000 = OUTPUT,32,3,-;
LDS_000 = OUTPUT,31,3,-;
A0 = BIDIR,69,6,-;
SIZE_1_ = OUTPUT,79,7,-;
SIZE_0_ = OUTPUT,70,6,-;
AHIGH_24_ = OUTPUT,19,2,-;
AHIGH_25_ = OUTPUT,18,2,-;
AHIGH_26_ = OUTPUT,17,2,-;
AHIGH_27_ = OUTPUT,16,2,-;
AHIGH_28_ = OUTPUT,15,2,-;
AHIGH_29_ = OUTPUT,6,1,-;
AHIGH_30_ = OUTPUT,5,1,-;
AHIGH_31_ = OUTPUT,4,1,-;
IPL_030_2_ = OUTPUT,9,1,-;
IPL_030_0_ = OUTPUT,8,1,-;
IPL_030_1_ = OUTPUT,7,1,-;
DSACK1 = OUTPUT,81,7,-;
BGACK_030 = OUTPUT,83,7,-;
VMA = OUTPUT,35,3,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-;
E = OUTPUT,66,6,-;
AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-;
BG_000 = OUTPUT,29,3,-;
DS_030 = OUTPUT,98,0,-;
AVEC = OUTPUT,92,0,-;
@ -166,41 +174,37 @@ AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
CLK_EXP = OUTPUT,10,1,-;
RESET = OUTPUT,3,1,-;
RN_BGACK_030 = NODE,-1,7,-;
inst_nEXP_SPACE_D0reg = NODE,*,0,-;
inst_RESET_OUT = NODE,*,3,-;
inst_CLK_000_PE = NODE,*,6,-;
SM_AMIGA_i_7_ = NODE,*,5,-;
inst_AS_030_D0 = NODE,*,7,-;
cpu_est_2_ = NODE,*,3,-;
SM_AMIGA_6_ = NODE,*,5,-;
CLK_000_P_SYNC_10_ = NODE,*,0,-;
SM_AMIGA_i_7_ = NODE,*,5,-;
SM_AMIGA_6_ = NODE,*,2,-;
cpu_est_2_ = NODE,*,5,-;
SM_AMIGA_5_ = NODE,*,5,-;
cpu_est_1_ = NODE,*,3,-;
cpu_est_1_ = NODE,*,5,-;
cpu_est_3_ = NODE,*,5,-;
SM_AMIGA_0_ = NODE,*,5,-;
CYCLE_DMA_0_ = NODE,*,1,-;
CLK_000_D_0_ = NODE,*,1,-;
inst_CLK_OUT_PRE_D = NODE,*,0,-;
cpu_est_0_ = NODE,*,1,-;
CLK_000_N_SYNC_12_ = NODE,*,3,-;
CLK_000_N_SYNC_0_ = NODE,*,3,-;
inst_CLK_OUT_PRE_D = NODE,*,4,-;
inst_BGACK_030_INT_D = NODE,*,7,-;
inst_AS_000_DMA = NODE,*,0,-;
inst_AS_030_000_SYNC = NODE,*,2,-;
inst_DS_000_ENABLE = NODE,*,2,-;
inst_DS_000_ENABLE = NODE,*,5,-;
RN_VMA = NODE,-1,3,-;
SM_AMIGA_1_ = NODE,*,5,-;
SM_AMIGA_4_ = NODE,*,5,-;
inst_LDS_000_INT = NODE,*,0,-;
SIZE_DMA_1_ = NODE,*,6,-;
SIZE_DMA_0_ = NODE,*,6,-;
CYCLE_DMA_1_ = NODE,*,2,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,1,-;
inst_UDS_000_INT = NODE,*,0,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-;
inst_UDS_000_INT = NODE,*,1,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,1,-;
inst_AS_000_INT = NODE,*,2,-;
cpu_est_0_ = NODE,*,3,-;
inst_CLK_000_NE_D0 = NODE,*,3,-;
inst_CLK_000_NE = NODE,*,6,-;
CLK_000_D_1_ = NODE,*,4,-;
inst_CLK_OUT_PRE_50 = NODE,*,5,-;
inst_VPA_D = NODE,*,5,-;
inst_AS_000_INT = NODE,*,6,-;
inst_CLK_000_NE_D0 = NODE,*,4,-;
CLK_000_D_0_ = NODE,*,6,-;
CLK_000_D_1_ = NODE,*,2,-;
inst_VPA_D = NODE,*,0,-;
RN_IPL_030_0_ = NODE,-1,1,-;
RN_IPL_030_1_ = NODE,-1,1,-;
RN_IPL_030_2_ = NODE,-1,1,-;
@ -210,38 +214,52 @@ SM_AMIGA_3_ = NODE,*,5,-;
RN_DSACK1 = NODE,-1,7,-;
SM_AMIGA_2_ = NODE,*,5,-;
RST_DLY_1_ = NODE,*,3,-;
N_317_i = NODE,*,5,-;
RN_A0 = NODE,-1,6,-;
RN_A_0_ = NODE,-1,6,-;
RN_RW_000 = NODE,-1,7,-;
RST_DLY_0_ = NODE,*,3,-;
SM_AMIGA_4_ = NODE,*,5,-;
CYCLE_DMA_1_ = NODE,*,0,-;
N_226 = NODE,*,5,-;
RN_RW = NODE,-1,6,-;
RN_BG_000 = NODE,-1,3,-;
CIIN_0 = NODE,*,4,-;
RST_DLY_2_ = NODE,*,3,-;
CLK_000_N_SYNC_10_ = NODE,*,7,-;
CLK_000_N_SYNC_9_ = NODE,*,0,-;
CLK_000_N_SYNC_8_ = NODE,*,0,-;
CLK_000_N_SYNC_7_ = NODE,*,5,-;
CLK_000_N_SYNC_6_ = NODE,*,6,-;
CLK_000_N_SYNC_5_ = NODE,*,3,-;
CLK_000_N_SYNC_4_ = NODE,*,1,-;
CLK_000_N_SYNC_3_ = NODE,*,1,-;
CLK_000_N_SYNC_2_ = NODE,*,1,-;
CLK_000_N_SYNC_1_ = NODE,*,0,-;
CLK_000_N_SYNC_0_ = NODE,*,4,-;
CLK_000_P_SYNC_8_ = NODE,*,6,-;
CLK_000_P_SYNC_7_ = NODE,*,1,-;
CLK_000_P_SYNC_6_ = NODE,*,0,-;
CYCLE_DMA_0_ = NODE,*,0,-;
CLK_000_N_SYNC_11_ = NODE,*,2,-;
CLK_000_N_SYNC_10_ = NODE,*,2,-;
CLK_000_N_SYNC_9_ = NODE,*,5,-;
CLK_000_N_SYNC_8_ = NODE,*,1,-;
CLK_000_N_SYNC_7_ = NODE,*,6,-;
CLK_000_N_SYNC_6_ = NODE,*,1,-;
CLK_000_N_SYNC_5_ = NODE,*,0,-;
CLK_000_N_SYNC_4_ = NODE,*,0,-;
CLK_000_N_SYNC_3_ = NODE,*,5,-;
CLK_000_N_SYNC_2_ = NODE,*,0,-;
CLK_000_N_SYNC_1_ = NODE,*,4,-;
CLK_000_P_SYNC_9_ = NODE,*,2,-;
CLK_000_P_SYNC_8_ = NODE,*,0,-;
CLK_000_P_SYNC_7_ = NODE,*,3,-;
CLK_000_P_SYNC_6_ = NODE,*,6,-;
CLK_000_P_SYNC_5_ = NODE,*,6,-;
CLK_000_P_SYNC_4_ = NODE,*,6,-;
CLK_000_P_SYNC_3_ = NODE,*,4,-;
CLK_000_P_SYNC_2_ = NODE,*,6,-;
CLK_000_P_SYNC_1_ = NODE,*,1,-;
CLK_000_P_SYNC_0_ = NODE,*,4,-;
CLK_000_P_SYNC_4_ = NODE,*,0,-;
CLK_000_P_SYNC_3_ = NODE,*,2,-;
CLK_000_P_SYNC_2_ = NODE,*,5,-;
CLK_000_P_SYNC_1_ = NODE,*,0,-;
CLK_000_P_SYNC_0_ = NODE,*,3,-;
CLK_000_D_12_ = NODE,*,7,-;
CLK_000_D_9_ = NODE,*,3,-;
CLK_000_D_8_ = NODE,*,1,-;
CLK_000_D_7_ = NODE,*,6,-;
CLK_000_D_6_ = NODE,*,1,-;
CLK_000_D_5_ = NODE,*,4,-;
CLK_000_D_4_ = NODE,*,2,-;
CLK_000_D_3_ = NODE,*,6,-;
CLK_000_D_2_ = NODE,*,6,-;
IPL_D0_2_ = NODE,*,1,-;
IPL_D0_1_ = NODE,*,3,-;
IPL_D0_0_ = NODE,*,6,-;
CLK_000_N_SYNC_11_ = NODE,*,7,-;
CLK_000_P_SYNC_9_ = NODE,*,6,-;
inst_DTACK_D0 = NODE,*,1,-;
IPL_D0_1_ = NODE,*,5,-;
IPL_D0_0_ = NODE,*,3,-;
inst_CLK_OUT_PRE_50 = NODE,*,4,-;
inst_DTACK_D0 = NODE,*,2,-;
CLK_000_D_11_ = NODE,*,7,-;
CLK_000_D_10_ = NODE,*,6,-;
CLK_OSZI = INPUT,61,-,-;

190
Logic/68030_tk.vco
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/17/16;
TIME = 17:45:51;
DATE = 8/19/16;
TIME = 00:20:46;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -136,24 +136,32 @@ layer = OFF;
[LOCATION ASSIGNMENT]
Layer = OFF;
A_DECODE_22_ = INPUT,84, H,-;
A_DECODE_21_ = INPUT,94, A,-;
SIZE_1_ = BIDIR,79, H,-;
A_31_ = INPUT,4, B,-;
A_DECODE_20_ = INPUT,93, A,-;
A_DECODE_19_ = INPUT,97, A,-;
AHIGH_31_ = BIDIR,4, B,-;
A_DECODE_18_ = INPUT,95, A,-;
A_DECODE_17_ = INPUT,59, F,-;
A_DECODE_23_ = INPUT,85, H,-;
A_DECODE_16_ = INPUT,96, A,-;
IPL_2_ = INPUT,68, G,-;
IPL_1_ = INPUT,56, F,-;
FC_1_ = INPUT,58, F,-;
IPL_0_ = INPUT,67, G,-;
AS_030 = BIDIR,82, H,-;
FC_0_ = INPUT,57, F,-;
AS_000 = BIDIR,42, E,-;
DS_030 = OUTPUT,98, A,-;
UDS_000 = BIDIR,32, D,-;
LDS_000 = BIDIR,31, D,-;
A1 = INPUT,60, F,-;
nEXP_SPACE = INPUT,14,-,-;
BERR = BIDIR,41, E,-;
BG_030 = INPUT,21, C,-;
IPL_1_ = INPUT,56, F,-;
IPL_0_ = INPUT,67, G,-;
BGACK_000 = INPUT,28, D,-;
FC_0_ = INPUT,57, F,-;
CLK_030 = INPUT,64,-,-;
A_1_ = INPUT,60, F,-;
CLK_000 = INPUT,11,-,-;
CLK_OSZI = INPUT,61,-,-;
CLK_DIV_OUT = OUTPUT,65, G,-;
@ -166,103 +174,105 @@ VPA = INPUT,36,-,-;
RST = INPUT,86,-,-;
RESET = OUTPUT,3, B,-;
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
SIZE_0_ = BIDIR,70, G,-;
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
A_30_ = INPUT,5, B,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
A_29_ = INPUT,6, B,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
A_28_ = INPUT,15, C,-;
CIIN = OUTPUT,47, E,-;
A_27_ = INPUT,16, C,-;
A_26_ = INPUT,17, C,-;
A_25_ = INPUT,18, C,-;
A_24_ = INPUT,19, C,-;
A_23_ = INPUT,85, H,-;
A_22_ = INPUT,84, H,-;
A_21_ = INPUT,94, A,-;
A_20_ = INPUT,93, A,-;
A_19_ = INPUT,97, A,-;
A_18_ = INPUT,95, A,-;
A_17_ = INPUT,59, F,-;
A_16_ = INPUT,96, A,-;
SIZE_0_ = BIDIR,70, G,-;
AHIGH_30_ = BIDIR,5, B,-;
AHIGH_29_ = BIDIR,6, B,-;
AHIGH_28_ = BIDIR,15, C,-;
AHIGH_27_ = BIDIR,16, C,-;
AHIGH_26_ = BIDIR,17, C,-;
AHIGH_25_ = BIDIR,18, C,-;
AHIGH_24_ = BIDIR,19, C,-;
IPL_030_2_ = OUTPUT,9, B,-;
RW_000 = BIDIR,80, H,-;
A_0_ = BIDIR,69, G,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
RW_000 = BIDIR,80, H,-;
A0 = BIDIR,69, G,-;
BG_000 = OUTPUT,29, D,-;
BGACK_030 = OUTPUT,83, H,-;
CLK_EXP = OUTPUT,10, B,-;
DSACK1 = OUTPUT,81, H,-;
VMA = OUTPUT,35, D,-;
RW = BIDIR,71, G,-;
N_317_i = NODE,14, F,-;
cpu_est_2_ = NODE,13, D,-;
cpu_est_3_ = NODE,12, F,-;
cpu_est_0_ = NODE,6, D,-;
cpu_est_1_ = NODE,2, D,-;
inst_AS_000_INT = NODE,1, C,-;
SM_AMIGA_5_ = NODE,8, F,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,2, B,-;
inst_AS_030_D0 = NODE,3, H,-;
inst_nEXP_SPACE_D0reg = NODE,8, A,-;
inst_AS_030_000_SYNC = NODE,4, C,-;
N_226 = NODE,14, F,-;
cpu_est_2_ = NODE,4, F,-;
cpu_est_3_ = NODE,1, F,-;
cpu_est_0_ = NODE,2, B,-;
cpu_est_1_ = NODE,12, F,-;
inst_AS_000_INT = NODE,2, G,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, B,-;
inst_AS_030_D0 = NODE,1, H,-;
inst_AS_030_000_SYNC = NODE,13, C,-;
inst_BGACK_030_INT_D = NODE,13, H,-;
inst_AS_000_DMA = NODE,1, A,-;
inst_DS_000_DMA = NODE,13, A,-;
CYCLE_DMA_0_ = NODE,5, B,-;
CYCLE_DMA_1_ = NODE,12, C,-;
SIZE_DMA_0_ = NODE,13, G,-;
SIZE_DMA_1_ = NODE,9, G,-;
inst_VPA_D = NODE,2, F,-;
inst_UDS_000_INT = NODE,9, A,-;
inst_LDS_000_INT = NODE,5, A,-;
inst_CLK_OUT_PRE_D = NODE,12, A,-;
inst_DTACK_D0 = NODE,15, B,-;
inst_AS_000_DMA = NODE,12, A,-;
inst_DS_000_DMA = NODE,9, A,-;
CYCLE_DMA_0_ = NODE,10, A,-;
CYCLE_DMA_1_ = NODE,2, A,-;
SIZE_DMA_0_ = NODE,9, G,-;
SIZE_DMA_1_ = NODE,5, G,-;
inst_VPA_D = NODE,5, A,-;
inst_UDS_000_INT = NODE,6, B,-;
inst_LDS_000_INT = NODE,1, A,-;
inst_CLK_OUT_PRE_D = NODE,8, E,-;
CLK_000_D_10_ = NODE,15, G,-;
CLK_000_D_11_ = NODE,10, H,-;
inst_DTACK_D0 = NODE,15, C,-;
inst_RESET_OUT = NODE,9, D,-;
inst_CLK_OUT_PRE_50 = NODE,13, F,-;
CLK_000_D_1_ = NODE,8, E,-;
CLK_000_D_0_ = NODE,9, B,-;
inst_CLK_000_PE = NODE,5, G,-;
CLK_000_P_SYNC_9_ = NODE,15, G,-;
inst_CLK_000_NE = NODE,2, G,-;
CLK_000_N_SYNC_11_ = NODE,6, H,-;
IPL_D0_0_ = NODE,11, G,-;
IPL_D0_1_ = NODE,15, D,-;
IPL_D0_2_ = NODE,11, B,-;
inst_CLK_000_NE_D0 = NODE,10, D,-;
SM_AMIGA_0_ = NODE,1, F,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,13, B,-;
SM_AMIGA_4_ = NODE,9, F,-;
inst_DS_000_ENABLE = NODE,8, C,-;
RST_DLY_0_ = NODE,3, D,-;
RST_DLY_1_ = NODE,14, D,-;
RST_DLY_2_ = NODE,7, D,-;
CLK_000_P_SYNC_0_ = NODE,2, E,-;
CLK_000_P_SYNC_1_ = NODE,7, B,-;
CLK_000_P_SYNC_2_ = NODE,7, G,-;
CLK_000_P_SYNC_3_ = NODE,13, E,-;
CLK_000_P_SYNC_4_ = NODE,3, G,-;
inst_CLK_OUT_PRE_50 = NODE,2, E,-;
CLK_000_D_1_ = NODE,6, C,-;
CLK_000_D_0_ = NODE,13, G,-;
CLK_000_P_SYNC_10_ = NODE,8, A,-;
SM_AMIGA_5_ = NODE,8, F,-;
IPL_D0_0_ = NODE,15, D,-;
IPL_D0_1_ = NODE,15, F,-;
IPL_D0_2_ = NODE,15, B,-;
CLK_000_D_2_ = NODE,11, G,-;
CLK_000_D_3_ = NODE,7, G,-;
CLK_000_D_4_ = NODE,11, C,-;
CLK_000_D_5_ = NODE,13, E,-;
CLK_000_D_6_ = NODE,11, B,-;
CLK_000_D_7_ = NODE,3, G,-;
CLK_000_D_8_ = NODE,7, B,-;
CLK_000_D_9_ = NODE,11, D,-;
CLK_000_D_12_ = NODE,2, H,-;
SM_AMIGA_0_ = NODE,5, F,-;
CLK_000_N_SYNC_0_ = NODE,2, D,-;
SM_AMIGA_4_ = NODE,10, F,-;
inst_DS_000_ENABLE = NODE,9, F,-;
CLK_000_N_SYNC_12_ = NODE,13, D,-;
RST_DLY_0_ = NODE,10, D,-;
RST_DLY_1_ = NODE,6, D,-;
RST_DLY_2_ = NODE,14, D,-;
CLK_000_P_SYNC_0_ = NODE,7, D,-;
CLK_000_P_SYNC_1_ = NODE,15, A,-;
CLK_000_P_SYNC_2_ = NODE,11, F,-;
CLK_000_P_SYNC_3_ = NODE,7, C,-;
CLK_000_P_SYNC_4_ = NODE,11, A,-;
CLK_000_P_SYNC_5_ = NODE,14, G,-;
CLK_000_P_SYNC_6_ = NODE,3, A,-;
CLK_000_P_SYNC_7_ = NODE,3, B,-;
CLK_000_P_SYNC_8_ = NODE,10, G,-;
CLK_000_N_SYNC_0_ = NODE,9, E,-;
CLK_000_N_SYNC_1_ = NODE,14, A,-;
CLK_000_N_SYNC_2_ = NODE,14, B,-;
CLK_000_N_SYNC_3_ = NODE,10, B,-;
CLK_000_N_SYNC_4_ = NODE,6, B,-;
CLK_000_N_SYNC_5_ = NODE,11, D,-;
CLK_000_N_SYNC_6_ = NODE,6, G,-;
CLK_000_N_SYNC_7_ = NODE,3, F,-;
CLK_000_N_SYNC_8_ = NODE,10, A,-;
CLK_000_N_SYNC_9_ = NODE,6, A,-;
CLK_000_N_SYNC_10_ = NODE,2, H,-;
SM_AMIGA_6_ = NODE,4, F,-;
inst_CLK_030_H = NODE,2, A,-;
SM_AMIGA_1_ = NODE,5, F,-;
SM_AMIGA_3_ = NODE,6, F,-;
SM_AMIGA_2_ = NODE,10, F,-;
CLK_000_P_SYNC_6_ = NODE,10, G,-;
CLK_000_P_SYNC_7_ = NODE,3, D,-;
CLK_000_P_SYNC_8_ = NODE,7, A,-;
CLK_000_P_SYNC_9_ = NODE,3, C,-;
CLK_000_N_SYNC_1_ = NODE,9, E,-;
CLK_000_N_SYNC_2_ = NODE,3, A,-;
CLK_000_N_SYNC_3_ = NODE,7, F,-;
CLK_000_N_SYNC_4_ = NODE,14, A,-;
CLK_000_N_SYNC_5_ = NODE,6, A,-;
CLK_000_N_SYNC_6_ = NODE,3, B,-;
CLK_000_N_SYNC_7_ = NODE,6, G,-;
CLK_000_N_SYNC_8_ = NODE,14, B,-;
CLK_000_N_SYNC_9_ = NODE,3, F,-;
CLK_000_N_SYNC_10_ = NODE,14, C,-;
CLK_000_N_SYNC_11_ = NODE,10, C,-;
inst_CLK_000_NE_D0 = NODE,5, E,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,2, C,-;
SM_AMIGA_6_ = NODE,9, C,-;
inst_CLK_030_H = NODE,13, A,-;
SM_AMIGA_1_ = NODE,13, F,-;
SM_AMIGA_3_ = NODE,2, F,-;
SM_AMIGA_2_ = NODE,6, F,-;
SM_AMIGA_i_7_ = NODE,0, F,-;
CIIN_0 = NODE,5, E,-;
CIIN_0 = NODE,10, E,-;

22
Logic/68030_tk.vct
View File

@ -15,8 +15,8 @@ Voltage = 5.0;
RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
DATE = 03/16/2015;
TIME = 21:53:52;
DATE = 08/18/2016;
TIME = 23:26:14;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -177,6 +177,24 @@ FPU_SENSE = input,91,A,-;
A1 = input,60,F,-;
A_3_ = input,44,E,-;
A_2_ = input,43,E,-;
AHIGH_24_ = input,19,C,-;
AHIGH_25_ = input,18,C,-;
AHIGH_26_ = input,17,C,-;
AHIGH_27_ = input,16,C,-;
AHIGH_28_ = input,15,C,-;
AHIGH_29_ = input,6,B,-;
AHIGH_30_ = input,5,B,-;
AHIGH_31_ = input,4,B,-;
A_1_ = input,60,F,-;
A_0_ = input,69,G,-;
A_DECODE_16_ = input,96,A,-;
A_DECODE_17_ = input,59,F,-;
A_DECODE_18_ = input,95,A,-;
A_DECODE_19_ = input,97,A,-;
A_DECODE_20_ = input,93,A,-;
A_DECODE_21_ = input,94,A,-;
A_DECODE_22_ = input,84,H,-;
A_DECODE_23_ = input,85,H,-;
[GROUP ASSIGNMENT]
Layer = OFF;

2
Logic/68030_tk.xrf
View File

@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 2.0.00.17.20.15
Design '68030_tk' created Wed Aug 17 17:45:46 2016
Design '68030_tk' created Fri Aug 19 00:20:41 2016
LEGEND: '>' Functional Block Port Separator

3220
Logic/BUS68030.bl0
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3247
Logic/BUS68030.bl1
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5923
Logic/BUS68030.edi
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20
Logic/BUS68030.fse
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@ -1,20 +1,20 @@
fsm_encoding {7134371341} onehot
fsm_encoding {7139371391} onehot
fsm_state_encoding {7134371341} idle_p {00000000}
fsm_state_encoding {7139371391} idle_p {00000000}
fsm_state_encoding {7134371341} idle_n {00000011}
fsm_state_encoding {7139371391} idle_n {00000011}
fsm_state_encoding {7134371341} as_set_p {00000101}
fsm_state_encoding {7139371391} as_set_p {00000101}
fsm_state_encoding {7134371341} as_set_n {00001001}
fsm_state_encoding {7139371391} as_set_n {00001001}
fsm_state_encoding {7134371341} sample_dtack_p {00010001}
fsm_state_encoding {7139371391} sample_dtack_p {00010001}
fsm_state_encoding {7134371341} data_fetch_n {00100001}
fsm_state_encoding {7139371391} data_fetch_n {00100001}
fsm_state_encoding {7134371341} data_fetch_p {01000001}
fsm_state_encoding {7139371391} data_fetch_p {01000001}
fsm_state_encoding {7134371341} end_cycle_n {10000001}
fsm_state_encoding {7139371391} end_cycle_n {10000001}
fsm_registers {7134371341} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
fsm_registers {7139371391} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}

64
Logic/BUS68030.naf
View File

@ -6,38 +6,38 @@ UDS_000 b
LDS_000 b
SIZE[1] b
SIZE[0] b
A[31] i
A[30] i
A[29] i
A[28] i
A[27] i
A[26] i
A[25] i
A[24] i
A[23] i
A[22] i
A[21] i
A[20] i
A[19] i
A[18] i
A[17] i
A[16] i
A[15] i
A[14] i
A[13] i
A[12] i
A[11] i
A[10] i
A[9] i
A[8] i
A[7] i
A[6] i
A[5] i
A[4] i
A[3] i
A[2] i
A0 b
A1 i
AHIGH[31] b
AHIGH[30] b
AHIGH[29] b
AHIGH[28] b
AHIGH[27] b
AHIGH[26] b
AHIGH[25] b
AHIGH[24] b
A_DECODE[23] i
A_DECODE[22] i
A_DECODE[21] i
A_DECODE[20] i
A_DECODE[19] i
A_DECODE[18] i
A_DECODE[17] i
A_DECODE[16] i
A_DECODE[15] i
A_DECODE[14] i
A_DECODE[13] i
A_DECODE[12] i
A_DECODE[11] i
A_DECODE[10] i
A_DECODE[9] i
A_DECODE[8] i
A_DECODE[7] i
A_DECODE[6] i
A_DECODE[5] i
A_DECODE[4] i
A_DECODE[3] i
A_DECODE[2] i
A[1] b
A[0] b
nEXP_SPACE i
BERR b
BG_030 i

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Wed Aug 17 17:45:34 2016
#-- Written on Fri Aug 19 00:20:27 2016
#device options

6493
Logic/BUS68030.srm
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49
Logic/BUS68030.srr
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed Aug 17 17:45:41 2016
#Fri Aug 19 00:20:34 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -18,20 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -42,14 +39,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:41 2016
# Fri Aug 19 00:20:34 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -59,7 +56,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:35 2016
###########################################################]
Map & Optimize Report
@ -68,7 +65,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -83,13 +80,13 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 78 uses
BI_DIR 10 uses
DFF 88 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 46 uses
IBUF 38 uses
OBUF 15 uses
AND2 299 uses
INV 261 uses
AND2 301 uses
INV 262 uses
OR2 27 uses
XOR2 7 uses
@ -101,6 +98,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:36 2016
###########################################################]

BIN
Logic/BUS68030.srs
View File

Binary file not shown.

1308
Logic/bus68030.exf
View File

File diff suppressed because it is too large Load Diff

77
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed Aug 17 17:45:41 2016
#Fri Aug 19 00:20:34 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -18,20 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -42,14 +39,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:41 2016
# Fri Aug 19 00:20:34 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -59,6 +56,48 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:35 2016
###########################################################]
Map & Optimize Report
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
---------------------------------------
Resource Usage Report
Simple gate primitives:
DFF 88 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 301 uses
INV 262 uses
OR2 27 uses
XOR2 7 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:20:36 2016
###########################################################]

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version I-2014.03LC
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Wed Aug 17 17:45:41 2016
#-- Written on Fri Aug 19 00:20:34 2016
#project files

2
Logic/synlog/BUS68030_multi_srs_gen.srr
View File

@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:35 2016
###########################################################]

14
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -17,13 +17,13 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 78 uses
BI_DIR 10 uses
DFF 88 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 46 uses
IBUF 38 uses
OBUF 15 uses
AND2 299 uses
INV 261 uses
AND2 301 uses
INV 262 uses
OR2 27 uses
XOR2 7 uses
@ -35,6 +35,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:36 2016
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":380:22:380:22|No identifier "clk_000_ne_d" in scope
@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":406:49:406:49|Expecting keyword then
@E|Parse errors encountered - exiting

8
Logic/synlog/report/BUS68030_compiler_notes.txt
View File

@ -2,8 +2,8 @@
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>11</data>
<data>8</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1471448741</data>
<data type="timestamp">1471558834</data>
</info>
</job_info>
</job_run_status>

19
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,12 +1,9 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>105MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1471448743</data>
<data type="timestamp">1471558836</data>
</info>
</job_info>
</job_run_status>

65
Logic/syntmp/BUS68030_srr.htm
View File

@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1471448741>
<!@TC:1471558834>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
@ -8,32 +8,29 @@
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Wed Aug 17 17:45:41 2016
#Fri Aug 19 00:20:34 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1471448741> | Running in 64-bit mode
@N: : <!@TM:1471558834> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1471448741> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471448741> | Top entity is set to BUS68030.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1471558834> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471558834> | Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471448741> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1471448741> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1471448741> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1471448741> | Signal clk_out_pre is undriven </font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471558834> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:71:10:71:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(71)</a><!@TM:1471558834> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:88:14:88:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(88)</a><!@TM:1471558834> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:7:129:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1471558834> | Signal clk_out_pre is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Pruning register AMIGA_BUS_ENABLE_INT_5 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1471448741> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1471448741> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:151:2:151:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(151)</a><!@TM:1471448741> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:61:130:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471448741> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:55:129:65:@W:CL271:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1471448741> | Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:38:127:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1471448741> | Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Trying to extract state machine for register SM_AMIGA
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1471558834> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1471558834> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1471558834> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:36:127:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1471558834> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:163:2:163:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(163)</a><!@TM:1471558834> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1471558834> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1471558834> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -44,24 +41,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1471448741> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1471558834> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1471558834> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:41 2016
# Fri Aug 19 00:20:34 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1471448743> | Running in 64-bit mode
@N: : <!@TM:1471558835> | Running in 64-bit mode
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:35 2016
###########################################################]
Map & Optimize Report
@ -69,8 +66,8 @@ Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471448743> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N::@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448743> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471558836> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N::@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1471558836> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -85,25 +82,25 @@ original code -> new code
<a name=resourceUsage3>Resource Usage Report</a>
Simple gate primitives:
DFF 78 uses
BI_DIR 10 uses
DFF 88 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 46 uses
IBUF 38 uses
OBUF 15 uses
AND2 299 uses
INV 261 uses
AND2 301 uses
INV 262 uses
OR2 27 uses
XOR2 7 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1471448743> | Timing Report not generated for this device, please use place and route tools for timing analysis.
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1471558836> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
# Fri Aug 19 00:20:36 2016
###########################################################]

2
Logic/syntmp/BUS68030_toc.htm
View File

@ -16,7 +16,7 @@
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (17:45 17-Aug)</a>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (00:20 19-Aug)</a>
<ul ></ul></li> </ul>
</li>
</ul>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Wed Aug 17 17:45:41 2016
Written on Fri Aug 19 00:20:34 2016
-->

8
Logic/syntmp/statusReport.html
View File

@ -33,12 +33,12 @@
<tr>
<td class="optionTitle">Compile Input</td><td>Complete</td>
<td>8</td>
<td>11</td>
<td>8</td>
<td>0</td>
<td>-</td>
<td>0m:00s</td>
<td>-</td>
<td><font size="-1">17.08.2016</font><br/><font size="-2">17:45:41</font></td>
<td><font size="-1">19.08.2016</font><br/><font size="-2">00:20:34</font></td>
</tr>
<tr>
@ -49,12 +49,12 @@
<td>0m:00s</td>
<td>0m:00s</td>
<td>105MB</td>
<td><font size="-1">17.08.2016</font><br/><font size="-2">17:45:43</font></td>
<td><font size="-1">19.08.2016</font><br/><font size="-2">00:20:36</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">17.08.2016</font><br/><font size="-2">17:45:43</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">19.08.2016</font><br/><font size="-2">00:20:35</font></td> </tbody>
</table>
</td></tr></table></body>
</html>

2
Logic/synwork/BUS68030_comp.fdep
View File

@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471448728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471558823
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_comp.fdeporig
View File

@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471448728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471558823
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_comp.srs
View File

Binary file not shown.

27
Logic/synwork/BUS68030_comp.tlg
View File

@ -1,18 +1,15 @@
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -23,5 +20,5 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

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Logic/synwork/BUS68030_mult.srs
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Logic/synwork/BUS68030_mult_srs/skeleton.srs
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Logic/synwork/BUS68030_s.srs
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