DMA-Bug fixed

When BGACK gets deasserted, the DMA-Statemachine has to wait for AS_000
to deassert too!

Logic/68030-68000-bus.vhd

@@ -269,6 +269,7 @@ begin
 					BGACK_030_INT	<= '0';
 				elsif (	BGACK_000='1' 
 						AND CLK_000_PE='1'
+						AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
 						--AND CLK_000_D0='1' and CLK_000_D1='0'
 						) then -- BGACK_000 is high here!
 					BGACK_030_INT_PRE<= '1';
@@ -492,10 +493,10 @@ begin
 	end process pos_clk;
 
 	--output clock assignment
-	--CLK_DIV_OUT	<= CLK_OUT_INT;
-	--CLK_EXP		<= CLK_OUT_INT;
-	CLK_DIV_OUT	<= 'Z';
-	CLK_EXP		<= CLK_030;
+	CLK_DIV_OUT	<= CLK_OUT_INT;
+	CLK_EXP		<= CLK_OUT_INT;
+	--CLK_DIV_OUT	<= 'Z';
+	--CLK_EXP		<= CLK_030;
 
 
 	
@@ -556,10 +557,9 @@ begin
 
 
 	--cache inhibit:  Tristate for expansion (it decides) and off for the Amiga 
-	CIIN <= 'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
-			'1' WHEN A(31 downto 24) = x"00" and AS_030_D0 ='0' and nEXP_SPACE_D0 = '1' ELSE -- Enable for Kick-rom
-			'Z'; --off for the Amiga
-
+	CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
+			'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
+			'0'; --off for the Amiga
 		
 	--e and VMA		
 	E		<= cpu_est(3);

Logic/68030_TK.STY

@@ -1,4 +1,4 @@
-[synthesis-type]
-tool=Synplify
 [STRATEGY-LIST]
 Normal=True, 1412327082
+[synthesis-type]
+tool=Synplify

Logic/68030_TK.tcl

@@ -342396,3 +342396,719 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
 
 ########## Tcl recorder end at 07/09/15 18:48:45 ###########
 
+
+########## Tcl recorder starts at 09/24/15 15:46:43 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 15:46:43 ###########
+
+
+########## Tcl recorder starts at 09/24/15 15:46:43 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 15:46:43 ###########
+
+
+########## Tcl recorder starts at 09/24/15 16:04:18 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 16:04:18 ###########
+
+
+########## Tcl recorder starts at 09/24/15 16:04:18 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 16:04:18 ###########
+
+
+########## Tcl recorder starts at 09/24/15 16:16:41 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 16:16:41 ###########
+
+
+########## Tcl recorder starts at 09/24/15 16:20:44 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 16:20:44 ###########
+
+
+########## Tcl recorder starts at 09/24/15 16:20:44 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 09/24/15 16:20:44 ###########
+

Logic/68030_tk.bl3

@@ -1,39 +1,40 @@
 #$ TOOL ispLEVER Classic 1.8.00.04.29.14
-#$ DATE Thu Jul 09 18:48:59 2015
+#$ DATE Thu Sep 24 16:20:59 2015
 #$ MODULE 68030_tk
-#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ IPL_030_2_ A_25_ A_24_ \
-#  IPL_2_ FC_1_ AS_030 AS_000 A_19_ RW_000 A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A0 A1 \
-#  nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \
-#  CLK_EXP FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E VPA \
-#  VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
-#  AMIGA_BUS_ENABLE_HIGH CIIN
+#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \
+#  IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 \
+#  nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI IPL_030_1_ \
+#  CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E \
+#  VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
+#  AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_
 #$ NODES 84 inst_BGACK_030_INTreg cpu_est_3_reg inst_VMA_INTreg inst_RESET_OUTreg \
-#  N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ \
-#  inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 \
-#  inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
-#  CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \
-#  inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 \
-#  inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE \
+#  cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \
+#  inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC \
+#  inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ \
+#  SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT \
+#  inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 \
+#  inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE \
 #  CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ \
 #  inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \
 #  SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ \
 #  RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ \
 #  CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ \
 #  CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ \
-#  CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ \
-#  CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ \
-#  CLK_000_N_SYNC_10_ inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA inst_CLK_030_H \
-#  SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ BG_000DFFreg \
-#  IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg
+#  CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ \
+#  pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ \
+#  CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ \
+#  inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ \
+#  SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ BG_000DFFreg IPL_030DFF_0_reg \
+#  IPL_030DFF_1_reg IPL_030DFF_2_reg
 .model bus68030
 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
 BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
 DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
-A_26_.BLIF A_25_.BLIF A_24_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
-IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
-cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF inst_RESET_OUTreg.BLIF N_165.BLIF \
-cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF \
-inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
+A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
+inst_BGACK_030_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \
+inst_RESET_OUTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \
+SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
 inst_nEXP_SPACE_D0reg.BLIF inst_DS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF \
 inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \
 CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \
@@ -50,106 +51,102 @@ CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF \
 CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF \
 CLK_000_P_SYNC_8_.BLIF CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF \
 CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF \
-CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF \
-CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \
-inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF \
-SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF inst_DS_000_ENABLE.BLIF \
-SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF IPL_030DFF_0_reg.BLIF \
-IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
-RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
-SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
+pos_clk_un29_clk_000_ne_d0_i_n.BLIF CLK_000_N_SYNC_5_.BLIF \
+CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \
+CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \
+inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \
+SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_i_7_.BLIF \
+BG_000DFFreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \
+IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
+DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
+SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
 .outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \
 VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
-AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \
-SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \
+AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \
+IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
+IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \
 SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D \
 SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
 cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \
 cpu_est_3_reg.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \
-IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \
-IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D \
-RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.C \
-RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D \
-CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \
-SIZE_DMA_1_.D SIZE_DMA_1_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \
-CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \
-CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \
-CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \
-CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \
-CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
-CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
-CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
-CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
-CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.D \
-CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C \
-CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \
-CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \
-CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
-CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C inst_LDS_000_INT.D \
-inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
+IPL_030DFF_1_reg.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \
+CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \
+CLK_000_N_SYNC_11_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
+RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C \
+RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
+CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
+SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
+CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \
+CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \
+CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \
+CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \
+CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \
+CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \
+CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
+CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \
+CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
+CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
+CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
+CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.C inst_RESET_OUTreg.D \
+inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
+inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
+inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
+inst_BGACK_030_INTreg.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
 inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
 inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
 inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \
 inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
 inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
-inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUTreg.D inst_RESET_OUTreg.C \
-inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_BGACK_030_INTreg.D \
-inst_BGACK_030_INTreg.C BG_000DFFreg.D BG_000DFFreg.C \
-inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
-inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
-inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \
-inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
-inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \
-inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \
-inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \
-inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
-inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \
-UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_165 AS_030.OE AS_000.OE RW_000.OE \
-DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \
-CLK_DIV_OUT.OE DSACK1.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \
-SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 RST_DLY_4_.D.X1 RST_DLY_4_.D.X2 \
-RST_DLY_5_.D.X1 RST_DLY_5_.D.X2 RST_DLY_6_.D.X1 RST_DLY_6_.D.X2 \
-inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2
+inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
+inst_UDS_000_INT.D inst_UDS_000_INT.C inst_BGACK_030_INT_D.D \
+inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D \
+inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
+inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
+inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C \
+SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ \
+pos_clk_un29_clk_000_ne_d0_i_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE \
+UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \
+DSACK1.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 SM_AMIGA_3_.D.X1 \
+SM_AMIGA_3_.D.X2 RST_DLY_4_.D.X1 RST_DLY_4_.D.X2 RST_DLY_5_.D.X1 \
+RST_DLY_5_.D.X2 RST_DLY_6_.D.X1 RST_DLY_6_.D.X2 inst_CLK_030_H.D.X1 \
+inst_CLK_030_H.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2
+.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
+IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
+1-00001- 1
+1-01101- 1
+1-10011- 1
+1-11111- 1
+1------1 1
+------11 1
+--1--0-1 1
+--0--1-1 1
+---10--1 1
+---01--1 1
+-0------ 1
+0100000- 0
+0101100- 0
+0110010- 0
+0111110- 0
+-11--0-0 0
+-10--1-0 0
+-1-10--0 0
+-1-01--0 0
+-1----00 0
+01-----0 0
+.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D
+0- 1
+-1 1
+10 0
+.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D
+0- 1
+-1 1
+10 0
 .names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D
 1- 1
 -0 1
 01 0
-.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF N_165.BLIF \
-cpu_est_0_.BLIF cpu_est_1_.BLIF SM_AMIGA_5_.BLIF inst_VPA_D.BLIF \
-inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF cpu_est_2_.BLIF \
-SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \
-SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
-SM_AMIGA_i_7_.D
-11000000---1-100000- 1
-110000-0--11-100-00- 1
-11000000-1-1-10-0--- 1
-110000-0-111-10----- 1
-1--0--010----100000- 1
-1--0---10-1--100-00- 1
-1--0--0-----0-00000- 1
-1--0--0101---10-0--- 1
-1--0------1-0-00-00- 1
-1--0---1011--10----- 1
-1--0--0--1--0-0-0--- 1
-1--0-----11-0-0----- 1
-1--0-----0---------1 1
-1--0----------0----1 1
--------11---1------0 0
----------1----1----- 0
--------0---01------0 0
------1-0----1------0 0
-----1--0----1------0 0
---1----0----1------0 0
--0-----0----1------0 0
-----------0-----1--0 0
-------1---0--------0 0
----------0--------10 0
----------0-------1-0 0
----------0-----1---0 0
-------------10-----0 0
----1---------------- 0
-0------------------- 0
---------------1----0 0
 .names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
 inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
 SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
@@ -291,37 +288,6 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D
 -1-01--0 0
 -1---0-0 0
 -10----0 0
-.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
-IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
-1-00001- 1
-1-01101- 1
-1-10011- 1
-1-11111- 1
-1------1 1
-------11 1
---1--0-1 1
---0--1-1 1
----10--1 1
----01--1 1
--0------ 1
-0100000- 0
-0101100- 0
-0110010- 0
-0111110- 0
--11--0-0 0
--10--1-0 0
--1-10--0 0
--1-01--0 0
--1----00 0
-01-----0 0
-.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D
-0- 1
--1 1
-10 0
-.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D
-0- 1
--1 1
-10 0
 .names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
 RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
 RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_0_.D
@@ -444,6 +410,51 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
 01 1
 1- 0
 -0 0
+.names RST.BLIF inst_RESET_OUTreg.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \
+RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF \
+RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF inst_RESET_OUTreg.D
+1-111111111 1
+11--------- 1
+0---------- 0
+-0-------0- 0
+-0------0-- 0
+-0-----0--- 0
+-0----0---- 0
+-0---0----- 0
+-0--0------ 0
+-0-0------- 0
+-00-------- 0
+-0--------0 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF SM_AMIGA_3_.BLIF \
+inst_DS_000_ENABLE.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
+1-0-11- 1
+10-1--- 1
+11----1 1
+-0-0-0- 0
+-0-00-- 0
+-010--- 0
+-1---00 0
+-1--0-0 0
+-11---0 0
+0------ 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
+-1-1- 1
+-10-- 1
+0---- 1
+-0--1 1
+1110- 0
+10--0 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
+inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
+-0--1-- 1
+-011--- 1
+-0---0- 1
+0------ 1
+-1----1 1
+10-001- 0
+100-01- 0
+11----0 0
 .names RST.BLIF inst_DS_030_D0.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF \
 SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
 -0-1100 1
@@ -455,6 +466,14 @@ SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
 10-1--1 0
 1-00--- 0
 110---- 0
+.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
+AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
+1-1-- 1
+1--11 1
+-0--- 1
+-100- 0
+-10-0 0
+01--- 0
 .names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
 FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \
 inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
@@ -574,40 +593,6 @@ inst_DS_000_DMA.D
 1- 1
 -0 1
 01 0
-.names RST.BLIF inst_RESET_OUTreg.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \
-RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF \
-RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF inst_RESET_OUTreg.D
-1-111111111 1
-11--------- 1
-0---------- 0
--0-------0- 0
--0------0-- 0
--0-----0--- 0
--0----0---- 0
--0---0----- 0
--0--0------ 0
--0-0------- 0
--00-------- 0
--0--------0 0
-.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF SM_AMIGA_3_.BLIF \
-inst_DS_000_ENABLE.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
-1-0-11- 1
-10-1--- 1
-11----1 1
--0-0-0- 0
--0-00-- 0
--010--- 0
--1---00 0
--1--0-0 0
--11---0 0
-0------ 0
-.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
-inst_BGACK_030_INTreg.D
-1-1- 1
--0-- 1
-1--1 1
--100 0
-01-- 0
 .names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \
 inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
 ----01 1
@@ -638,12 +623,12 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.D
 cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
 cpu_est_2_.BLIF inst_VMA_INTreg.D
 -0-01-1-1 1
-0-------- 1
 --1----0- 1
 --1--1--- 1
--11------ 1
---1-1---- 1
 --10----- 1
+--1-1---- 1
+0-------- 1
+-11------ 1
 --1-----0 1
 10-100-11 0
 1-0---0-- 0
@@ -660,24 +645,6 @@ A0.PIN.BLIF inst_UDS_000_INT.D
 10-10 0
 1-00- 0
 110-- 0
-.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
-inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
--1-1- 1
--10-- 1
-0---- 1
--0--1 1
-1110- 0
-10--0 0
-.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
-inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
--0--1-- 1
--011--- 1
--0---0- 1
-0------ 1
--1----1 1
-10-001- 0
-100-01- 0
-11----0 0
 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
 0- 1
 -1 1
@@ -685,21 +652,18 @@ inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
 0 1
 1 0
-.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
-inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF \
-SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF N_165
-0---1000000 1
-0--0-000000 1
-0-1--000000 1
-00---000000 1
--1010------ 0
----------1- 0
---------1-- 0
--------1--- 0
-------1---- 0
------1----- 0
-1---------- 0
-----------1 0
+.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
+inst_VPA_D.BLIF inst_DTACK_D0.BLIF cpu_est_2_.BLIF inst_CLK_000_NE_D0.BLIF \
+pos_clk_un29_clk_000_ne_d0_i_n
+----0-0- 1
+----11-- 1
+---10--- 1
+--1-0--- 1
+-1--0--- 1
+0---0--- 1
+-------0 1
+10000-11 0
+----10-1 0
 .names IPL_030DFF_2_reg.BLIF IPL_030_2_
 1 1
 0 0
@@ -761,14 +725,38 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 1-0 1
 00- 0
 1-1 0
-.names CIIN
- 1
+.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
+A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+inst_AS_030_D0.BLIF CIIN
+0000000011110 1
+-----------0- 0
+----------0-- 0
+---------0--- 0
+--------0---- 0
+-------1----- 0
+------1------ 0
+-----1------- 0
+----1-------- 0
+---1--------- 0
+--1---------- 0
+-1----------- 0
+1------------ 0
+------------1 0
 .names IPL_030DFF_1_reg.BLIF IPL_030_1_
 1 1
 0 0
 .names IPL_030DFF_0_reg.BLIF IPL_030_0_
 1 1
 0 0
+.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_D0_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_D0_1_.C
+1 1
+0 0
 .names CLK_OSZI.BLIF IPL_D0_2_.C
 1 1
 0 0
@@ -819,13 +807,22 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 .names CLK_OSZI.BLIF IPL_030DFF_1_reg.C
 1 1
 0 0
-.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C
+.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
 1 1
 0 0
-.names CLK_OSZI.BLIF IPL_D0_0_.C
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
 1 1
 0 0
-.names CLK_OSZI.BLIF IPL_D0_1_.C
+.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
 1 1
 0 0
 .names CLK_OSZI.BLIF RST_DLY_0_.C
@@ -864,6 +861,24 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 .names CLK_OSZI.BLIF SIZE_DMA_1_.C
 1 1
 0 0
+.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
+1 1
+0 0
 .names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
 1 1
 0 0
@@ -931,24 +946,6 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 .names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
 1 1
 0 0
-.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
-1 1
-0 0
-.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
-1 1
-0 0
-.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
-1 1
-0 0
-.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
-1 1
-0 0
-.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
-1 1
-0 0
-.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
-1 1
-0 0
 .names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
 1 1
 0 0
@@ -976,27 +973,27 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 .names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
 1 1
 0 0
-.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
+.names CLK_OSZI.BLIF inst_CLK_030_H.C
 1 1
 0 0
-.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
+.names CLK_OSZI.BLIF inst_RESET_OUTreg.C
 1 1
 0 0
-.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
+.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
 1 1
 0 0
-.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
+.names CLK_OSZI.BLIF inst_RW_000_DMA.C
 1 1
 0 0
-.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
-1 1
-0 0
-.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
+.names CLK_OSZI.BLIF inst_RW_000_INT.C
 1 1
 0 0
 .names CLK_OSZI.BLIF inst_LDS_000_INT.C
 1 1
 0 0
+.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
+1 1
+0 0
 .names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
 1 1
 0 0
@@ -1030,18 +1027,6 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 .names CLK_OSZI.BLIF inst_DTACK_D0.C
 1 1
 0 0
-.names CLK_OSZI.BLIF inst_CLK_030_H.C
-1 1
-0 0
-.names CLK_OSZI.BLIF inst_RESET_OUTreg.C
-1 1
-0 0
-.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
-1 1
-0 0
-.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
-1 1
-0 0
 .names CLK_OSZI.BLIF BG_000DFFreg.C
 1 1
 0 0
@@ -1057,12 +1042,6 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
 .names CLK_OSZI.BLIF inst_UDS_000_INT.C
 1 1
 0 0
-.names CLK_OSZI.BLIF inst_RW_000_DMA.C
-1 1
-0 0
-.names CLK_OSZI.BLIF inst_RW_000_INT.C
-1 1
-0 0
 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
 1 1
 0 0
@@ -1210,18 +1189,23 @@ A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE
 1 1
 0 0
 .names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
-A_25_.BLIF A_24_.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE
-0000000001 1
---------1- 0
--------1-- 0
-------1--- 0
------1---- 0
-----1----- 0
----1------ 0
---1------- 0
--1-------- 0
-1--------- 0
----------0 0
+A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE
+0000000011110- 1
+-------------1 1
+------------10 0
+-----------0-0 0
+----------0--0 0
+---------0---0 0
+--------0----0 0
+-------1-----0 0
+------1------0 0
+-----1-------0 0
+----1--------0 0
+---1---------0 0
+--1----------0 0
+-1-----------0 0
+1------------0 0
 .names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
 inst_CLK_000_NE_D0.BLIF cpu_est_3_reg.D.X1
 11111 1
@@ -1352,4 +1336,48 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
 0--010-00- 0
 0--001-0-0 0
 0--010-0-0 0
+.names RST.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_i_7_.D.X1
+10 1
+0- 0
+-1 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF \
+inst_AS_030_000_SYNC.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF \
+inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF \
+SM_AMIGA_6_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF SM_AMIGA_1_.BLIF \
+SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X2
+100-----000-000- 1
+10-1----000-000- 1
+10--0---000-000- 1
+10---1--000-000- 1
+1-----0--0----10 1
+1-----0--0---1-0 1
+1------0-0--1--0 1
+1-----0--01----0 1
+1-------10-1---0 1
+11-----0-0-----0 1
+1-----0--1-----1 1
+0--------------- 0
+------1--1------ 0
+---------1-----0 0
+-1-------0-----1 0
+--------10-----1 0
+---------01----1 0
+---------0--1--1 0
+---------0---1-1 0
+---------0----11 0
+-1----110------- 0
+------110-1----- 0
+-1----11---0---- 0
+------111--0---- 0
+------110---1--- 0
+-0----1-0-1-0--- 0
+-0----1-1--00--- 0
+-0----1-0---01-- 0
+-0----1-0---0-1- 0
+-1-----1000--00- 0
+-1-----1-000-00- 0
+-------11000-00- 0
+-------1000-100- 0
+-0------1000000- 0
+-01010--000-000- 0
 .end

Logic/68030_tk.crf

@@ -1,7 +1,7 @@
 // Signal Name Cross Reference File
 // ispLEVER Classic 1.8.00.04.29.14
 
-// Design '68030_tk' created Thu Jul 09 18:48:59 2015
+// Design '68030_tk' created Thu Sep 24 16:20:59 2015
 
 
 // LEGEND:  '>'  Functional Block Port Separator

Logic/68030_tk.eq3

@@ -2,13 +2,11 @@
 Copyright(C), 1992-2014, Lattice Semiconductor Corp.
 All Rights Reserved.
 
-Design bus68030 created  Thu Jul 09 18:48:59 2015
+Design bus68030 created  Thu Sep 24 16:20:59 2015
 
 
  P-Terms   Fan-in  Fan-out  Type  Name (attributes)
 ---------  ------  -------  ----  -----------------
-   1          2        1    Pin   SIZE_0_ 
-   1          2        1    Pin   SIZE_0_.OE 
    1          2        1    Pin   SIZE_1_ 
    1          2        1    Pin   SIZE_1_.OE 
    1          2        1    Pin   AS_030- 
@@ -32,8 +30,10 @@ Design bus68030 created  Thu Jul 09 18:48:59 2015
    2          4        1    Pin   AMIGA_BUS_DATA_DIR 
    1          2        1    Pin   AMIGA_BUS_ENABLE_LOW- 
    2          3        1    Pin   AMIGA_BUS_ENABLE_HIGH 
-   1          0        1    Pin   CIIN 
-   1         10        1    Pin   CIIN.OE 
+   1         13        1    Pin   CIIN 
+   1          1        1    Pin   CIIN.OE 
+   1          2        1    Pin   SIZE_0_ 
+   1          2        1    Pin   SIZE_0_.OE 
   10          8        1    Pin   IPL_030_2_.D- 
    1          1        1    Pin   IPL_030_2_.C 
    1          2        1    Pin   RW_000.OE 
@@ -44,7 +44,7 @@ Design bus68030 created  Thu Jul 09 18:48:59 2015
    1          1        1    Pin   A0.C 
    2          6        1    Pin   BG_000.D- 
    1          1        1    Pin   BG_000.C 
-   2          4        1    Pin   BGACK_030.D- 
+   3          5        1    Pin   BGACK_030.D 
    1          1        1    Pin   BGACK_030.C 
   10          8        1    Pin   IPL_030_1_.D- 
    1          1        1    Pin   IPL_030_1_.C 
@@ -62,7 +62,6 @@ Design bus68030 created  Thu Jul 09 18:48:59 2015
    1          2        1    Pin   RW.OE 
    2          5        1    Pin   RW.D- 
    1          1        1    Pin   RW.C 
-   4         11        1    Node  N_165 
    2          2        1    Node  cpu_est_0_.D 
    1          1        1    Node  cpu_est_0_.C 
    5          5        1    Node  cpu_est_1_.D- 
@@ -182,6 +181,7 @@ Design bus68030 created  Thu Jul 09 18:48:59 2015
    1          1        1    Node  CLK_000_N_SYNC_3_.C 
    1          1        1    Node  CLK_000_N_SYNC_4_.D 
    1          1        1    Node  CLK_000_N_SYNC_4_.C 
+   2          8        1    Node  pos_clk_un29_clk_000_ne_d0_i_n- 
    1          1        1    Node  CLK_000_N_SYNC_5_.D 
    1          1        1    Node  CLK_000_N_SYNC_5_.C 
    1          1        1    Node  CLK_000_N_SYNC_6_.D 
@@ -204,21 +204,18 @@ Design bus68030 created  Thu Jul 09 18:48:59 2015
    1          1        1    Node  SM_AMIGA_2_.C 
    3          7        1    Node  inst_DS_000_ENABLE.D 
    1          1        1    Node  inst_DS_000_ENABLE.C 
-  14         20        1    Node  SM_AMIGA_i_7_.D 
+  13         16        1    Node  SM_AMIGA_i_7_.D- 
    1          1        1    Node  SM_AMIGA_i_7_.C 
+   2         14        1    Node  CIIN_0 
 =========
  346                 P-Term Total: 346
-                       Total Pins: 57
-                      Total Nodes: 72
+                       Total Pins: 61
+                      Total Nodes: 73
             Average P-Term/Output: 2
 
 
 Equations:
 
-SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
-
-SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
-
 SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
 
 SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
@@ -267,9 +264,13 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
 AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
      # BGACK_030.Q & !SM_AMIGA_i_7_.Q);
 
-CIIN = (1);
+CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
 
-CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q);
+CIIN.OE = (CIIN_0);
+
+SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
+
+SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
 
 !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
      # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
@@ -305,8 +306,9 @@ A0.C = (CLK_OSZI);
 
 BG_000.C = (CLK_OSZI);
 
-!BGACK_030.D = (!BGACK_000 & RST
-     # RST & !BGACK_030.Q & !inst_CLK_000_PE.Q);
+BGACK_030.D = (!RST
+     # BGACK_000 & BGACK_030.Q
+     # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN);
 
 BGACK_030.C = (CLK_OSZI);
 
@@ -371,11 +373,6 @@ RW.OE = (!BGACK_030.Q & RESET.Q);
 
 RW.C = (CLK_OSZI);
 
-N_165 = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
-
 cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
      # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
 
@@ -687,6 +684,9 @@ CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
 
 CLK_000_N_SYNC_4_.C = (CLK_OSZI);
 
+!pos_clk_un29_clk_000_ne_d0_i_n = (inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q
+     # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
+
 CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
 
 CLK_000_N_SYNC_5_.C = (CLK_OSZI);
@@ -747,23 +747,25 @@ inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q
 
 inst_DS_000_ENABLE.C = (CLK_OSZI);
 
-SM_AMIGA_i_7_.D = (RST & !N_165 & !inst_CLK_000_PE.Q & BERR.PIN
-     # RST & !N_165 & !SM_AMIGA_0_.Q & BERR.PIN
-     # RST & !N_165 & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q
-     # RST & !N_165 & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
-     # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
-     # RST & !N_165 & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
-     # RST & !N_165 & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
-     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
-     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
-     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
+!SM_AMIGA_i_7_.D = (!RST
+     # inst_CLK_000_PE.Q & SM_AMIGA_0_.Q
+     # SM_AMIGA_0_.Q & !BERR.PIN
+     # SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & !BERR.PIN
+     # !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !BERR.PIN
+     # SM_AMIGA_3_.Q & pos_clk_un29_clk_000_ne_d0_i_n & !BERR.PIN
+     # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !BERR.PIN
+     # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN
+     # !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & !BERR.PIN
+     # !SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
 
 SM_AMIGA_i_7_.C = (CLK_OSZI);
 
+CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
+     # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
+
 
 Reverse-Polarity Equations:
 

Logic/68030_tk.fti

@@ -16,6 +16,10 @@ DATA LOCATION A_16_:A_*_96	// INP
 DATA LOCATION A_17_:F_*_59	// INP
 DATA LOCATION A_18_:A_*_95	// INP
 DATA LOCATION A_19_:A_*_97	// INP
+DATA LOCATION A_20_:A_*_93	// INP
+DATA LOCATION A_21_:A_*_94	// INP
+DATA LOCATION A_22_:H_*_84	// INP
+DATA LOCATION A_23_:H_*_85	// INP
 DATA LOCATION A_24_:C_*_19	// INP
 DATA LOCATION A_25_:C_*_18	// INP
 DATA LOCATION A_26_:C_*_17	// INP
@@ -30,35 +34,36 @@ DATA LOCATION BGACK_030:H_4_83	//  IO {RN_BGACK_030}
 DATA LOCATION BG_000:D_1_29	//  IO {RN_BG_000}
 DATA LOCATION BG_030:C_*_21	// INP
 DATA LOCATION CIIN:E_12_47	// OUT
+DATA LOCATION CIIN_0:E_5	// NOD
 DATA LOCATION CLK_000:*_*_11	// INP
-DATA LOCATION CLK_000_N_SYNC_0_:D_7	// NOD
+DATA LOCATION CLK_000_N_SYNC_0_:F_6	// NOD
 DATA LOCATION CLK_000_N_SYNC_10_:H_2	// NOD
 DATA LOCATION CLK_000_N_SYNC_11_:H_6	// NOD
-DATA LOCATION CLK_000_N_SYNC_1_:A_15	// NOD
-DATA LOCATION CLK_000_N_SYNC_2_:A_11	// NOD
-DATA LOCATION CLK_000_N_SYNC_3_:A_7	// NOD
-DATA LOCATION CLK_000_N_SYNC_4_:D_3	// NOD
-DATA LOCATION CLK_000_N_SYNC_5_:A_3	// NOD
-DATA LOCATION CLK_000_N_SYNC_6_:D_14	// NOD
-DATA LOCATION CLK_000_N_SYNC_7_:E_8	// NOD
-DATA LOCATION CLK_000_N_SYNC_8_:A_14	// NOD
-DATA LOCATION CLK_000_N_SYNC_9_:G_3	// NOD
-DATA LOCATION CLK_000_P_SYNC_0_:D_11	// NOD
-DATA LOCATION CLK_000_P_SYNC_1_:G_11	// NOD
-DATA LOCATION CLK_000_P_SYNC_2_:B_3	// NOD
-DATA LOCATION CLK_000_P_SYNC_3_:C_9	// NOD
-DATA LOCATION CLK_000_P_SYNC_4_:B_4	// NOD
-DATA LOCATION CLK_000_P_SYNC_5_:E_9	// NOD
-DATA LOCATION CLK_000_P_SYNC_6_:E_5	// NOD
-DATA LOCATION CLK_000_P_SYNC_7_:G_7	// NOD
-DATA LOCATION CLK_000_P_SYNC_8_:C_5	// NOD
-DATA LOCATION CLK_000_P_SYNC_9_:C_2	// NOD
+DATA LOCATION CLK_000_N_SYNC_1_:G_7	// NOD
+DATA LOCATION CLK_000_N_SYNC_2_:G_3	// NOD
+DATA LOCATION CLK_000_N_SYNC_3_:B_7	// NOD
+DATA LOCATION CLK_000_N_SYNC_4_:B_3	// NOD
+DATA LOCATION CLK_000_N_SYNC_5_:B_14	// NOD
+DATA LOCATION CLK_000_N_SYNC_6_:A_6	// NOD
+DATA LOCATION CLK_000_N_SYNC_7_:B_10	// NOD
+DATA LOCATION CLK_000_N_SYNC_8_:G_14	// NOD
+DATA LOCATION CLK_000_N_SYNC_9_:F_2	// NOD
+DATA LOCATION CLK_000_P_SYNC_0_:D_10	// NOD
+DATA LOCATION CLK_000_P_SYNC_1_:C_11	// NOD
+DATA LOCATION CLK_000_P_SYNC_2_:B_11	// NOD
+DATA LOCATION CLK_000_P_SYNC_3_:C_7	// NOD
+DATA LOCATION CLK_000_P_SYNC_4_:D_6	// NOD
+DATA LOCATION CLK_000_P_SYNC_5_:F_10	// NOD
+DATA LOCATION CLK_000_P_SYNC_6_:A_3	// NOD
+DATA LOCATION CLK_000_P_SYNC_7_:A_14	// NOD
+DATA LOCATION CLK_000_P_SYNC_8_:A_10	// NOD
+DATA LOCATION CLK_000_P_SYNC_9_:A_7	// NOD
 DATA LOCATION CLK_030:*_*_64	// INP
 DATA LOCATION CLK_DIV_OUT:G_1_65	// OUT
 DATA LOCATION CLK_EXP:B_1_10	// OUT
 DATA LOCATION CLK_OSZI:*_*_61	// Cin
-DATA LOCATION CYCLE_DMA_0_:A_10	// NOD
-DATA LOCATION CYCLE_DMA_1_:A_6	// NOD
+DATA LOCATION CYCLE_DMA_0_:A_2	// NOD
+DATA LOCATION CYCLE_DMA_1_:A_13	// NOD
 DATA LOCATION DSACK1:H_9_81	//  IO {RN_DSACK1}
 DATA LOCATION DS_030:A_0_98	//  IO
 DATA LOCATION DTACK:D_*_30	// INP
@@ -68,38 +73,37 @@ DATA LOCATION FC_1_:F_*_58	// INP
 DATA LOCATION FPU_CS:H_1_78	// OUT
 DATA LOCATION FPU_SENSE:A_*_91	// INP
 DATA LOCATION IPL_030_0_:B_8_8	//  IO {RN_IPL_030_0_}
-DATA LOCATION IPL_030_1_:B_6_7	//  IO {RN_IPL_030_1_}
-DATA LOCATION IPL_030_2_:B_2_9	//  IO {RN_IPL_030_2_}
+DATA LOCATION IPL_030_1_:B_12_7	//  IO {RN_IPL_030_1_}
+DATA LOCATION IPL_030_2_:B_4_9	//  IO {RN_IPL_030_2_}
 DATA LOCATION IPL_0_:G_*_67	// INP
 DATA LOCATION IPL_1_:F_*_56	// INP
 DATA LOCATION IPL_2_:G_*_68	// INP
-DATA LOCATION IPL_D0_0_:B_7	// NOD
-DATA LOCATION IPL_D0_1_:C_13	// NOD
-DATA LOCATION IPL_D0_2_:B_13	// NOD
+DATA LOCATION IPL_D0_0_:D_3	// NOD
+DATA LOCATION IPL_D0_1_:D_14	// NOD
+DATA LOCATION IPL_D0_2_:G_11	// NOD
 DATA LOCATION LDS_000:D_12_31	//  IO
-DATA LOCATION N_165:F_6	// NOD
-DATA LOCATION RESET:B_14_3	//  IO {RN_RESET}
+DATA LOCATION RESET:B_0_3	//  IO {RN_RESET}
 DATA LOCATION RN_A0:G_8	// NOD {A0}
 DATA LOCATION RN_BGACK_030:H_4	// NOD {BGACK_030}
 DATA LOCATION RN_BG_000:D_1	// NOD {BG_000}
 DATA LOCATION RN_DSACK1:H_9	// NOD {DSACK1}
 DATA LOCATION RN_E:G_4	// NOD {E}
 DATA LOCATION RN_IPL_030_0_:B_8	// NOD {IPL_030_0_}
-DATA LOCATION RN_IPL_030_1_:B_6	// NOD {IPL_030_1_}
-DATA LOCATION RN_IPL_030_2_:B_2	// NOD {IPL_030_2_}
-DATA LOCATION RN_RESET:B_14	// NOD {RESET}
+DATA LOCATION RN_IPL_030_1_:B_12	// NOD {IPL_030_1_}
+DATA LOCATION RN_IPL_030_2_:B_4	// NOD {IPL_030_2_}
+DATA LOCATION RN_RESET:B_0	// NOD {RESET}
 DATA LOCATION RN_RW:G_0	// NOD {RW}
 DATA LOCATION RN_RW_000:H_0	// NOD {RW_000}
 DATA LOCATION RN_VMA:D_0	// NOD {VMA}
 DATA LOCATION RST:*_*_86	// INP
-DATA LOCATION RST_DLY_0_:B_10	// NOD
-DATA LOCATION RST_DLY_1_:A_1	// NOD
+DATA LOCATION RST_DLY_0_:C_6	// NOD
+DATA LOCATION RST_DLY_1_:B_13	// NOD
 DATA LOCATION RST_DLY_2_:B_5	// NOD
-DATA LOCATION RST_DLY_3_:B_0	// NOD
-DATA LOCATION RST_DLY_4_:B_12	// NOD
-DATA LOCATION RST_DLY_5_:A_12	// NOD
-DATA LOCATION RST_DLY_6_:B_11	// NOD
-DATA LOCATION RST_DLY_7_:A_5	// NOD
+DATA LOCATION RST_DLY_3_:C_9	// NOD
+DATA LOCATION RST_DLY_4_:C_14	// NOD
+DATA LOCATION RST_DLY_5_:B_9	// NOD
+DATA LOCATION RST_DLY_6_:C_2	// NOD
+DATA LOCATION RST_DLY_7_:C_10	// NOD
 DATA LOCATION RW:G_0_71	//  IO {RN_RW}
 DATA LOCATION RW_000:H_0_80	//  IO {RN_RW_000}
 DATA LOCATION SIZE_0_:G_12_70	//  IO
@@ -107,43 +111,44 @@ DATA LOCATION SIZE_1_:H_12_79	//  IO
 DATA LOCATION SIZE_DMA_0_:G_6	// NOD
 DATA LOCATION SIZE_DMA_1_:G_2	// NOD
 DATA LOCATION SM_AMIGA_0_:F_9	// NOD
-DATA LOCATION SM_AMIGA_1_:F_1	// NOD
-DATA LOCATION SM_AMIGA_2_:F_2	// NOD
-DATA LOCATION SM_AMIGA_3_:F_12	// NOD
-DATA LOCATION SM_AMIGA_4_:F_10	// NOD
-DATA LOCATION SM_AMIGA_5_:F_4	// NOD
-DATA LOCATION SM_AMIGA_6_:C_4	// NOD
-DATA LOCATION SM_AMIGA_i_7_:F_0	// NOD
+DATA LOCATION SM_AMIGA_1_:C_1	// NOD
+DATA LOCATION SM_AMIGA_2_:C_13	// NOD
+DATA LOCATION SM_AMIGA_3_:C_8	// NOD
+DATA LOCATION SM_AMIGA_4_:F_1	// NOD
+DATA LOCATION SM_AMIGA_5_:F_12	// NOD
+DATA LOCATION SM_AMIGA_6_:F_5	// NOD
+DATA LOCATION SM_AMIGA_i_7_:F_8	// NOD
 DATA LOCATION UDS_000:D_8_32	//  IO
 DATA LOCATION VMA:D_0_35	//  IO {RN_VMA}
 DATA LOCATION VPA:*_*_36	// INP
-DATA LOCATION cpu_est_0_:D_6	// NOD
-DATA LOCATION cpu_est_1_:D_13	// NOD
-DATA LOCATION cpu_est_2_:D_2	// NOD
+DATA LOCATION cpu_est_0_:C_5	// NOD
+DATA LOCATION cpu_est_1_:G_5	// NOD
+DATA LOCATION cpu_est_2_:C_12	// NOD
 DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_10	// NOD
-DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_14	// NOD
+DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_3	// NOD
 DATA LOCATION inst_AS_000_DMA:A_8	// NOD
-DATA LOCATION inst_AS_000_INT:C_1	// NOD
-DATA LOCATION inst_AS_030_000_SYNC:C_8	// NOD
+DATA LOCATION inst_AS_000_INT:A_1	// NOD
+DATA LOCATION inst_AS_030_000_SYNC:F_13	// NOD
 DATA LOCATION inst_AS_030_D0:H_5	// NOD
 DATA LOCATION inst_BGACK_030_INT_D:H_13	// NOD
-DATA LOCATION inst_CLK_000_D0:G_13	// NOD
-DATA LOCATION inst_CLK_000_D1:F_8	// NOD
-DATA LOCATION inst_CLK_000_NE:G_9	// NOD
-DATA LOCATION inst_CLK_000_NE_D0:B_15	// NOD
-DATA LOCATION inst_CLK_000_PE:D_9	// NOD
-DATA LOCATION inst_CLK_030_H:A_2	// NOD
-DATA LOCATION inst_CLK_OUT_PRE_50:A_9	// NOD
-DATA LOCATION inst_CLK_OUT_PRE_D:G_15	// NOD
-DATA LOCATION inst_DS_000_DMA:A_13	// NOD
-DATA LOCATION inst_DS_000_ENABLE:C_12	// NOD
-DATA LOCATION inst_DS_030_D0:D_10	// NOD
-DATA LOCATION inst_DTACK_D0:D_15	// NOD
-DATA LOCATION inst_LDS_000_INT:B_9	// NOD
-DATA LOCATION inst_UDS_000_INT:F_5	// NOD
-DATA LOCATION inst_VPA_D:F_13	// NOD
-DATA LOCATION inst_nEXP_SPACE_D0reg:G_5	// NOD
+DATA LOCATION inst_CLK_000_D0:B_2	// NOD
+DATA LOCATION inst_CLK_000_D1:D_9	// NOD
+DATA LOCATION inst_CLK_000_NE:F_4	// NOD
+DATA LOCATION inst_CLK_000_NE_D0:E_8	// NOD
+DATA LOCATION inst_CLK_000_PE:C_4	// NOD
+DATA LOCATION inst_CLK_030_H:A_9	// NOD
+DATA LOCATION inst_CLK_OUT_PRE_50:E_9	// NOD
+DATA LOCATION inst_CLK_OUT_PRE_D:E_13	// NOD
+DATA LOCATION inst_DS_000_DMA:A_5	// NOD
+DATA LOCATION inst_DS_000_ENABLE:A_12	// NOD
+DATA LOCATION inst_DS_030_D0:D_7	// NOD
+DATA LOCATION inst_DTACK_D0:B_6	// NOD
+DATA LOCATION inst_LDS_000_INT:G_9	// NOD
+DATA LOCATION inst_UDS_000_INT:G_13	// NOD
+DATA LOCATION inst_VPA_D:D_13	// NOD
+DATA LOCATION inst_nEXP_SPACE_D0reg:F_0	// NOD
 DATA LOCATION nEXP_SPACE:*_*_14	// INP
+DATA LOCATION pos_clk_un29_clk_000_ne_d0_i_n:D_2	// NOD
 DATA IO_DIR   A0:BI
 DATA IO_DIR   A1:IN
 DATA IO_DIR   AMIGA_ADDR_ENABLE:OUT
@@ -157,6 +162,10 @@ DATA IO_DIR   A_16_:IN
 DATA IO_DIR   A_17_:IN
 DATA IO_DIR   A_18_:IN
 DATA IO_DIR   A_19_:IN
+DATA IO_DIR   A_20_:IN
+DATA IO_DIR   A_21_:IN
+DATA IO_DIR   A_22_:IN
+DATA IO_DIR   A_23_:IN
 DATA IO_DIR   A_24_:IN
 DATA IO_DIR   A_25_:IN
 DATA IO_DIR   A_26_:IN
@@ -202,46 +211,48 @@ DATA IO_DIR   VMA:OUT
 DATA IO_DIR   VPA:IN
 DATA IO_DIR   nEXP_SPACE:IN
 DATA GLB_CLOCK  CLK_OSZI
-DATA PW_LEVEL  SIZE_0_:1
-DATA SLEW      SIZE_0_:1
-DATA PW_LEVEL  A_30_:1
-DATA SLEW      A_30_:1
-DATA PW_LEVEL  SIZE_1_:1
-DATA SLEW      SIZE_1_:1
-DATA PW_LEVEL  A_29_:1
-DATA SLEW      A_29_:1
 DATA PW_LEVEL  A_28_:1
 DATA SLEW      A_28_:1
-DATA PW_LEVEL  A_31_:1
-DATA SLEW      A_31_:1
 DATA PW_LEVEL  A_27_:1
 DATA SLEW      A_27_:1
+DATA PW_LEVEL  SIZE_1_:1
+DATA SLEW      SIZE_1_:1
 DATA PW_LEVEL  A_26_:1
 DATA SLEW      A_26_:1
 DATA PW_LEVEL  A_25_:1
 DATA SLEW      A_25_:1
+DATA PW_LEVEL  A_31_:1
+DATA SLEW      A_31_:1
 DATA PW_LEVEL  A_24_:1
 DATA SLEW      A_24_:1
+DATA PW_LEVEL  A_23_:1
+DATA SLEW      A_23_:1
+DATA PW_LEVEL  A_22_:1
+DATA SLEW      A_22_:1
+DATA PW_LEVEL  A_21_:1
+DATA SLEW      A_21_:1
 DATA PW_LEVEL  IPL_2_:1
 DATA SLEW      IPL_2_:1
-DATA PW_LEVEL  FC_1_:1
-DATA SLEW      FC_1_:1
-DATA PW_LEVEL  AS_030:1
-DATA SLEW      AS_030:1
-DATA PW_LEVEL  AS_000:1
-DATA SLEW      AS_000:1
+DATA PW_LEVEL  A_20_:1
+DATA SLEW      A_20_:1
 DATA PW_LEVEL  A_19_:1
 DATA SLEW      A_19_:1
+DATA PW_LEVEL  FC_1_:1
+DATA SLEW      FC_1_:1
 DATA PW_LEVEL  A_18_:1
 DATA SLEW      A_18_:1
-DATA PW_LEVEL  DS_030:1
-DATA SLEW      DS_030:1
+DATA PW_LEVEL  AS_030:1
+DATA SLEW      AS_030:1
 DATA PW_LEVEL  A_17_:1
 DATA SLEW      A_17_:1
-DATA PW_LEVEL  UDS_000:1
-DATA SLEW      UDS_000:1
+DATA PW_LEVEL  AS_000:1
+DATA SLEW      AS_000:1
 DATA PW_LEVEL  A_16_:1
 DATA SLEW      A_16_:1
+DATA PW_LEVEL  DS_030:1
+DATA SLEW      DS_030:1
+DATA PW_LEVEL  UDS_000:1
+DATA SLEW      UDS_000:1
 DATA PW_LEVEL  LDS_000:1
 DATA SLEW      LDS_000:1
 DATA PW_LEVEL  A1:1
@@ -260,20 +271,20 @@ DATA PW_LEVEL  CLK_DIV_OUT:1
 DATA SLEW      CLK_DIV_OUT:0
 DATA PW_LEVEL  CLK_EXP:1
 DATA SLEW      CLK_EXP:0
-DATA PW_LEVEL  FPU_CS:1
-DATA SLEW      FPU_CS:0
-DATA PW_LEVEL  FPU_SENSE:1
-DATA SLEW      FPU_SENSE:1
 DATA PW_LEVEL  IPL_1_:1
 DATA SLEW      IPL_1_:1
-DATA PW_LEVEL  DTACK:1
-DATA SLEW      DTACK:1
+DATA PW_LEVEL  FPU_CS:1
+DATA SLEW      FPU_CS:0
 DATA PW_LEVEL  IPL_0_:1
 DATA SLEW      IPL_0_:1
-DATA PW_LEVEL  AVEC:1
-DATA SLEW      AVEC:1
+DATA PW_LEVEL  FPU_SENSE:1
+DATA SLEW      FPU_SENSE:1
 DATA PW_LEVEL  FC_0_:1
 DATA SLEW      FC_0_:1
+DATA PW_LEVEL  DTACK:1
+DATA SLEW      DTACK:1
+DATA PW_LEVEL  AVEC:1
+DATA SLEW      AVEC:1
 DATA SLEW      VPA:1
 DATA SLEW      RST:1
 DATA PW_LEVEL  AMIGA_ADDR_ENABLE:1
@@ -286,6 +297,12 @@ DATA PW_LEVEL  AMIGA_BUS_ENABLE_HIGH:1
 DATA SLEW      AMIGA_BUS_ENABLE_HIGH:0
 DATA PW_LEVEL  CIIN:1
 DATA SLEW      CIIN:1
+DATA PW_LEVEL  SIZE_0_:1
+DATA SLEW      SIZE_0_:1
+DATA PW_LEVEL  A_30_:1
+DATA SLEW      A_30_:1
+DATA PW_LEVEL  A_29_:1
+DATA SLEW      A_29_:1
 DATA PW_LEVEL  IPL_030_2_:1
 DATA SLEW      IPL_030_2_:1
 DATA PW_LEVEL  RW_000:1
@@ -310,8 +327,6 @@ DATA PW_LEVEL  RESET:1
 DATA SLEW      RESET:1
 DATA PW_LEVEL  RW:1
 DATA SLEW      RW:1
-DATA PW_LEVEL  N_165:1
-DATA SLEW      N_165:1
 DATA PW_LEVEL  cpu_est_0_:1
 DATA SLEW      cpu_est_0_:1
 DATA PW_LEVEL  cpu_est_1_:1
@@ -430,6 +445,8 @@ DATA PW_LEVEL  CLK_000_N_SYNC_3_:1
 DATA SLEW      CLK_000_N_SYNC_3_:1
 DATA PW_LEVEL  CLK_000_N_SYNC_4_:1
 DATA SLEW      CLK_000_N_SYNC_4_:1
+DATA PW_LEVEL  pos_clk_un29_clk_000_ne_d0_i_n:1
+DATA SLEW      pos_clk_un29_clk_000_ne_d0_i_n:1
 DATA PW_LEVEL  CLK_000_N_SYNC_5_:1
 DATA SLEW      CLK_000_N_SYNC_5_:1
 DATA PW_LEVEL  CLK_000_N_SYNC_6_:1
@@ -454,6 +471,8 @@ DATA PW_LEVEL  inst_DS_000_ENABLE:1
 DATA SLEW      inst_DS_000_ENABLE:1
 DATA PW_LEVEL  SM_AMIGA_i_7_:1
 DATA SLEW      SM_AMIGA_i_7_:1
+DATA PW_LEVEL  CIIN_0:1
+DATA SLEW      CIIN_0:1
 DATA PW_LEVEL  RN_IPL_030_2_:1
 DATA PW_LEVEL  RN_RW_000:1
 DATA PW_LEVEL  RN_A0:1

Logic/68030_tk.grp

@@ -1,28 +1,29 @@
 
-GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H RST_DLY_1_ RST_DLY_5_ RST_DLY_7_ 
-      inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ 
-      CLK_000_N_SYNC_3_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_8_ inst_CLK_OUT_PRE_50 
-      DS_030 AVEC 
-GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ 
-      IPL_030_2_ RN_IPL_030_2_ RST_DLY_3_ RST_DLY_0_ RST_DLY_2_ RST_DLY_4_ 
-      RST_DLY_6_ inst_LDS_000_INT IPL_D0_0_ IPL_D0_2_ CLK_000_P_SYNC_2_ 
-      CLK_000_P_SYNC_4_ inst_CLK_000_NE_D0 CLK_EXP 
-GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_DS_000_ENABLE inst_AS_000_INT 
-      IPL_D0_1_ CLK_000_P_SYNC_9_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_8_ AMIGA_BUS_ENABLE_LOW 
+GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_DS_000_ENABLE 
+      CYCLE_DMA_1_ inst_AS_000_INT CYCLE_DMA_0_ CLK_000_P_SYNC_9_ CLK_000_P_SYNC_6_ 
+      CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_6_ DS_030 AVEC 
       
-GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 cpu_est_1_ cpu_est_2_ cpu_est_0_ 
-      CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ inst_DTACK_D0 inst_DS_030_D0 
-      inst_CLK_000_PE CLK_000_N_SYNC_4_ CLK_000_N_SYNC_6_ LDS_000 UDS_000 
-      AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE 
-GROUP MACH_SEG_E CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_N_SYNC_7_ 
-      CIIN BERR AMIGA_BUS_DATA_DIR AS_000 
-GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_1_ 
-      SM_AMIGA_4_ SM_AMIGA_5_ inst_UDS_000_INT inst_VPA_D inst_CLK_000_D1 
-      N_165 
-GROUP MACH_SEG_G A0 RN_A0 RW RN_RW E RN_E SIZE_DMA_0_ SIZE_DMA_1_ inst_AMIGA_BUS_ENABLE_DMA_LOW 
-      inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_nEXP_SPACE_D0reg inst_CLK_000_D0 
-      inst_CLK_000_NE CLK_000_P_SYNC_1_ CLK_000_P_SYNC_7_ CLK_000_N_SYNC_9_ 
-      inst_CLK_OUT_PRE_D SIZE_0_ CLK_DIV_OUT 
+GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ 
+      IPL_030_2_ RN_IPL_030_2_ RST_DLY_1_ RST_DLY_2_ RST_DLY_5_ inst_DTACK_D0 
+      inst_CLK_000_D0 CLK_000_P_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ 
+      CLK_000_N_SYNC_5_ CLK_000_N_SYNC_7_ CLK_EXP 
+GROUP MACH_SEG_C SM_AMIGA_3_ SM_AMIGA_2_ RST_DLY_3_ RST_DLY_0_ RST_DLY_4_ 
+      RST_DLY_6_ RST_DLY_7_ SM_AMIGA_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW 
+      cpu_est_0_ inst_CLK_000_PE CLK_000_P_SYNC_1_ CLK_000_P_SYNC_3_ AMIGA_BUS_ENABLE_LOW 
+      
+GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 CLK_000_P_SYNC_0_ inst_VPA_D 
+      inst_DS_030_D0 IPL_D0_0_ IPL_D0_1_ CLK_000_P_SYNC_4_ inst_CLK_000_D1 
+      LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE pos_clk_un29_clk_000_ne_d0_i_n 
+      
+GROUP MACH_SEG_E inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 inst_CLK_000_NE_D0 
+      CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 
+GROUP MACH_SEG_F SM_AMIGA_i_7_ inst_AS_030_000_SYNC SM_AMIGA_6_ SM_AMIGA_0_ 
+      SM_AMIGA_4_ SM_AMIGA_5_ CLK_000_N_SYNC_0_ inst_nEXP_SPACE_D0reg inst_CLK_000_NE 
+      CLK_000_P_SYNC_5_ CLK_000_N_SYNC_9_ 
+GROUP MACH_SEG_G A0 RN_A0 RW RN_RW E RN_E inst_LDS_000_INT SIZE_DMA_0_ 
+      SIZE_DMA_1_ cpu_est_1_ inst_UDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH 
+      IPL_D0_2_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_8_ SIZE_0_ 
+      CLK_DIV_OUT 
 GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 
       inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_ 
       FPU_CS AS_030 SIZE_1_ 

Logic/68030_tk.ipr

@@ -1 +1 @@
-<LATTICE_ENCRYPTED_BLIF>9273210z*5A(L3-
+<LATTICE_ENCRYPTED_BLIF>9467445Fv,kS-

Logic/68030_tk.lco

@@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
 Parent = m4a5.lci;
 SDS_File = m4a5.sds;
 Design = 68030_tk.tt4;
-DATE = 7/9/15;
-TIME = 18:49:07;
+DATE = 9/24/15;
+TIME = 16:21:08;
 Source_Format = Pure_VHDL;
 Type = TT2;
 Pre_Fit_Time = 1;
@@ -76,26 +76,27 @@ Usercode_Format = Hex;
 
 [LOCATION ASSIGNMENTS]
 Layer = OFF;
-SIZE_0_ = pin,70,-,G,-;
-A_30_ = pin,5,-,B,-;
-SIZE_1_ = pin,79,-,H,-;
-A_29_ = pin,6,-,B,-;
 A_28_ = pin,15,-,C,-;
-A_31_ = pin,4,-,B,-;
 A_27_ = pin,16,-,C,-;
+SIZE_1_ = pin,79,-,H,-;
 A_26_ = pin,17,-,C,-;
 A_25_ = pin,18,-,C,-;
+A_31_ = pin,4,-,B,-;
 A_24_ = pin,19,-,C,-;
+A_23_ = pin,85,-,H,-;
+A_22_ = pin,84,-,H,-;
+A_21_ = pin,94,-,A,-;
 IPL_2_ = pin,68,-,G,-;
-FC_1_ = pin,58,-,F,-;
-AS_030 = pin,82,-,H,-;
-AS_000 = pin,42,-,E,-;
+A_20_ = pin,93,-,A,-;
 A_19_ = pin,97,-,A,-;
+FC_1_ = pin,58,-,F,-;
 A_18_ = pin,95,-,A,-;
-DS_030 = pin,98,-,A,-;
+AS_030 = pin,82,-,H,-;
 A_17_ = pin,59,-,F,-;
-UDS_000 = pin,32,-,D,-;
+AS_000 = pin,42,-,E,-;
 A_16_ = pin,96,-,A,-;
+DS_030 = pin,98,-,A,-;
+UDS_000 = pin,32,-,D,-;
 LDS_000 = pin,31,-,D,-;
 A1 = pin,60,-,F,-;
 nEXP_SPACE = pin,14,-,-,-;
@@ -107,13 +108,13 @@ CLK_000 = pin,11,-,-,-;
 CLK_OSZI = pin,61,-,-,-;
 CLK_DIV_OUT = pin,65,-,G,-;
 CLK_EXP = pin,10,-,B,-;
-FPU_CS = pin,78,-,H,-;
-FPU_SENSE = pin,91,-,A,-;
 IPL_1_ = pin,56,-,F,-;
-DTACK = pin,30,-,D,-;
+FPU_CS = pin,78,-,H,-;
 IPL_0_ = pin,67,-,G,-;
-AVEC = pin,92,-,A,-;
+FPU_SENSE = pin,91,-,A,-;
 FC_0_ = pin,57,-,F,-;
+DTACK = pin,30,-,D,-;
+AVEC = pin,92,-,A,-;
 VPA = pin,36,-,-,-;
 RST = pin,86,-,-,-;
 AMIGA_ADDR_ENABLE = pin,33,-,D,-;
@@ -121,6 +122,9 @@ AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
 AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
 AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
 CIIN = pin,47,-,E,-;
+SIZE_0_ = pin,70,-,G,-;
+A_30_ = pin,5,-,B,-;
+A_29_ = pin,6,-,B,-;
 IPL_030_2_ = pin,9,-,B,-;
 RW_000 = pin,80,-,H,-;
 A0 = pin,69,-,G,-;
@@ -133,78 +137,79 @@ E = pin,66,-,G,-;
 VMA = pin,35,-,D,-;
 RESET = pin,3,-,B,-;
 RW = pin,71,-,G,-;
-N_165 = node,-,-,F,6;
-cpu_est_0_ = node,-,-,D,6;
-cpu_est_1_ = node,-,-,D,13;
-inst_AS_000_INT = node,-,-,C,1;
-SM_AMIGA_5_ = node,-,-,F,4;
-inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,14;
+cpu_est_0_ = node,-,-,C,5;
+cpu_est_1_ = node,-,-,G,5;
+inst_AS_000_INT = node,-,-,A,1;
+SM_AMIGA_5_ = node,-,-,F,12;
+inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,3;
 inst_AS_030_D0 = node,-,-,H,5;
-inst_nEXP_SPACE_D0reg = node,-,-,G,5;
-inst_DS_030_D0 = node,-,-,D,10;
-inst_AS_030_000_SYNC = node,-,-,C,8;
+inst_nEXP_SPACE_D0reg = node,-,-,F,0;
+inst_DS_030_D0 = node,-,-,D,7;
+inst_AS_030_000_SYNC = node,-,-,F,13;
 inst_BGACK_030_INT_D = node,-,-,H,13;
 inst_AS_000_DMA = node,-,-,A,8;
-inst_DS_000_DMA = node,-,-,A,13;
-CYCLE_DMA_0_ = node,-,-,A,10;
-CYCLE_DMA_1_ = node,-,-,A,6;
+inst_DS_000_DMA = node,-,-,A,5;
+CYCLE_DMA_0_ = node,-,-,A,2;
+CYCLE_DMA_1_ = node,-,-,A,13;
 SIZE_DMA_0_ = node,-,-,G,6;
 SIZE_DMA_1_ = node,-,-,G,2;
-inst_VPA_D = node,-,-,F,13;
-inst_UDS_000_INT = node,-,-,F,5;
-inst_LDS_000_INT = node,-,-,B,9;
-inst_CLK_OUT_PRE_D = node,-,-,G,15;
-inst_DTACK_D0 = node,-,-,D,15;
-inst_CLK_OUT_PRE_50 = node,-,-,A,9;
-inst_CLK_000_D1 = node,-,-,F,8;
-inst_CLK_000_D0 = node,-,-,G,13;
-inst_CLK_000_PE = node,-,-,D,9;
-CLK_000_P_SYNC_9_ = node,-,-,C,2;
-inst_CLK_000_NE = node,-,-,G,9;
+inst_VPA_D = node,-,-,D,13;
+inst_UDS_000_INT = node,-,-,G,13;
+inst_LDS_000_INT = node,-,-,G,9;
+inst_CLK_OUT_PRE_D = node,-,-,E,13;
+inst_DTACK_D0 = node,-,-,B,6;
+inst_CLK_OUT_PRE_50 = node,-,-,E,9;
+inst_CLK_000_D1 = node,-,-,D,9;
+inst_CLK_000_D0 = node,-,-,B,2;
+inst_CLK_000_PE = node,-,-,C,4;
+CLK_000_P_SYNC_9_ = node,-,-,A,7;
+inst_CLK_000_NE = node,-,-,F,4;
 CLK_000_N_SYNC_11_ = node,-,-,H,6;
-cpu_est_2_ = node,-,-,D,2;
-IPL_D0_0_ = node,-,-,B,7;
-IPL_D0_1_ = node,-,-,C,13;
-IPL_D0_2_ = node,-,-,B,13;
-SM_AMIGA_3_ = node,-,-,F,12;
-inst_CLK_000_NE_D0 = node,-,-,B,15;
+cpu_est_2_ = node,-,-,C,12;
+IPL_D0_0_ = node,-,-,D,3;
+IPL_D0_1_ = node,-,-,D,14;
+IPL_D0_2_ = node,-,-,G,11;
+SM_AMIGA_3_ = node,-,-,C,8;
+inst_CLK_000_NE_D0 = node,-,-,E,8;
 SM_AMIGA_0_ = node,-,-,F,9;
 inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,10;
-SM_AMIGA_6_ = node,-,-,C,4;
-RST_DLY_0_ = node,-,-,B,10;
-RST_DLY_1_ = node,-,-,A,1;
+SM_AMIGA_6_ = node,-,-,F,5;
+RST_DLY_0_ = node,-,-,C,6;
+RST_DLY_1_ = node,-,-,B,13;
 RST_DLY_2_ = node,-,-,B,5;
-RST_DLY_3_ = node,-,-,B,0;
-RST_DLY_4_ = node,-,-,B,12;
-RST_DLY_5_ = node,-,-,A,12;
-RST_DLY_6_ = node,-,-,B,11;
-RST_DLY_7_ = node,-,-,A,5;
-CLK_000_P_SYNC_0_ = node,-,-,D,11;
-CLK_000_P_SYNC_1_ = node,-,-,G,11;
-CLK_000_P_SYNC_2_ = node,-,-,B,3;
-CLK_000_P_SYNC_3_ = node,-,-,C,9;
-CLK_000_P_SYNC_4_ = node,-,-,B,4;
-CLK_000_P_SYNC_5_ = node,-,-,E,9;
-CLK_000_P_SYNC_6_ = node,-,-,E,5;
-CLK_000_P_SYNC_7_ = node,-,-,G,7;
-CLK_000_P_SYNC_8_ = node,-,-,C,5;
-CLK_000_N_SYNC_0_ = node,-,-,D,7;
-CLK_000_N_SYNC_1_ = node,-,-,A,15;
-CLK_000_N_SYNC_2_ = node,-,-,A,11;
-CLK_000_N_SYNC_3_ = node,-,-,A,7;
-CLK_000_N_SYNC_4_ = node,-,-,D,3;
-CLK_000_N_SYNC_5_ = node,-,-,A,3;
-CLK_000_N_SYNC_6_ = node,-,-,D,14;
-CLK_000_N_SYNC_7_ = node,-,-,E,8;
-CLK_000_N_SYNC_8_ = node,-,-,A,14;
-CLK_000_N_SYNC_9_ = node,-,-,G,3;
+RST_DLY_3_ = node,-,-,C,9;
+RST_DLY_4_ = node,-,-,C,14;
+RST_DLY_5_ = node,-,-,B,9;
+RST_DLY_6_ = node,-,-,C,2;
+RST_DLY_7_ = node,-,-,C,10;
+CLK_000_P_SYNC_0_ = node,-,-,D,10;
+CLK_000_P_SYNC_1_ = node,-,-,C,11;
+CLK_000_P_SYNC_2_ = node,-,-,B,11;
+CLK_000_P_SYNC_3_ = node,-,-,C,7;
+CLK_000_P_SYNC_4_ = node,-,-,D,6;
+CLK_000_P_SYNC_5_ = node,-,-,F,10;
+CLK_000_P_SYNC_6_ = node,-,-,A,3;
+CLK_000_P_SYNC_7_ = node,-,-,A,14;
+CLK_000_P_SYNC_8_ = node,-,-,A,10;
+CLK_000_N_SYNC_0_ = node,-,-,F,6;
+CLK_000_N_SYNC_1_ = node,-,-,G,7;
+CLK_000_N_SYNC_2_ = node,-,-,G,3;
+CLK_000_N_SYNC_3_ = node,-,-,B,7;
+CLK_000_N_SYNC_4_ = node,-,-,B,3;
+pos_clk_un29_clk_000_ne_d0_i_n = node,-,-,D,2;
+CLK_000_N_SYNC_5_ = node,-,-,B,14;
+CLK_000_N_SYNC_6_ = node,-,-,A,6;
+CLK_000_N_SYNC_7_ = node,-,-,B,10;
+CLK_000_N_SYNC_8_ = node,-,-,G,14;
+CLK_000_N_SYNC_9_ = node,-,-,F,2;
 CLK_000_N_SYNC_10_ = node,-,-,H,2;
-inst_CLK_030_H = node,-,-,A,2;
-SM_AMIGA_1_ = node,-,-,F,1;
-SM_AMIGA_4_ = node,-,-,F,10;
-SM_AMIGA_2_ = node,-,-,F,2;
-inst_DS_000_ENABLE = node,-,-,C,12;
-SM_AMIGA_i_7_ = node,-,-,F,0;
+inst_CLK_030_H = node,-,-,A,9;
+SM_AMIGA_1_ = node,-,-,C,1;
+SM_AMIGA_4_ = node,-,-,F,1;
+SM_AMIGA_2_ = node,-,-,C,13;
+inst_DS_000_ENABLE = node,-,-,A,12;
+SM_AMIGA_i_7_ = node,-,-,F,8;
+CIIN_0 = node,-,-,E,5;
 
 [GROUP ASSIGNMENTS]
 Layer = OFF;

Logic/68030_tk.out

@@ -2388,6 +2388,604 @@
   14      A_28_  1   -1  -1   1              4           14   -1
   13 nEXP_SPACE  1   -1  -1   1                    6     13   -1
   10    CLK_000  1   -1  -1   1                    6     10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4  0     2        5     7  40   -1   1   0   21
+  79     RW_000  5  366   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  376   6   2  0                    7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  367   6   1                    6     68   -1   3   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1                    6     78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1                    6     69   -1   1   0   21
+   8 IPL_030_2_  5  365   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  371   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  370   1   0                           6   -1  10   0   21
+  65          E  5  373   6   0                          65   -1   5   0   21
+  80     DSACK1  5  372   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  369   7   0                          82   -1   3   0   21
+  34        VMA  5  374   3   0                          34   -1   3   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  368   3   0                          28   -1   2   0   21
+   2      RESET  5  375   1   0                           2   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+ 369 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 375   RN_RESET  3    2   1   6  0  1     3  4     6  7   2   -1   2   0   21
+ 299 inst_nEXP_SPACE_D0reg  3   -1   5   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 319 inst_CLK_000_NE  3   -1   2   5  0  1  2  3     5        -1   -1   1   0   21
+ 317 inst_CLK_000_PE  3   -1   3   5  0     2  3     5     7  -1   -1   1   0   21
+ 298 inst_AS_030_D0  3   -1   7   5  0        3  4  5     7  -1   -1   1   0   21
+ 326 inst_CLK_000_NE_D0  3   -1   1   4        2  3     5  6     -1   -1   1   0   21
+ 364 SM_AMIGA_i_7_  3   -1   5   3           3     5     7  -1   -1  14   0   21
+ 373       RN_E  3   65   6   3        2  3        6     65   -1   5   0   21
+ 325 SM_AMIGA_3_  3   -1   2   3  0     2        5        -1   -1   5   0   21
+ 294 cpu_est_1_  3   -1   3   3        2  3        6     -1   -1   5   0   21
+ 321 cpu_est_2_  3   -1   3   3        2  3        6     -1   -1   4   0   21
+ 359 SM_AMIGA_1_  3   -1   5   3  0              5     7  -1   -1   3   0   21
+ 296 SM_AMIGA_5_  3   -1   5   3  0              5     7  -1   -1   3   0   21
+ 327 SM_AMIGA_0_  3   -1   0   3  0              5     7  -1   -1   2   0   21
+ 293 cpu_est_0_  3   -1   3   3        2  3        6     -1   -1   2   0   21
+ 302 inst_BGACK_030_INT_D  3   -1   7   3  0              5  6     -1   -1   1   0   21
+ 303 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 333 RST_DLY_3_  3   -1   2   2     1  2                 -1   -1   6   0   21
+ 332 RST_DLY_2_  3   -1   2   2     1  2                 -1   -1   5   0   21
+ 361 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 335 RST_DLY_5_  3   -1   1   2     1  2                 -1   -1   4   0   21
+ 331 RST_DLY_1_  3   -1   2   2     1  2                 -1   -1   4   0   21
+ 311 inst_LDS_000_INT  3   -1   6   2           3        6     -1   -1   4   0   21
+ 374     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 362 inst_DS_000_ENABLE  3   -1   0   2  0        3              -1   -1   3   0   21
+ 360 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 336 RST_DLY_6_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 330 RST_DLY_0_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 329 SM_AMIGA_6_  3   -1   5   2                 5  6     -1   -1   3   0   21
+ 310 inst_UDS_000_INT  3   -1   6   2           3        6     -1   -1   3   0   21
+ 308 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 307 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 337 RST_DLY_7_  3   -1   1   2     1  2                 -1   -1   2   0   21
+ 334 RST_DLY_4_  3   -1   2   2     1  2                 -1   -1   2   1   21
+ 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   0   2  0        3              -1   -1   2   0   21
+ 297 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   6   2        2           6     -1   -1   2   0   21
+ 295 inst_AS_000_INT  3   -1   0   2  0           4           -1   -1   2   0   21
+ 316 inst_CLK_000_D0  3   -1   6   2           3     5        -1   -1   1   0   21
+ 309 inst_VPA_D  3   -1   1   2        2  3              -1   -1   1   0   21
+ 371 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 370 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 365 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 304 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 358 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 301 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 372  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 367      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 366  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 306 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 376      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 368  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 363 pos_clk_un23_clk_000_ne_d0_0_n  3   -1   2   1                 5        -1   -1   2   0   21
+ 305 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 357 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 356 CLK_000_N_SYNC_9_  3   -1   5   1                       7  -1   -1   1   0   21
+ 355 CLK_000_N_SYNC_8_  3   -1   2   1                 5        -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_7_  3   -1   4   1        2                 -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_6_  3   -1   1   1              4           -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_5_  3   -1   4   1     1                    -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_4_  3   -1   3   1              4           -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_3_  3   -1   1   1           3              -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_2_  3   -1   3   1     1                    -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_1_  3   -1   4   1           3              -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_0_  3   -1   5   1              4           -1   -1   1   0   21
+ 346 CLK_000_P_SYNC_8_  3   -1   0   1                    6     -1   -1   1   0   21
+ 345 CLK_000_P_SYNC_7_  3   -1   1   1  0                       -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_6_  3   -1   3   1     1                    -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_5_  3   -1   1   1           3              -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_4_  3   -1   2   1     1                    -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_3_  3   -1   1   1        2                 -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_2_  3   -1   2   1     1                    -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_1_  3   -1   0   1        2                 -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_0_  3   -1   5   1  0                       -1   -1   1   0   21
+ 324  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 323  IPL_D0_1_  3   -1   3   1     1                    -1   -1   1   0   21
+ 322  IPL_D0_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 320 CLK_000_N_SYNC_11_  3   -1   7   1        2                 -1   -1   1   0   21
+ 318 CLK_000_P_SYNC_9_  3   -1   6   1           3              -1   -1   1   0   21
+ 315 inst_CLK_000_D1  3   -1   5   1                 5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_50  3   -1   6   1                    6     -1   -1   1   0   21
+ 313 inst_DTACK_D0  3   -1   3   1        2                 -1   -1   1   0   21
+ 312 inst_CLK_OUT_PRE_D  3   -1   6   1                       7  -1   -1   1   0   21
+ 300 inst_DS_030_D0  3   -1   3   1                    6     -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  63    CLK_030  1   -1  -1   3  0  1                 7  63   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  59         A1  1   -1  -1   2  0                 6     59   -1
+  55     IPL_1_  1   -1  -1   2     1     3              55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  66     IPL_0_  1   -1  -1   1     1                    66   -1
+  35        VPA  1   -1  -1   1     1                    35   -1
+  29      DTACK  1   -1  -1   1           3              29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1                    6     10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4        2        5  6  7  40   -1   1   0   21
+  79     RW_000  5  366   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  376   6   2                    6  7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  367   6   1  0                       68   -1   3   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  365   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  371   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  370   1   0                           6   -1  10   0   21
+  65          E  5  373   6   0                          65   -1   5   0   21
+  80     DSACK1  5  372   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  369   7   0                          82   -1   3   0   21
+  34        VMA  5  374   3   0                          34   -1   3   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  368   3   0                          28   -1   2   0   21
+   2      RESET  5  375   1   0                           2   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+ 369 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 375   RN_RESET  3    2   1   6  0  1     3  4     6  7   2   -1   2   0   21
+ 299 inst_nEXP_SPACE_D0reg  3   -1   5   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 317 inst_CLK_000_PE  3   -1   0   5  0     2  3     5     7  -1   -1   1   0   21
+ 298 inst_AS_030_D0  3   -1   7   5           3  4  5  6  7  -1   -1   1   0   21
+ 319 inst_CLK_000_NE  3   -1   1   4     1  2  3     5        -1   -1   1   0   21
+ 302 inst_BGACK_030_INT_D  3   -1   7   4  0        3     5  6     -1   -1   1   0   21
+ 364 SM_AMIGA_i_7_  3   -1   5   3           3     5     7  -1   -1  13   0   21
+ 373       RN_E  3   65   6   3        2  3        6     65   -1   5   0   21
+ 325 SM_AMIGA_3_  3   -1   2   3        2        5  6     -1   -1   5   0   21
+ 294 cpu_est_1_  3   -1   2   3        2  3        6     -1   -1   5   0   21
+ 321 cpu_est_2_  3   -1   2   3        2  3        6     -1   -1   4   0   21
+ 296 SM_AMIGA_5_  3   -1   5   3                 5  6  7  -1   -1   3   0   21
+ 293 cpu_est_0_  3   -1   6   3        2  3        6     -1   -1   2   0   21
+ 312 inst_CLK_OUT_PRE_D  3   -1   6   3     1              6  7  -1   -1   1   0   21
+ 303 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 334 RST_DLY_3_  3   -1   2   2     1  2                 -1   -1   6   0   21
+ 333 RST_DLY_2_  3   -1   2   2     1  2                 -1   -1   5   0   21
+ 362 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 336 RST_DLY_5_  3   -1   1   2     1  2                 -1   -1   4   0   21
+ 332 RST_DLY_1_  3   -1   2   2     1  2                 -1   -1   4   0   21
+ 311 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   4   0   21
+ 374     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 363 inst_DS_000_ENABLE  3   -1   6   2           3        6     -1   -1   3   0   21
+ 361 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 360 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 337 RST_DLY_6_  3   -1   1   2     1  2                 -1   -1   3   0   21
+ 330 RST_DLY_0_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 329 SM_AMIGA_6_  3   -1   5   2  0              5        -1   -1   3   0   21
+ 310 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 308 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 307 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 338 RST_DLY_7_  3   -1   2   2     1  2                 -1   -1   2   0   21
+ 335 RST_DLY_4_  3   -1   2   2     1  2                 -1   -1   2   1   21
+ 327 SM_AMIGA_0_  3   -1   5   2                 5     7  -1   -1   2   0   21
+ 297 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   0   2  0     2                 -1   -1   2   0   21
+ 295 inst_AS_000_INT  3   -1   6   2              4     6     -1   -1   2   0   21
+ 326 inst_CLK_000_NE_D0  3   -1   2   2        2           6     -1   -1   1   0   21
+ 316 inst_CLK_000_D0  3   -1   1   2           3     5        -1   -1   1   0   21
+ 309 inst_VPA_D  3   -1   5   2        2  3              -1   -1   1   0   21
+ 371 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 370 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 365 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 304 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 359 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 301 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 372  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 367      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 366  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 306 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 376      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 368  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 331    N_264_i  3   -1   2   1                 5        -1   -1   2   0   21
+ 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   3   1           3              -1   -1   2   0   21
+ 305 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 358 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 357 CLK_000_N_SYNC_9_  3   -1   1   1                       7  -1   -1   1   0   21
+ 356 CLK_000_N_SYNC_8_  3   -1   0   1     1                    -1   -1   1   0   21
+ 355 CLK_000_N_SYNC_7_  3   -1   3   1  0                       -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_6_  3   -1   4   1           3              -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_5_  3   -1   1   1              4           -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_4_  3   -1   4   1     1                    -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_3_  3   -1   1   1              4           -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_1_  3   -1   2   1     1                    -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_0_  3   -1   5   1        2                 -1   -1   1   0   21
+ 347 CLK_000_P_SYNC_8_  3   -1   6   1              4           -1   -1   1   0   21
+ 346 CLK_000_P_SYNC_7_  3   -1   1   1                    6     -1   -1   1   0   21
+ 345 CLK_000_P_SYNC_6_  3   -1   2   1     1                    -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_5_  3   -1   3   1        2                 -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_4_  3   -1   4   1           3              -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_3_  3   -1   3   1              4           -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_2_  3   -1   6   1           3              -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_1_  3   -1   1   1                    6     -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_0_  3   -1   5   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_2_  3   -1   0   1     1                    -1   -1   1   0   21
+ 323  IPL_D0_1_  3   -1   2   1     1                    -1   -1   1   0   21
+ 322  IPL_D0_0_  3   -1   3   1     1                    -1   -1   1   0   21
+ 320 CLK_000_N_SYNC_11_  3   -1   7   1     1                    -1   -1   1   0   21
+ 318 CLK_000_P_SYNC_9_  3   -1   4   1  0                       -1   -1   1   0   21
+ 315 inst_CLK_000_D1  3   -1   3   1                 5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_50  3   -1   6   1                    6     -1   -1   1   0   21
+ 313 inst_DTACK_D0  3   -1   0   1        2                 -1   -1   1   0   21
+ 300 inst_DS_030_D0  3   -1   3   1  0                       -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2  0  1                    67   -1
+  66     IPL_0_  1   -1  -1   2     1     3              66   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  59         A1  1   -1  -1   2  0        3              59   -1
+  55     IPL_1_  1   -1  -1   2     1  2                 55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  35        VPA  1   -1  -1   1                 5        35   -1
+  29      DTACK  1   -1  -1   1  0                       29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+146 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   6     1  2  3     5  6  7  40   -1   1   0   21
+  79     RW_000  5  367   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  377   6   2           3           7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  368   6   1  0                       68   -1   3   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  366   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  372   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  371   1   0                           6   -1  10   0   21
+  65          E  5  374   6   0                          65   -1   5   0   21
+  80     DSACK1  5  373   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  370   7   0                          82   -1   3   0   21
+  34        VMA  5  375   3   0                          34   -1   3   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  369   3   0                          28   -1   2   0   21
+   2      RESET  5  376   1   0                           2   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+ 370 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 376   RN_RESET  3    2   1   6  0  1     3  4     6  7   2   -1   2   0   21
+ 317 inst_CLK_000_PE  3   -1   2   6  0  1  2  3     5     7  -1   -1   1   0   21
+ 299 inst_nEXP_SPACE_D0reg  3   -1   1   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 296 SM_AMIGA_5_  3   -1   1   5     1     3     5  6  7  -1   -1   3   0   21
+ 298 inst_AS_030_D0  3   -1   7   5           3  4  5  6  7  -1   -1   1   0   21
+ 319 inst_CLK_000_NE  3   -1   0   4     1  2  3     5        -1   -1   1   0   21
+ 364 SM_AMIGA_i_7_  3   -1   5   3           3     5     7  -1   -1  13   0   21
+ 374       RN_E  3   65   6   3        2  3        6     65   -1   5   0   21
+ 325 SM_AMIGA_3_  3   -1   2   3        2  3     5        -1   -1   5   0   21
+ 294 cpu_est_1_  3   -1   3   3        2  3        6     -1   -1   5   0   21
+ 321 cpu_est_2_  3   -1   3   3        2  3        6     -1   -1   4   0   21
+ 361 SM_AMIGA_4_  3   -1   3   3        2  3     5        -1   -1   3   0   21
+ 329 SM_AMIGA_6_  3   -1   5   3  0  1           5        -1   -1   3   0   21
+ 308 SIZE_DMA_1_  3   -1   0   3  0                 6  7  -1   -1   3   0   21
+ 293 cpu_est_0_  3   -1   2   3        2  3        6     -1   -1   2   0   21
+ 326 inst_CLK_000_NE_D0  3   -1   5   3        2  3        6     -1   -1   1   0   21
+ 316 inst_CLK_000_D0  3   -1   4   3           3  4  5        -1   -1   1   0   21
+ 312 inst_CLK_OUT_PRE_D  3   -1   1   3     1              6  7  -1   -1   1   0   21
+ 302 inst_BGACK_030_INT_D  3   -1   7   3  0              5  6     -1   -1   1   0   21
+ 303 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 333 RST_DLY_3_  3   -1   1   2     1  2                 -1   -1   6   0   21
+ 332 RST_DLY_2_  3   -1   2   2     1  2                 -1   -1   5   0   21
+ 362 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 335 RST_DLY_5_  3   -1   2   2     1  2                 -1   -1   4   0   21
+ 331 RST_DLY_1_  3   -1   2   2     1  2                 -1   -1   4   0   21
+ 311 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   4   0   21
+ 375     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 360 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 336 RST_DLY_6_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 330 RST_DLY_0_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 310 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 307 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 337 RST_DLY_7_  3   -1   2   2     1  2                 -1   -1   2   0   21
+ 334 RST_DLY_4_  3   -1   1   2     1  2                 -1   -1   2   1   21
+ 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   0   2  0        3              -1   -1   2   0   21
+ 327 SM_AMIGA_0_  3   -1   5   2                 5     7  -1   -1   2   0   21
+ 297 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   0   2  0     2                 -1   -1   2   0   21
+ 295 inst_AS_000_INT  3   -1   6   2              4     6     -1   -1   2   0   21
+ 309 inst_VPA_D  3   -1   6   2        2  3              -1   -1   1   0   21
+ 372 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 371 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 366 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 304 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 359 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 301 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 373  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 368      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 367  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 363 inst_DS_000_ENABLE  3   -1   3   1           3              -1   -1   3   0   21
+ 306 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 377      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 369  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 365     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 338    N_203_i  3   -1   2   1                 5        -1   -1   2   0   21
+ 305 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 358 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 357 CLK_000_N_SYNC_9_  3   -1   4   1                       7  -1   -1   1   0   21
+ 356 CLK_000_N_SYNC_8_  3   -1   3   1              4           -1   -1   1   0   21
+ 355 CLK_000_N_SYNC_7_  3   -1   6   1           3              -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_6_  3   -1   0   1                    6     -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_5_  3   -1   6   1  0                       -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_4_  3   -1   2   1                    6     -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_3_  3   -1   1   1        2                 -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_1_  3   -1   2   1     1                    -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_0_  3   -1   5   1        2                 -1   -1   1   0   21
+ 347 CLK_000_P_SYNC_8_  3   -1   5   1        2                 -1   -1   1   0   21
+ 346 CLK_000_P_SYNC_7_  3   -1   3   1                 5        -1   -1   1   0   21
+ 345 CLK_000_P_SYNC_6_  3   -1   5   1           3              -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_5_  3   -1   6   1                 5        -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_4_  3   -1   1   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_3_  3   -1   6   1     1                    -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_2_  3   -1   6   1                    6     -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_1_  3   -1   6   1                    6     -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_0_  3   -1   5   1                    6     -1   -1   1   0   21
+ 324  IPL_D0_2_  3   -1   3   1     1                    -1   -1   1   0   21
+ 323  IPL_D0_1_  3   -1   5   1     1                    -1   -1   1   0   21
+ 322  IPL_D0_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 320 CLK_000_N_SYNC_11_  3   -1   7   1  0                       -1   -1   1   0   21
+ 318 CLK_000_P_SYNC_9_  3   -1   2   1        2                 -1   -1   1   0   21
+ 315 inst_CLK_000_D1  3   -1   4   1                 5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_50  3   -1   1   1     1                    -1   -1   1   0   21
+ 313 inst_DTACK_D0  3   -1   2   1        2                 -1   -1   1   0   21
+ 300 inst_DS_030_D0  3   -1   3   1  0                       -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2     1     3              67   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  55     IPL_1_  1   -1  -1   2     1           5        55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  66     IPL_0_  1   -1  -1   1     1                    66   -1
+  59         A1  1   -1  -1   1  0                       59   -1
+  35        VPA  1   -1  -1   1                    6     35   -1
+  29      DTACK  1   -1  -1   1        2                 29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1     1                    13   -1
+  10    CLK_000  1   -1  -1   1              4           10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+146 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4  0     2        5     7  40   -1   1   0   21
+  79     RW_000  5  367   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  377   6   2  0                    7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  368   6   1                    6     68   -1   3   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1                    6     78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1                    6     69   -1   1   0   21
+   8 IPL_030_2_  5  366   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  372   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  371   1   0                           6   -1  10   0   21
+  65          E  5  374   6   0                          65   -1   5   0   21
+  80     DSACK1  5  373   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  370   7   0                          82   -1   3   0   21
+  34        VMA  5  375   3   0                          34   -1   3   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  369   3   0                          28   -1   2   0   21
+   2      RESET  5  376   1   0                           2   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+ 370 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 376   RN_RESET  3    2   1   6  0  1     3  4     6  7   2   -1   2   0   21
+ 299 inst_nEXP_SPACE_D0reg  3   -1   5   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 319 inst_CLK_000_NE  3   -1   5   5     1  2  3  4  5        -1   -1   1   0   21
+ 317 inst_CLK_000_PE  3   -1   2   5  0     2  3     5     7  -1   -1   1   0   21
+ 298 inst_AS_030_D0  3   -1   7   5  0        3  4  5     7  -1   -1   1   0   21
+ 364 SM_AMIGA_i_7_  3   -1   5   3           3     5     7  -1   -1  13   0   21
+ 374       RN_E  3   65   6   3        2  3        6     65   -1   5   0   21
+ 325 SM_AMIGA_3_  3   -1   2   3  0     2        5        -1   -1   5   0   21
+ 294 cpu_est_1_  3   -1   6   3        2  3        6     -1   -1   5   0   21
+ 321 cpu_est_2_  3   -1   2   3        2  3        6     -1   -1   4   0   21
+ 360 SM_AMIGA_1_  3   -1   2   3        2        5     7  -1   -1   3   0   21
+ 296 SM_AMIGA_5_  3   -1   5   3  0              5     7  -1   -1   3   0   21
+ 293 cpu_est_0_  3   -1   2   3        2  3        6     -1   -1   2   0   21
+ 326 inst_CLK_000_NE_D0  3   -1   4   3        2  3        6     -1   -1   1   0   21
+ 302 inst_BGACK_030_INT_D  3   -1   7   3        2        5  6     -1   -1   1   0   21
+ 303 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 333 RST_DLY_3_  3   -1   2   2     1  2                 -1   -1   6   0   21
+ 332 RST_DLY_2_  3   -1   1   2     1  2                 -1   -1   5   0   21
+ 362 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 335 RST_DLY_5_  3   -1   1   2     1  2                 -1   -1   4   0   21
+ 331 RST_DLY_1_  3   -1   1   2     1  2                 -1   -1   4   0   21
+ 311 inst_LDS_000_INT  3   -1   6   2           3        6     -1   -1   4   0   21
+ 375     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 363 inst_DS_000_ENABLE  3   -1   0   2  0        3              -1   -1   3   0   21
+ 361 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 336 RST_DLY_6_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 330 RST_DLY_0_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 329 SM_AMIGA_6_  3   -1   5   2                 5  6     -1   -1   3   0   21
+ 310 inst_UDS_000_INT  3   -1   6   2           3        6     -1   -1   3   0   21
+ 308 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 307 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 337 RST_DLY_7_  3   -1   2   2     1  2                 -1   -1   2   0   21
+ 334 RST_DLY_4_  3   -1   2   2     1  2                 -1   -1   2   1   21
+ 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   6   2           3        6     -1   -1   2   0   21
+ 327 SM_AMIGA_0_  3   -1   5   2                 5     7  -1   -1   2   0   21
+ 295 inst_AS_000_INT  3   -1   0   2  0           4           -1   -1   2   0   21
+ 316 inst_CLK_000_D0  3   -1   1   2           3     5        -1   -1   1   0   21
+ 315 inst_CLK_000_D1  3   -1   3   2           3     5        -1   -1   1   0   21
+ 313 inst_DTACK_D0  3   -1   1   2        2  3              -1   -1   1   0   21
+ 309 inst_VPA_D  3   -1   3   2        2  3              -1   -1   1   0   21
+ 372 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 371 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 366 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 304 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 359 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 301 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 373  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 368      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 367  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 306 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 377      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 369  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 365     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 352 pos_clk_un29_clk_000_ne_d0_i_n  3   -1   3   1                 5        -1   -1   2   0   21
+ 305 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 297 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   2   1        2                 -1   -1   2   0   21
+ 358 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 357 CLK_000_N_SYNC_9_  3   -1   5   1                       7  -1   -1   1   0   21
+ 356 CLK_000_N_SYNC_8_  3   -1   6   1                 5        -1   -1   1   0   21
+ 355 CLK_000_N_SYNC_7_  3   -1   1   1                    6     -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_6_  3   -1   0   1     1                    -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_5_  3   -1   1   1  0                       -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_4_  3   -1   1   1     1                    -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_3_  3   -1   1   1     1                    -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_2_  3   -1   6   1     1                    -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_1_  3   -1   6   1                    6     -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_0_  3   -1   5   1                    6     -1   -1   1   0   21
+ 346 CLK_000_P_SYNC_8_  3   -1   0   1  0                       -1   -1   1   0   21
+ 345 CLK_000_P_SYNC_7_  3   -1   0   1  0                       -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_6_  3   -1   0   1  0                       -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_5_  3   -1   5   1  0                       -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_4_  3   -1   3   1                 5        -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_3_  3   -1   2   1           3              -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_2_  3   -1   1   1        2                 -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_1_  3   -1   2   1     1                    -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_0_  3   -1   3   1        2                 -1   -1   1   0   21
+ 324  IPL_D0_2_  3   -1   6   1     1                    -1   -1   1   0   21
+ 323  IPL_D0_1_  3   -1   3   1     1                    -1   -1   1   0   21
+ 322  IPL_D0_0_  3   -1   3   1     1                    -1   -1   1   0   21
+ 320 CLK_000_N_SYNC_11_  3   -1   7   1                 5        -1   -1   1   0   21
+ 318 CLK_000_P_SYNC_9_  3   -1   0   1        2                 -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_50  3   -1   4   1              4           -1   -1   1   0   21
+ 312 inst_CLK_OUT_PRE_D  3   -1   4   1                       7  -1   -1   1   0   21
+ 300 inst_DS_030_D0  3   -1   3   1                    6     -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  63    CLK_030  1   -1  -1   3  0  1                 7  63   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2     1              6     67   -1
+  66     IPL_0_  1   -1  -1   2     1     3              66   -1
+  59         A1  1   -1  -1   2        2           6     59   -1
+  55     IPL_1_  1   -1  -1   2     1     3              55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  35        VPA  1   -1  -1   1           3              35   -1
+  29      DTACK  1   -1  -1   1     1                    29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
    5      A_29_  1   -1  -1   1              4            5   -1
    4      A_30_  1   -1  -1   1              4            4   -1
    3      A_31_  1   -1  -1   1              4            3   -1

Logic/68030_tk.plc

@@ -8,29 +8,30 @@
 ; Source file 68030_tk.tt4
 ; FITTER-generated Placements.
 ; DEVICE   mach447a
-; DATE     Thu Jul 09 18:49:07 2015
+; DATE     Thu Sep 24 16:21:08 2015
 
 
-Pin   70  SIZE_0_ Comb ; S6=1  S9=1  Pair 263
-Pin   5  A_30_
-Pin   79  SIZE_1_ Comb ; S6=1  S9=1  Pair 287
-Pin   6  A_29_
 Pin   15  A_28_
-Pin   4  A_31_
 Pin   16  A_27_
+Pin   79  SIZE_1_ Comb ; S6=1  S9=1  Pair 287
 Pin   17  A_26_
 Pin   18  A_25_
+Pin   4  A_31_
 Pin   19  A_24_
+Pin   85  A_23_
+Pin   84  A_22_
+Pin   94  A_21_
 Pin   68  IPL_2_
-Pin   58  FC_1_
-Pin   82  AS_030 Comb ; S6=1  S9=1  Pair 281
-Pin   42  AS_000 Comb ; S6=1  S9=1  Pair 203
+Pin   93  A_20_
 Pin   97  A_19_
+Pin   58  FC_1_
 Pin   95  A_18_
-Pin   98  DS_030 Comb ; S6=1  S9=1  Pair 101
+Pin   82  AS_030 Comb ; S6=1  S9=1  Pair 281
 Pin   59  A_17_
-Pin   32  UDS_000 Comb ; S6=1  S9=1  Pair 185
+Pin   42  AS_000 Comb ; S6=1  S9=1  Pair 203
 Pin   96  A_16_
+Pin   98  DS_030 Comb ; S6=1  S9=1  Pair 101
+Pin   32  UDS_000 Comb ; S6=1  S9=1  Pair 185
 Pin   31  LDS_000 Comb ; S6=1  S9=1  Pair 191
 Pin   60  A1
 Pin   14  nEXP_SPACE
@@ -42,13 +43,13 @@ Pin   11  CLK_000
 Pin   61  CLK_OSZI
 Pin   65  CLK_DIV_OUT Comb ; S6=1  S9=1  Pair 247
 Pin   10  CLK_EXP Comb ; S6=1  S9=1  Pair 127
-Pin   78  FPU_CS Comb ; S6=1  S9=1  Pair 271
-Pin   91  FPU_SENSE
 Pin   56  IPL_1_
-Pin   30  DTACK
+Pin   78  FPU_CS Comb ; S6=1  S9=1  Pair 271
 Pin   67  IPL_0_
-Pin   92  AVEC Comb ; S6=1  S9=1  Pair 107
+Pin   91  FPU_SENSE
 Pin   57  FC_0_
+Pin   30  DTACK
+Pin   92  AVEC Comb ; S6=1  S9=1  Pair 107
 Pin   36  VPA
 Pin   86  RST
 Pin   33  AMIGA_ADDR_ENABLE Comb ; S6=1  S9=1  Pair 181
@@ -56,19 +57,21 @@ Pin   48  AMIGA_BUS_DATA_DIR Comb ; S6=1  S9=1  Pair 199
 Pin   20  AMIGA_BUS_ENABLE_LOW Comb ; S6=1  S9=1  Pair 149
 Pin   34  AMIGA_BUS_ENABLE_HIGH Comb ; S6=1  S9=1  Pair 179
 Pin   47  CIIN Comb ; S6=1  S9=1  Pair 215
-Pin   9  IPL_030_2_ Reg  ; S6=1  S9=1  Pair 128
+Pin   70  SIZE_0_ Comb ; S6=1  S9=1  Pair 263
+Pin   5  A_30_
+Pin   6  A_29_
+Pin   9  IPL_030_2_ Reg  ; S6=1  S9=1  Pair 131
 Pin   80  RW_000 Reg  ; S6=1  S9=1  Pair 269
 Pin   69  A0 Reg  ; S6=1  S9=1  Pair 257
 Pin   29  BG_000 Reg  ; S6=1  S9=1  Pair 175
 Pin   83  BGACK_030 Reg  ; S6=1  S9=1  Pair 275
-Pin   7  IPL_030_1_ Reg  ; S6=1  S9=1  Pair 134
+Pin   7  IPL_030_1_ Reg  ; S6=1  S9=1  Pair 143
 Pin   8  IPL_030_0_ Reg  ; S6=1  S9=1  Pair 137
 Pin   81  DSACK1 Reg  ; S6=1  S9=1  Pair 283
 Pin   66  E Reg  ; S6=1  S9=1  Pair 251
 Pin   35  VMA Reg  ; S6=1  S9=1  Pair 173
-Pin   3  RESET Reg  ; S6=1  S9=1  Pair 146
+Pin   3  RESET Reg  ; S6=1  S9=1  Pair 125
 Pin   71  RW Reg  ; S6=1  S9=1  Pair 245
-Node  263  RN_SIZE_0_ Comb ; S6=1  S9=1 
 Node  287  RN_SIZE_1_ Comb ; S6=1  S9=1 
 Node  281  RN_AS_030 Comb ; S6=1  S9=1 
 Node  203  RN_AS_000 Comb ; S6=1  S9=1 
@@ -76,89 +79,91 @@ Node  101  RN_DS_030 Comb ; S6=1  S9=1
 Node  185  RN_UDS_000 Comb ; S6=1  S9=1 
 Node  191  RN_LDS_000 Comb ; S6=1  S9=1 
 Node  197  RN_BERR Comb ; S6=1  S9=1 
-Node  128  RN_IPL_030_2_ Reg  ; S6=1  S9=1 
+Node  263  RN_SIZE_0_ Comb ; S6=1  S9=1 
+Node  131  RN_IPL_030_2_ Reg  ; S6=1  S9=1 
 Node  269  RN_RW_000 Reg  ; S6=1  S9=1 
 Node  257  RN_A0 Reg  ; S6=1  S9=1 
 Node  175  RN_BG_000 Reg  ; S6=1  S9=1 
 Node  275  RN_BGACK_030 Reg  ; S6=1  S9=1 
-Node  134  RN_IPL_030_1_ Reg  ; S6=1  S9=1 
+Node  143  RN_IPL_030_1_ Reg  ; S6=1  S9=1 
 Node  137  RN_IPL_030_0_ Reg  ; S6=1  S9=1 
 Node  283  RN_DSACK1 Reg  ; S6=1  S9=1 
 Node  251  RN_E Reg  ; S6=1  S9=1 
 Node  173  RN_VMA Reg  ; S6=1  S9=1 
-Node  146  RN_RESET Reg  ; S6=1  S9=1 
+Node  125  RN_RESET Reg  ; S6=1  S9=1 
 Node  245  RN_RW Reg  ; S6=1  S9=1 
-Node  230  N_165 Comb ; S6=1  S9=1 
-Node  182  cpu_est_0_ Reg  ; S6=1  S9=1 
-Node  193  cpu_est_1_ Reg  ; S6=1  S9=1 
-Node  151  inst_AS_000_INT Reg  ; S6=1  S9=1 
-Node  227  SM_AMIGA_5_ Reg  ; S6=1  S9=1 
-Node  266  inst_AMIGA_BUS_ENABLE_DMA_LOW Reg  ; S6=1  S9=1 
+Node  157  cpu_est_0_ Reg  ; S6=1  S9=1 
+Node  253  cpu_est_1_ Reg  ; S6=1  S9=1 
+Node  103  inst_AS_000_INT Reg  ; S6=1  S9=1 
+Node  239  SM_AMIGA_5_ Reg  ; S6=1  S9=1 
+Node  154  inst_AMIGA_BUS_ENABLE_DMA_LOW Reg  ; S6=1  S9=1 
 Node  277  inst_AS_030_D0 Reg  ; S6=1  S9=1 
-Node  253  inst_nEXP_SPACE_D0reg Reg  ; S6=1  S9=1 
-Node  188  inst_DS_030_D0 Reg  ; S6=1  S9=1 
-Node  161  inst_AS_030_000_SYNC Reg  ; S6=1  S9=1 
+Node  221  inst_nEXP_SPACE_D0reg Reg  ; S6=1  S9=1 
+Node  184  inst_DS_030_D0 Reg  ; S6=1  S9=1 
+Node  241  inst_AS_030_000_SYNC Reg  ; S6=1  S9=1 
 Node  289  inst_BGACK_030_INT_D Reg  ; S6=1  S9=1 
 Node  113  inst_AS_000_DMA Reg  ; S6=1  S9=1 
-Node  121  inst_DS_000_DMA Reg  ; S6=1  S9=1 
-Node  116  CYCLE_DMA_0_ Reg  ; S6=1  S9=1 
-Node  110  CYCLE_DMA_1_ Reg  ; S6=1  S9=1 
+Node  109  inst_DS_000_DMA Reg  ; S6=1  S9=1 
+Node  104  CYCLE_DMA_0_ Reg  ; S6=1  S9=1 
+Node  121  CYCLE_DMA_1_ Reg  ; S6=1  S9=1 
 Node  254  SIZE_DMA_0_ Reg  ; S6=1  S9=1 
 Node  248  SIZE_DMA_1_ Reg  ; S6=1  S9=1 
-Node  241  inst_VPA_D Reg  ; S6=1  S9=1 
-Node  229  inst_UDS_000_INT Reg  ; S6=1  S9=1 
-Node  139  inst_LDS_000_INT Reg  ; S6=1  S9=1 
-Node  268  inst_CLK_OUT_PRE_D Reg  ; S6=1  S9=1 
-Node  196  inst_DTACK_D0 Reg  ; S6=1  S9=1 
-Node  115  inst_CLK_OUT_PRE_50 Reg  ; S6=1  S9=1 
-Node  233  inst_CLK_000_D1 Reg  ; S6=1  S9=1 
-Node  265  inst_CLK_000_D0 Reg  ; S6=1  S9=1 
-Node  187  inst_CLK_000_PE Reg  ; S6=1  S9=1 
-Node  152  CLK_000_P_SYNC_9_ Reg  ; S6=1  S9=1 
-Node  259  inst_CLK_000_NE Reg  ; S6=1  S9=1 
+Node  193  inst_VPA_D Reg  ; S6=1  S9=1 
+Node  265  inst_UDS_000_INT Reg  ; S6=1  S9=1 
+Node  259  inst_LDS_000_INT Reg  ; S6=1  S9=1 
+Node  217  inst_CLK_OUT_PRE_D Reg  ; S6=1  S9=1 
+Node  134  inst_DTACK_D0 Reg  ; S6=1  S9=1 
+Node  211  inst_CLK_OUT_PRE_50 Reg  ; S6=1  S9=1 
+Node  187  inst_CLK_000_D1 Reg  ; S6=1  S9=1 
+Node  128  inst_CLK_000_D0 Reg  ; S6=1  S9=1 
+Node  155  inst_CLK_000_PE Reg  ; S6=1  S9=1 
+Node  112  CLK_000_P_SYNC_9_ Reg  ; S6=1  S9=1 
+Node  227  inst_CLK_000_NE Reg  ; S6=1  S9=1 
 Node  278  CLK_000_N_SYNC_11_ Reg  ; S6=1  S9=1 
-Node  176  cpu_est_2_ Reg  ; S6=1  S9=1 
-Node  136  IPL_D0_0_ Reg  ; S6=1  S9=1 
-Node  169  IPL_D0_1_ Reg  ; S6=1  S9=1 
-Node  145  IPL_D0_2_ Reg  ; S6=1  S9=1 
-Node  239  SM_AMIGA_3_ Reg  ; S6=1  S9=1 
-Node  148  inst_CLK_000_NE_D0 Reg  ; S6=1  S9=1 
+Node  167  cpu_est_2_ Reg  ; S6=1  S9=1 
+Node  178  IPL_D0_0_ Reg  ; S6=1  S9=1 
+Node  194  IPL_D0_1_ Reg  ; S6=1  S9=1 
+Node  262  IPL_D0_2_ Reg  ; S6=1  S9=1 
+Node  161  SM_AMIGA_3_ Reg  ; S6=1  S9=1 
+Node  209  inst_CLK_000_NE_D0 Reg  ; S6=1  S9=1 
 Node  235  SM_AMIGA_0_ Reg  ; S6=1  S9=1 
 Node  260  inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg  ; S6=1  S9=1 
-Node  155  SM_AMIGA_6_ Reg  ; S6=1  S9=1 
-Node  140  RST_DLY_0_ Reg  ; S6=1  S9=1 
-Node  103  RST_DLY_1_ Reg  ; S6=1  S9=1 
+Node  229  SM_AMIGA_6_ Reg  ; S6=1  S9=1 
+Node  158  RST_DLY_0_ Reg  ; S6=1  S9=1 
+Node  145  RST_DLY_1_ Reg  ; S6=1  S9=1 
 Node  133  RST_DLY_2_ Reg  ; S6=1  S9=1 
-Node  125  RST_DLY_3_ Reg  ; S6=1  S9=1 
-Node  143  RST_DLY_4_ Reg  ; S6=1  S9=1 
-Node  119  RST_DLY_5_ Reg  ; S6=1  S9=1 
-Node  142  RST_DLY_6_ Reg  ; S6=1  S9=1 
-Node  109  RST_DLY_7_ Reg  ; S6=1  S9=1 
-Node  190  CLK_000_P_SYNC_0_ Reg  ; S6=1  S9=1 
-Node  262  CLK_000_P_SYNC_1_ Reg  ; S6=1  S9=1 
-Node  130  CLK_000_P_SYNC_2_ Reg  ; S6=1  S9=1 
-Node  163  CLK_000_P_SYNC_3_ Reg  ; S6=1  S9=1 
-Node  131  CLK_000_P_SYNC_4_ Reg  ; S6=1  S9=1 
-Node  211  CLK_000_P_SYNC_5_ Reg  ; S6=1  S9=1 
-Node  205  CLK_000_P_SYNC_6_ Reg  ; S6=1  S9=1 
-Node  256  CLK_000_P_SYNC_7_ Reg  ; S6=1  S9=1 
-Node  157  CLK_000_P_SYNC_8_ Reg  ; S6=1  S9=1 
-Node  184  CLK_000_N_SYNC_0_ Reg  ; S6=1  S9=1 
-Node  124  CLK_000_N_SYNC_1_ Reg  ; S6=1  S9=1 
-Node  118  CLK_000_N_SYNC_2_ Reg  ; S6=1  S9=1 
-Node  112  CLK_000_N_SYNC_3_ Reg  ; S6=1  S9=1 
-Node  178  CLK_000_N_SYNC_4_ Reg  ; S6=1  S9=1 
-Node  106  CLK_000_N_SYNC_5_ Reg  ; S6=1  S9=1 
-Node  194  CLK_000_N_SYNC_6_ Reg  ; S6=1  S9=1 
-Node  209  CLK_000_N_SYNC_7_ Reg  ; S6=1  S9=1 
-Node  122  CLK_000_N_SYNC_8_ Reg  ; S6=1  S9=1 
-Node  250  CLK_000_N_SYNC_9_ Reg  ; S6=1  S9=1 
+Node  163  RST_DLY_3_ Reg  ; S6=1  S9=1 
+Node  170  RST_DLY_4_ Reg  ; S6=1  S9=1 
+Node  139  RST_DLY_5_ Reg  ; S6=1  S9=1 
+Node  152  RST_DLY_6_ Reg  ; S6=1  S9=1 
+Node  164  RST_DLY_7_ Reg  ; S6=1  S9=1 
+Node  188  CLK_000_P_SYNC_0_ Reg  ; S6=1  S9=1 
+Node  166  CLK_000_P_SYNC_1_ Reg  ; S6=1  S9=1 
+Node  142  CLK_000_P_SYNC_2_ Reg  ; S6=1  S9=1 
+Node  160  CLK_000_P_SYNC_3_ Reg  ; S6=1  S9=1 
+Node  182  CLK_000_P_SYNC_4_ Reg  ; S6=1  S9=1 
+Node  236  CLK_000_P_SYNC_5_ Reg  ; S6=1  S9=1 
+Node  106  CLK_000_P_SYNC_6_ Reg  ; S6=1  S9=1 
+Node  122  CLK_000_P_SYNC_7_ Reg  ; S6=1  S9=1 
+Node  116  CLK_000_P_SYNC_8_ Reg  ; S6=1  S9=1 
+Node  230  CLK_000_N_SYNC_0_ Reg  ; S6=1  S9=1 
+Node  256  CLK_000_N_SYNC_1_ Reg  ; S6=1  S9=1 
+Node  250  CLK_000_N_SYNC_2_ Reg  ; S6=1  S9=1 
+Node  136  CLK_000_N_SYNC_3_ Reg  ; S6=1  S9=1 
+Node  130  CLK_000_N_SYNC_4_ Reg  ; S6=1  S9=1 
+Node  176  pos_clk_un29_clk_000_ne_d0_i_n Comb ; S6=1  S9=1 
+Node  146  CLK_000_N_SYNC_5_ Reg  ; S6=1  S9=1 
+Node  110  CLK_000_N_SYNC_6_ Reg  ; S6=1  S9=1 
+Node  140  CLK_000_N_SYNC_7_ Reg  ; S6=1  S9=1 
+Node  266  CLK_000_N_SYNC_8_ Reg  ; S6=1  S9=1 
+Node  224  CLK_000_N_SYNC_9_ Reg  ; S6=1  S9=1 
 Node  272  CLK_000_N_SYNC_10_ Reg  ; S6=1  S9=1 
-Node  104  inst_CLK_030_H Reg  ; S6=1  S9=1 
-Node  223  SM_AMIGA_1_ Reg  ; S6=1  S9=1 
-Node  236  SM_AMIGA_4_ Reg  ; S6=1  S9=1 
-Node  224  SM_AMIGA_2_ Reg  ; S6=1  S9=1 
-Node  167  inst_DS_000_ENABLE Reg  ; S6=1  S9=1 
-Node  221  SM_AMIGA_i_7_ Reg  ; S6=1  S9=1 
+Node  115  inst_CLK_030_H Reg  ; S6=1  S9=1 
+Node  151  SM_AMIGA_1_ Reg  ; S6=1  S9=1 
+Node  223  SM_AMIGA_4_ Reg  ; S6=1  S9=1 
+Node  169  SM_AMIGA_2_ Reg  ; S6=1  S9=1 
+Node  119  inst_DS_000_ENABLE Reg  ; S6=1  S9=1 
+Node  233  SM_AMIGA_i_7_ Reg  ; S6=1  S9=1 
+Node  205  CIIN_0 Comb ; S6=1  S9=1 
 ; Unused Pins & Nodes
 ; -> None Found.

Logic/68030_tk.tal

@@ -46,66 +46,64 @@ SIGNAL NAME       min  max  min  max  min  max  min  max
           DS_030  ..   ..   ..   ..    1    2   ..   ..   
           FPU_CS  ..   ..   ..   ..    1    2   ..   ..   
 AMIGA_BUS_DATA_DIR  ..   ..   ..   ..    1    2   ..   ..   
-     SM_AMIGA_5_   1    1   ..   ..   ..   ..    1    2   
-  inst_AS_030_D0   1    2   ..   ..   ..   ..    1    1   
-inst_nEXP_SPACE_D0reg   1    1    1    1   ..   ..    1    2   
-inst_AS_030_000_SYNC   1    1   ..   ..   ..   ..    1    2   
+       BGACK_030   1    2    0    1   ..   ..    1    1   
+    RN_BGACK_030   1    2    0    1   ..   ..    1    1   
+               E  ..   ..    0    0   ..   ..    1    2   
+            RN_E  ..   ..    0    0   ..   ..    1    2   
+             VMA   1    1    0    0   ..   ..    1    2   
+          RN_VMA   1    1    0    0   ..   ..    1    2   
+      cpu_est_0_  ..   ..   ..   ..   ..   ..    1    2   
+      cpu_est_1_  ..   ..   ..   ..   ..   ..    1    2   
+  inst_AS_030_D0   1    2    1    1   ..   ..    1    1   
     CYCLE_DMA_0_   1    2   ..   ..   ..   ..    1    1   
     CYCLE_DMA_1_   1    2   ..   ..   ..   ..    1    1   
+      inst_VPA_D   1    1   ..   ..   ..   ..    1    2   
 inst_UDS_000_INT   1    1    1    1   ..   ..    2    2   
 inst_LDS_000_INT   1    1    1    1   ..   ..    2    2   
- inst_CLK_000_D1  ..   ..   ..   ..   ..   ..    1    2   
- inst_CLK_000_D0   1    1   ..   ..   ..   ..    1    2   
-     SM_AMIGA_3_   1    1   ..   ..   ..   ..    1    2   
-     SM_AMIGA_0_   1    1   ..   ..   ..   ..    1    2   
-     SM_AMIGA_6_   1    1   ..   ..   ..   ..    1    2   
-     SM_AMIGA_1_   1    1   ..   ..   ..   ..    1    2   
-     SM_AMIGA_4_   1    1   ..   ..   ..   ..    1    2   
-     SM_AMIGA_2_   1    1   ..   ..   ..   ..    1    2   
+   inst_DTACK_D0   1    1   ..   ..   ..   ..    1    2   
+      cpu_est_2_  ..   ..   ..   ..   ..   ..    1    2   
+inst_CLK_000_NE_D0  ..   ..   ..   ..   ..   ..    1    2   
 inst_DS_000_ENABLE   1    1    1    1   ..   ..    2    2   
           AS_030  ..   ..   ..   ..    1    1   ..   ..   
           AS_000  ..   ..   ..   ..    1    1   ..   ..   
          CLK_EXP  ..   ..   ..   ..    1    1   ..   ..   
+            CIIN  ..   ..   ..   ..    1    1   ..   ..   
       IPL_030_2_   1    1    0    0   ..   ..    1    1   
    RN_IPL_030_2_   1    1    0    0   ..   ..    1    1   
           RW_000   1    1    0    0   ..   ..    1    1   
        RN_RW_000   1    1    0    0   ..   ..    1    1   
           BG_000   1    1    0    0   ..   ..    1    1   
        RN_BG_000   1    1    0    0   ..   ..    1    1   
-       BGACK_030   1    1    0    1   ..   ..    1    1   
-    RN_BGACK_030   1    1    0    1   ..   ..    1    1   
       IPL_030_1_   1    1    0    0   ..   ..    1    1   
    RN_IPL_030_1_   1    1    0    0   ..   ..    1    1   
       IPL_030_0_   1    1    0    0   ..   ..    1    1   
    RN_IPL_030_0_   1    1    0    0   ..   ..    1    1   
           DSACK1   1    1    0    0   ..   ..    1    1   
        RN_DSACK1   1    1    0    0   ..   ..    1    1   
-               E  ..   ..    0    0   ..   ..    1    1   
-            RN_E  ..   ..    0    0   ..   ..    1    1   
-             VMA   1    1    0    0   ..   ..    1    1   
-          RN_VMA   1    1    0    0   ..   ..    1    1   
            RESET   1    1    0    0   ..   ..    1    1   
         RN_RESET   1    1    0    0   ..   ..    1    1   
               RW   1    1    0    0   ..   ..    1    1   
            RN_RW   1    1    0    0   ..   ..    1    1   
-      cpu_est_0_  ..   ..   ..   ..   ..   ..    1    1   
-      cpu_est_1_  ..   ..   ..   ..   ..   ..    1    1   
+     SM_AMIGA_5_   1    1   ..   ..   ..   ..    1    1   
 inst_AMIGA_BUS_ENABLE_DMA_LOW   1    1    1    1   ..   ..   ..   ..   
+inst_nEXP_SPACE_D0reg   1    1    1    1   ..   ..    1    1   
+inst_AS_030_000_SYNC   1    1   ..   ..   ..   ..    1    1   
 inst_BGACK_030_INT_D   1    1   ..   ..   ..   ..    1    1   
-      inst_VPA_D   1    1   ..   ..   ..   ..    1    1   
 inst_CLK_OUT_PRE_D  ..   ..   ..   ..   ..   ..    1    1   
-   inst_DTACK_D0   1    1   ..   ..   ..   ..    1    1   
 inst_CLK_OUT_PRE_50  ..   ..   ..   ..   ..   ..    1    1   
+ inst_CLK_000_D1  ..   ..   ..   ..   ..   ..    1    1   
+ inst_CLK_000_D0   1    1   ..   ..   ..   ..    1    1   
  inst_CLK_000_PE  ..   ..   ..   ..   ..   ..    1    1   
 CLK_000_P_SYNC_9_  ..   ..   ..   ..   ..   ..    1    1   
  inst_CLK_000_NE  ..   ..   ..   ..   ..   ..    1    1   
 CLK_000_N_SYNC_11_  ..   ..   ..   ..   ..   ..    1    1   
-      cpu_est_2_  ..   ..   ..   ..   ..   ..    1    1   
        IPL_D0_0_   1    1   ..   ..   ..   ..    1    1   
        IPL_D0_1_   1    1   ..   ..   ..   ..    1    1   
        IPL_D0_2_   1    1   ..   ..   ..   ..    1    1   
-inst_CLK_000_NE_D0  ..   ..   ..   ..   ..   ..    1    1   
+     SM_AMIGA_3_   1    1   ..   ..   ..   ..    1    1   
+     SM_AMIGA_0_   1    1   ..   ..   ..   ..    1    1   
 inst_AMIGA_BUS_ENABLE_DMA_HIGH   1    1    1    1   ..   ..   ..   ..   
+     SM_AMIGA_6_   1    1   ..   ..   ..   ..    1    1   
       RST_DLY_0_   1    1   ..   ..   ..   ..    1    1   
       RST_DLY_1_   1    1   ..   ..   ..   ..    1    1   
       RST_DLY_2_   1    1   ..   ..   ..   ..    1    1   
@@ -134,4 +132,8 @@ CLK_000_N_SYNC_7_  ..   ..   ..   ..   ..   ..    1    1
 CLK_000_N_SYNC_8_  ..   ..   ..   ..   ..   ..    1    1   
 CLK_000_N_SYNC_9_  ..   ..   ..   ..   ..   ..    1    1   
 CLK_000_N_SYNC_10_  ..   ..   ..   ..   ..   ..    1    1   
-   SM_AMIGA_i_7_   1    1    1    1   ..   ..    1    1   
+     SM_AMIGA_1_   1    1   ..   ..   ..   ..    1    1   
+     SM_AMIGA_4_   1    1   ..   ..   ..   ..    1    1   
+     SM_AMIGA_2_   1    1   ..   ..   ..   ..    1    1   
+   SM_AMIGA_i_7_   1    1    1    1   ..   ..    1    1   
+          CIIN_0  ..   ..   ..   ..    1    1   ..   ..   

Logic/68030_tk.tt4

@@ -1,13 +1,14 @@
 #$ TOOL  ispLEVER Classic 1.8.00.04.29.14
-#$ DATE  Thu Jul 09 18:48:59 2015
+#$ DATE  Thu Sep 24 16:20:59 2015
 #$ MODULE  BUS68030
-#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ A_25_ A_24_
- IPL_2_ FC_1_ AS_030 AS_000 A_19_ A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A1
+#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_
+ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1
  nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP
- FPU_CS FPU_SENSE IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_ADDR_ENABLE
- AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_
- RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW
-#$ NODES 72 N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_
+ IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE
+ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_
+ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA
+ RESET RW
+#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_
  inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
  inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA
  inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D
@@ -20,60 +21,60 @@
  CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
  CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
  CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
- CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
- CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H
- SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_
+ CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_
+ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_
+ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_
+ inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0
 .type f
-.i 123
-.o 199
+.i 128
+.o 200
 .ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
- FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_19_ A_18_
- A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q N_165 cpu_est_0_.Q
- cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q
- inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q
- inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q
- CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q
- inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q
- inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
- inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q
- IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q
- inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q
- RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q
- RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q
- CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q
- CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q
- CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q
- CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q
- CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q
- SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q
- IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN
- DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN
- RW.PIN
-.ob SIZE_0_ SIZE_0_.OE SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE
- DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE
- CLK_DIV_OUT CLK_DIV_OUT.OE CLK_EXP FPU_CS% AVEC AMIGA_ADDR_ENABLE
- AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE
- IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D%
- BG_000.C BGACK_030.D% BGACK_030.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D%
- IPL_030_0_.C DSACK1.D% DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C
- RW.D% RW.C RW.OE N_165 cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D% cpu_est_1_.C
- inst_AS_000_INT.D% inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C
- inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C
- inst_AS_030_D0.D% inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D%
- inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D% inst_DS_030_D0.C
- inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D%
- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
- inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
- SIZE_DMA_0_.D% SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D%
- inst_VPA_D.C inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D
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- inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D
- inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D
- cpu_est_2_.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D%
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- inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
+ FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
+ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q
+ RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q
+ inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q
+ inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
+ inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
+ inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
+ inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
+ inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q
+ cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q
+ inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
+ SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q
+ RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q
+ CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q
+ CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q
+ CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q
+ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q
+ CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q
+ RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q
+ inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q
+ IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN
+ SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN CIIN_0
+.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE
+ UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE
+ CLK_EXP FPU_CS% AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW%
+ AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C
+ RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D
+ BGACK_030.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C DSACK1.D%
+ DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D% RW.C RW.OE
+ cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D% cpu_est_1_.C inst_AS_000_INT.D%
+ inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
+ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
+ inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D%
+ inst_DS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C
+ inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
+ inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
+ CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C
+ SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C inst_UDS_000_INT.D%
+ inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D
+ inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D
+ inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D
+ inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D
+ CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D
+ CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D% IPL_D0_0_.C
+ IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C
+ inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
  inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D
  SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D
  RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1 RST_DLY_4_.T.X2
@@ -85,254 +86,252 @@
  CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D
  CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D
  CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D
- CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D
- CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D
- CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D
- CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D
- SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_2_.D SM_AMIGA_2_.C
- inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C
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 .end

Logic/68030_tk.tte

@@ -1,13 +1,14 @@
 #$ TOOL  ispLEVER Classic 1.8.00.04.29.14
-#$ DATE  Thu Jul 09 18:48:59 2015
+#$ DATE  Thu Sep 24 16:20:59 2015
 #$ MODULE  BUS68030
-#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ A_25_ A_24_
- IPL_2_ FC_1_ AS_030 AS_000 A_19_ A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A1
+#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_
+ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1
  nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP
- FPU_CS FPU_SENSE IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_ADDR_ENABLE
- AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_
- RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW
-#$ NODES 72 N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_
+ IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE
+ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_
+ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA
+ RESET RW
+#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_
  inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
  inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA
  inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D
@@ -20,60 +21,60 @@
  CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
  CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
  CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
- CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
- CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H
- SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_
+ CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_
+ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_
+ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_
+ inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0
 .type f
-.i 123
-.o 199
+.i 128
+.o 200
 .ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
- FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_19_ A_18_
- A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q N_165 cpu_est_0_.Q
- cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q
- inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q
- inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q
- CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q
- inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q
- inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
- inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q
- IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q
- inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q
- RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q
- RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q
- CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q
- CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q
- CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q
- CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q
- CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q
- SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q
- IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN
- DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN
- RW.PIN
-.ob SIZE_0_ SIZE_0_.OE SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE
- DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE
- CLK_DIV_OUT CLK_DIV_OUT.OE CLK_EXP FPU_CS- AVEC AMIGA_ADDR_ENABLE
- AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE
- IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D-
- BG_000.C BGACK_030.D- BGACK_030.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D-
- IPL_030_0_.C DSACK1.D- DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C
- RW.D- RW.C RW.OE N_165 cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D- cpu_est_1_.C
- inst_AS_000_INT.D- inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C
- inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C
- inst_AS_030_D0.D- inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D-
- inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D- inst_DS_030_D0.C
- inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D-
- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
- inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
- SIZE_DMA_0_.D- SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D-
- inst_VPA_D.C inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D
- inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D-
- inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D
- inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D
- inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D
- inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D
- cpu_est_2_.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D-
- IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C inst_CLK_000_NE_D0.D
- inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
+ FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
+ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q
+ RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q
+ inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q
+ inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
+ inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
+ inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
+ inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
+ inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q
+ cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q
+ inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
+ SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q
+ RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q
+ CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q
+ CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q
+ CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q
+ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q
+ CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q
+ RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q
+ inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q
+ IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN
+ SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN CIIN_0
+.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE
+ UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE
+ CLK_EXP FPU_CS- AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW-
+ AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C
+ RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D
+ BGACK_030.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C DSACK1.D-
+ DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D- RW.C RW.OE
+ cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D- cpu_est_1_.C inst_AS_000_INT.D-
+ inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
+ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
+ inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D-
+ inst_DS_030_D0.C inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C
+ inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
+ inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
+ CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C
+ SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C inst_UDS_000_INT.D-
+ inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D
+ inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D
+ inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D
+ inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D
+ CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D
+ CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D- IPL_D0_0_.C
+ IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C
+ inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
  inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D
  SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D
  RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1 RST_DLY_4_.T.X2
@@ -85,254 +86,252 @@
  CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D
  CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D
  CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D
- CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D
- CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D
- CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D
- CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D
- SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_2_.D SM_AMIGA_2_.C
- inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C
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+ CLK_000_N_SYNC_4_.C pos_clk_un29_clk_000_ne_d0_i_n- CLK_000_N_SYNC_5_.D
+ CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D
+ CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D
+ CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C inst_CLK_030_H.D
+ inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C
+ SM_AMIGA_2_.D SM_AMIGA_2_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
+ SM_AMIGA_i_7_.D- SM_AMIGA_i_7_.C CIIN_0
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+.p 239
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 .end

Logic/68030_tk.vcl

@@ -17,8 +17,8 @@ Parent = m4a5.lci;
 SDS_file = m4a5.sds;
 Design = 68030_tk.tt4;
 Rev = 0.01;
-DATE = 7/9/15;
-TIME = 18:49:07;
+DATE = 9/24/15;
+TIME = 16:21:08;
 Type = TT2;
 Pre_Fit_Time = 1;
 Source_Format = Pure_VHDL;
@@ -136,14 +136,14 @@ layer = OFF;
 [LOCATION ASSIGNMENT]
 
 Layer = OFF
+BERR = OUTPUT,41,4,-;
 RW_000 = BIDIR,80,7,-;
 AS_000 = OUTPUT,42,4,-;
-BERR = OUTPUT,41,4,-;
-A0 = BIDIR,69,6,-;
 RW = BIDIR,71,6,-;
 AS_030 = OUTPUT,82,7,-;
 UDS_000 = OUTPUT,32,3,-;
 LDS_000 = OUTPUT,31,3,-;
+A0 = BIDIR,69,6,-;
 DS_030 = OUTPUT,98,0,-;
 SIZE_1_ = OUTPUT,79,7,-;
 SIZE_0_ = OUTPUT,70,6,-;
@@ -152,8 +152,8 @@ IPL_030_0_ = OUTPUT,8,1,-;
 IPL_030_1_ = OUTPUT,7,1,-;
 E = OUTPUT,66,6,-;
 DSACK1 = OUTPUT,81,7,-;
-VMA = OUTPUT,35,3,-;
 BGACK_030 = OUTPUT,83,7,-;
+VMA = OUTPUT,35,3,-;
 AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
 AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-;
 BG_000 = OUTPUT,29,3,-;
@@ -165,88 +165,89 @@ CIIN = OUTPUT,47,4,-;
 AMIGA_ADDR_ENABLE = OUTPUT,33,3,-;
 AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
 CLK_EXP = OUTPUT,10,1,-;
-inst_nEXP_SPACE_D0reg = NODE,*,6,-;
-RN_RESET = NODE,-1,1,-;
 RN_BGACK_030 = NODE,-1,7,-;
-inst_CLK_000_PE = NODE,*,3,-;
-inst_CLK_000_NE = NODE,*,6,-;
+RN_RESET = NODE,-1,1,-;
+inst_nEXP_SPACE_D0reg = NODE,*,5,-;
+inst_CLK_000_NE = NODE,*,5,-;
+inst_CLK_000_PE = NODE,*,2,-;
 inst_AS_030_D0 = NODE,*,7,-;
 SM_AMIGA_i_7_ = NODE,*,5,-;
 RN_E = NODE,-1,6,-;
-cpu_est_1_ = NODE,*,3,-;
-cpu_est_2_ = NODE,*,3,-;
-SM_AMIGA_6_ = NODE,*,2,-;
+SM_AMIGA_3_ = NODE,*,2,-;
+cpu_est_1_ = NODE,*,6,-;
+cpu_est_2_ = NODE,*,2,-;
+SM_AMIGA_1_ = NODE,*,2,-;
 SM_AMIGA_5_ = NODE,*,5,-;
-cpu_est_0_ = NODE,*,3,-;
-inst_CLK_000_NE_D0 = NODE,*,1,-;
-inst_CLK_000_D0 = NODE,*,6,-;
-inst_CLK_000_D1 = NODE,*,5,-;
+cpu_est_0_ = NODE,*,2,-;
+inst_CLK_000_NE_D0 = NODE,*,4,-;
+inst_BGACK_030_INT_D = NODE,*,7,-;
 inst_AS_000_DMA = NODE,*,0,-;
-inst_AS_030_000_SYNC = NODE,*,2,-;
-RST_DLY_3_ = NODE,*,1,-;
+RST_DLY_3_ = NODE,*,2,-;
 RST_DLY_2_ = NODE,*,1,-;
-SM_AMIGA_3_ = NODE,*,5,-;
-RST_DLY_5_ = NODE,*,0,-;
-RST_DLY_1_ = NODE,*,0,-;
-inst_LDS_000_INT = NODE,*,1,-;
+SM_AMIGA_2_ = NODE,*,2,-;
+RST_DLY_5_ = NODE,*,1,-;
+RST_DLY_1_ = NODE,*,1,-;
+inst_LDS_000_INT = NODE,*,6,-;
 RN_VMA = NODE,-1,3,-;
-inst_DS_000_ENABLE = NODE,*,2,-;
-SM_AMIGA_1_ = NODE,*,5,-;
-RST_DLY_6_ = NODE,*,1,-;
-RST_DLY_0_ = NODE,*,1,-;
-inst_UDS_000_INT = NODE,*,5,-;
+inst_DS_000_ENABLE = NODE,*,0,-;
+SM_AMIGA_4_ = NODE,*,5,-;
+RST_DLY_6_ = NODE,*,2,-;
+RST_DLY_0_ = NODE,*,2,-;
+SM_AMIGA_6_ = NODE,*,5,-;
+inst_UDS_000_INT = NODE,*,6,-;
 SIZE_DMA_1_ = NODE,*,6,-;
 SIZE_DMA_0_ = NODE,*,6,-;
-RST_DLY_7_ = NODE,*,0,-;
-RST_DLY_4_ = NODE,*,1,-;
+RST_DLY_7_ = NODE,*,2,-;
+RST_DLY_4_ = NODE,*,2,-;
 inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-;
 SM_AMIGA_0_ = NODE,*,5,-;
-inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-;
-inst_AS_000_INT = NODE,*,2,-;
-inst_CLK_OUT_PRE_50 = NODE,*,0,-;
-inst_VPA_D = NODE,*,5,-;
-inst_BGACK_030_INT_D = NODE,*,7,-;
-inst_DS_030_D0 = NODE,*,3,-;
+inst_AS_000_INT = NODE,*,0,-;
+inst_CLK_000_D0 = NODE,*,1,-;
+inst_CLK_000_D1 = NODE,*,3,-;
+inst_DTACK_D0 = NODE,*,1,-;
+inst_VPA_D = NODE,*,3,-;
 RN_IPL_030_0_ = NODE,-1,1,-;
 RN_IPL_030_1_ = NODE,-1,1,-;
 RN_IPL_030_2_ = NODE,-1,1,-;
 inst_DS_000_DMA = NODE,*,0,-;
 inst_CLK_030_H = NODE,*,0,-;
+inst_AS_030_000_SYNC = NODE,*,5,-;
 RN_DSACK1 = NODE,-1,7,-;
-SM_AMIGA_2_ = NODE,*,5,-;
-N_165 = NODE,*,5,-;
 RN_A0 = NODE,-1,6,-;
 RN_RW_000 = NODE,-1,7,-;
-SM_AMIGA_4_ = NODE,*,5,-;
 CYCLE_DMA_1_ = NODE,*,0,-;
 RN_RW = NODE,-1,6,-;
 RN_BG_000 = NODE,-1,3,-;
+CIIN_0 = NODE,*,4,-;
+pos_clk_un29_clk_000_ne_d0_i_n = NODE,*,3,-;
 CYCLE_DMA_0_ = NODE,*,0,-;
+inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-;
 CLK_000_N_SYNC_10_ = NODE,*,7,-;
-CLK_000_N_SYNC_9_ = NODE,*,6,-;
-CLK_000_N_SYNC_8_ = NODE,*,0,-;
-CLK_000_N_SYNC_7_ = NODE,*,4,-;
-CLK_000_N_SYNC_6_ = NODE,*,3,-;
-CLK_000_N_SYNC_5_ = NODE,*,0,-;
-CLK_000_N_SYNC_4_ = NODE,*,3,-;
-CLK_000_N_SYNC_3_ = NODE,*,0,-;
-CLK_000_N_SYNC_2_ = NODE,*,0,-;
-CLK_000_N_SYNC_1_ = NODE,*,0,-;
-CLK_000_N_SYNC_0_ = NODE,*,3,-;
-CLK_000_P_SYNC_8_ = NODE,*,2,-;
-CLK_000_P_SYNC_7_ = NODE,*,6,-;
-CLK_000_P_SYNC_6_ = NODE,*,4,-;
-CLK_000_P_SYNC_5_ = NODE,*,4,-;
-CLK_000_P_SYNC_4_ = NODE,*,1,-;
+CLK_000_N_SYNC_9_ = NODE,*,5,-;
+CLK_000_N_SYNC_8_ = NODE,*,6,-;
+CLK_000_N_SYNC_7_ = NODE,*,1,-;
+CLK_000_N_SYNC_6_ = NODE,*,0,-;
+CLK_000_N_SYNC_5_ = NODE,*,1,-;
+CLK_000_N_SYNC_4_ = NODE,*,1,-;
+CLK_000_N_SYNC_3_ = NODE,*,1,-;
+CLK_000_N_SYNC_2_ = NODE,*,6,-;
+CLK_000_N_SYNC_1_ = NODE,*,6,-;
+CLK_000_N_SYNC_0_ = NODE,*,5,-;
+CLK_000_P_SYNC_8_ = NODE,*,0,-;
+CLK_000_P_SYNC_7_ = NODE,*,0,-;
+CLK_000_P_SYNC_6_ = NODE,*,0,-;
+CLK_000_P_SYNC_5_ = NODE,*,5,-;
+CLK_000_P_SYNC_4_ = NODE,*,3,-;
 CLK_000_P_SYNC_3_ = NODE,*,2,-;
 CLK_000_P_SYNC_2_ = NODE,*,1,-;
-CLK_000_P_SYNC_1_ = NODE,*,6,-;
+CLK_000_P_SYNC_1_ = NODE,*,2,-;
 CLK_000_P_SYNC_0_ = NODE,*,3,-;
-IPL_D0_2_ = NODE,*,1,-;
-IPL_D0_1_ = NODE,*,2,-;
-IPL_D0_0_ = NODE,*,1,-;
+IPL_D0_2_ = NODE,*,6,-;
+IPL_D0_1_ = NODE,*,3,-;
+IPL_D0_0_ = NODE,*,3,-;
 CLK_000_N_SYNC_11_ = NODE,*,7,-;
-CLK_000_P_SYNC_9_ = NODE,*,2,-;
-inst_DTACK_D0 = NODE,*,3,-;
-inst_CLK_OUT_PRE_D = NODE,*,6,-;
+CLK_000_P_SYNC_9_ = NODE,*,0,-;
+inst_CLK_OUT_PRE_50 = NODE,*,4,-;
+inst_CLK_OUT_PRE_D = NODE,*,4,-;
+inst_DS_030_D0 = NODE,*,3,-;
 CLK_OSZI = INPUT,61,-,-;

Logic/68030_tk.vco

@@ -17,8 +17,8 @@ Parent = m4a5.lci;
 SDS_file = m4a5.sds;
 Design = 68030_tk.tt4;
 Rev = 0.01;
-DATE = 7/9/15;
-TIME = 18:49:07;
+DATE = 9/24/15;
+TIME = 16:21:08;
 Type = TT2;
 Pre_Fit_Time = 1;
 Source_Format = Pure_VHDL;
@@ -136,26 +136,27 @@ layer = OFF;
 [LOCATION ASSIGNMENT]
 
 Layer = OFF;
-SIZE_0_ = BIDIR,70, G,-;
-A_30_ = INPUT,5, B,-;
-SIZE_1_ = BIDIR,79, H,-;
-A_29_ = INPUT,6, B,-;
 A_28_ = INPUT,15, C,-;
-A_31_ = INPUT,4, B,-;
 A_27_ = INPUT,16, C,-;
+SIZE_1_ = BIDIR,79, H,-;
 A_26_ = INPUT,17, C,-;
 A_25_ = INPUT,18, C,-;
+A_31_ = INPUT,4, B,-;
 A_24_ = INPUT,19, C,-;
+A_23_ = INPUT,85, H,-;
+A_22_ = INPUT,84, H,-;
+A_21_ = INPUT,94, A,-;
 IPL_2_ = INPUT,68, G,-;
-FC_1_ = INPUT,58, F,-;
-AS_030 = BIDIR,82, H,-;
-AS_000 = BIDIR,42, E,-;
+A_20_ = INPUT,93, A,-;
 A_19_ = INPUT,97, A,-;
+FC_1_ = INPUT,58, F,-;
 A_18_ = INPUT,95, A,-;
-DS_030 = BIDIR,98, A,-;
+AS_030 = BIDIR,82, H,-;
 A_17_ = INPUT,59, F,-;
-UDS_000 = BIDIR,32, D,-;
+AS_000 = BIDIR,42, E,-;
 A_16_ = INPUT,96, A,-;
+DS_030 = BIDIR,98, A,-;
+UDS_000 = BIDIR,32, D,-;
 LDS_000 = BIDIR,31, D,-;
 A1 = INPUT,60, F,-;
 nEXP_SPACE = INPUT,14,-,-;
@@ -167,13 +168,13 @@ CLK_000 = INPUT,11,-,-;
 CLK_OSZI = INPUT,61,-,-;
 CLK_DIV_OUT = OUTPUT,65, G,-;
 CLK_EXP = OUTPUT,10, B,-;
-FPU_CS = OUTPUT,78, H,-;
-FPU_SENSE = INPUT,91, A,-;
 IPL_1_ = INPUT,56, F,-;
-DTACK = INPUT,30, D,-;
+FPU_CS = OUTPUT,78, H,-;
 IPL_0_ = INPUT,67, G,-;
-AVEC = OUTPUT,92, A,-;
+FPU_SENSE = INPUT,91, A,-;
 FC_0_ = INPUT,57, F,-;
+DTACK = INPUT,30, D,-;
+AVEC = OUTPUT,92, A,-;
 VPA = INPUT,36,-,-;
 RST = INPUT,86,-,-;
 AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
@@ -181,6 +182,9 @@ AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
 AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
 AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
 CIIN = OUTPUT,47, E,-;
+SIZE_0_ = BIDIR,70, G,-;
+A_30_ = INPUT,5, B,-;
+A_29_ = INPUT,6, B,-;
 IPL_030_2_ = OUTPUT,9, B,-;
 RW_000 = BIDIR,80, H,-;
 A0 = BIDIR,69, G,-;
@@ -193,75 +197,76 @@ E = OUTPUT,66, G,-;
 VMA = OUTPUT,35, D,-;
 RESET = OUTPUT,3, B,-;
 RW = BIDIR,71, G,-;
-N_165 = NODE,6, F,-;
-cpu_est_0_ = NODE,6, D,-;
-cpu_est_1_ = NODE,13, D,-;
-inst_AS_000_INT = NODE,1, C,-;
-SM_AMIGA_5_ = NODE,4, F,-;
-inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,14, G,-;
+cpu_est_0_ = NODE,5, C,-;
+cpu_est_1_ = NODE,5, G,-;
+inst_AS_000_INT = NODE,1, A,-;
+SM_AMIGA_5_ = NODE,12, F,-;
+inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,3, C,-;
 inst_AS_030_D0 = NODE,5, H,-;
-inst_nEXP_SPACE_D0reg = NODE,5, G,-;
-inst_DS_030_D0 = NODE,10, D,-;
-inst_AS_030_000_SYNC = NODE,8, C,-;
+inst_nEXP_SPACE_D0reg = NODE,0, F,-;
+inst_DS_030_D0 = NODE,7, D,-;
+inst_AS_030_000_SYNC = NODE,13, F,-;
 inst_BGACK_030_INT_D = NODE,13, H,-;
 inst_AS_000_DMA = NODE,8, A,-;
-inst_DS_000_DMA = NODE,13, A,-;
-CYCLE_DMA_0_ = NODE,10, A,-;
-CYCLE_DMA_1_ = NODE,6, A,-;
+inst_DS_000_DMA = NODE,5, A,-;
+CYCLE_DMA_0_ = NODE,2, A,-;
+CYCLE_DMA_1_ = NODE,13, A,-;
 SIZE_DMA_0_ = NODE,6, G,-;
 SIZE_DMA_1_ = NODE,2, G,-;
-inst_VPA_D = NODE,13, F,-;
-inst_UDS_000_INT = NODE,5, F,-;
-inst_LDS_000_INT = NODE,9, B,-;
-inst_CLK_OUT_PRE_D = NODE,15, G,-;
-inst_DTACK_D0 = NODE,15, D,-;
-inst_CLK_OUT_PRE_50 = NODE,9, A,-;
-inst_CLK_000_D1 = NODE,8, F,-;
-inst_CLK_000_D0 = NODE,13, G,-;
-inst_CLK_000_PE = NODE,9, D,-;
-CLK_000_P_SYNC_9_ = NODE,2, C,-;
-inst_CLK_000_NE = NODE,9, G,-;
+inst_VPA_D = NODE,13, D,-;
+inst_UDS_000_INT = NODE,13, G,-;
+inst_LDS_000_INT = NODE,9, G,-;
+inst_CLK_OUT_PRE_D = NODE,13, E,-;
+inst_DTACK_D0 = NODE,6, B,-;
+inst_CLK_OUT_PRE_50 = NODE,9, E,-;
+inst_CLK_000_D1 = NODE,9, D,-;
+inst_CLK_000_D0 = NODE,2, B,-;
+inst_CLK_000_PE = NODE,4, C,-;
+CLK_000_P_SYNC_9_ = NODE,7, A,-;
+inst_CLK_000_NE = NODE,4, F,-;
 CLK_000_N_SYNC_11_ = NODE,6, H,-;
-cpu_est_2_ = NODE,2, D,-;
-IPL_D0_0_ = NODE,7, B,-;
-IPL_D0_1_ = NODE,13, C,-;
-IPL_D0_2_ = NODE,13, B,-;
-SM_AMIGA_3_ = NODE,12, F,-;
-inst_CLK_000_NE_D0 = NODE,15, B,-;
+cpu_est_2_ = NODE,12, C,-;
+IPL_D0_0_ = NODE,3, D,-;
+IPL_D0_1_ = NODE,14, D,-;
+IPL_D0_2_ = NODE,11, G,-;
+SM_AMIGA_3_ = NODE,8, C,-;
+inst_CLK_000_NE_D0 = NODE,8, E,-;
 SM_AMIGA_0_ = NODE,9, F,-;
 inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,10, G,-;
-SM_AMIGA_6_ = NODE,4, C,-;
-RST_DLY_0_ = NODE,10, B,-;
-RST_DLY_1_ = NODE,1, A,-;
+SM_AMIGA_6_ = NODE,5, F,-;
+RST_DLY_0_ = NODE,6, C,-;
+RST_DLY_1_ = NODE,13, B,-;
 RST_DLY_2_ = NODE,5, B,-;
-RST_DLY_3_ = NODE,0, B,-;
-RST_DLY_4_ = NODE,12, B,-;
-RST_DLY_5_ = NODE,12, A,-;
-RST_DLY_6_ = NODE,11, B,-;
-RST_DLY_7_ = NODE,5, A,-;
-CLK_000_P_SYNC_0_ = NODE,11, D,-;
-CLK_000_P_SYNC_1_ = NODE,11, G,-;
-CLK_000_P_SYNC_2_ = NODE,3, B,-;
-CLK_000_P_SYNC_3_ = NODE,9, C,-;
-CLK_000_P_SYNC_4_ = NODE,4, B,-;
-CLK_000_P_SYNC_5_ = NODE,9, E,-;
-CLK_000_P_SYNC_6_ = NODE,5, E,-;
-CLK_000_P_SYNC_7_ = NODE,7, G,-;
-CLK_000_P_SYNC_8_ = NODE,5, C,-;
-CLK_000_N_SYNC_0_ = NODE,7, D,-;
-CLK_000_N_SYNC_1_ = NODE,15, A,-;
-CLK_000_N_SYNC_2_ = NODE,11, A,-;
-CLK_000_N_SYNC_3_ = NODE,7, A,-;
-CLK_000_N_SYNC_4_ = NODE,3, D,-;
-CLK_000_N_SYNC_5_ = NODE,3, A,-;
-CLK_000_N_SYNC_6_ = NODE,14, D,-;
-CLK_000_N_SYNC_7_ = NODE,8, E,-;
-CLK_000_N_SYNC_8_ = NODE,14, A,-;
-CLK_000_N_SYNC_9_ = NODE,3, G,-;
+RST_DLY_3_ = NODE,9, C,-;
+RST_DLY_4_ = NODE,14, C,-;
+RST_DLY_5_ = NODE,9, B,-;
+RST_DLY_6_ = NODE,2, C,-;
+RST_DLY_7_ = NODE,10, C,-;
+CLK_000_P_SYNC_0_ = NODE,10, D,-;
+CLK_000_P_SYNC_1_ = NODE,11, C,-;
+CLK_000_P_SYNC_2_ = NODE,11, B,-;
+CLK_000_P_SYNC_3_ = NODE,7, C,-;
+CLK_000_P_SYNC_4_ = NODE,6, D,-;
+CLK_000_P_SYNC_5_ = NODE,10, F,-;
+CLK_000_P_SYNC_6_ = NODE,3, A,-;
+CLK_000_P_SYNC_7_ = NODE,14, A,-;
+CLK_000_P_SYNC_8_ = NODE,10, A,-;
+CLK_000_N_SYNC_0_ = NODE,6, F,-;
+CLK_000_N_SYNC_1_ = NODE,7, G,-;
+CLK_000_N_SYNC_2_ = NODE,3, G,-;
+CLK_000_N_SYNC_3_ = NODE,7, B,-;
+CLK_000_N_SYNC_4_ = NODE,3, B,-;
+pos_clk_un29_clk_000_ne_d0_i_n = NODE,2, D,-;
+CLK_000_N_SYNC_5_ = NODE,14, B,-;
+CLK_000_N_SYNC_6_ = NODE,6, A,-;
+CLK_000_N_SYNC_7_ = NODE,10, B,-;
+CLK_000_N_SYNC_8_ = NODE,14, G,-;
+CLK_000_N_SYNC_9_ = NODE,2, F,-;
 CLK_000_N_SYNC_10_ = NODE,2, H,-;
-inst_CLK_030_H = NODE,2, A,-;
-SM_AMIGA_1_ = NODE,1, F,-;
-SM_AMIGA_4_ = NODE,10, F,-;
-SM_AMIGA_2_ = NODE,2, F,-;
-inst_DS_000_ENABLE = NODE,12, C,-;
-SM_AMIGA_i_7_ = NODE,0, F,-;
+inst_CLK_030_H = NODE,9, A,-;
+SM_AMIGA_1_ = NODE,1, C,-;
+SM_AMIGA_4_ = NODE,1, F,-;
+SM_AMIGA_2_ = NODE,13, C,-;
+inst_DS_000_ENABLE = NODE,12, A,-;
+SM_AMIGA_i_7_ = NODE,8, F,-;
+CIIN_0 = NODE,5, E,-;

Logic/68030_tk.xrf

@@ -2,7 +2,7 @@ Signal Name Cross Reference File
 
 ispLEVER Classic 1.8.00.04.29.14
 
-Design '68030_tk' created Thu Jul 09 18:48:59 2015
+Design '68030_tk' created Thu Sep 24 16:20:59 2015
 
 
  LEGEND:  '>'  Functional Block Port Separator

Logic/BUS68030.cmd

@@ -0,0 +1,8 @@
+STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC

Logic/BUS68030.prj

@@ -1,6 +1,6 @@
 #-- Lattice Semiconductor Corporation Ltd.
 #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Thu Jul 09 18:48:45 2015
+#-- Written on Thu Sep 24 16:20:44 2015
 
 
 #device options

Logic/BUS68030.srr

@@ -1,12 +1,12 @@
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: C:\ispLever\synpbase
-#OS: Windows 7 6.1
+#OS: Windows 7 6.2
 #Hostname: DEEPTHOUGHT
 
 #Implementation: logic
 
 $ Start of Compile
-#Thu Jul 09 18:48:52 2015
+#Thu Sep 24 16:20:52 2015
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
 @N|Running in 64-bit mode
@@ -42,14 +42,13 @@ State machine has 8 reachable states with original encodings of:
    110
    111
 @N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
-@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused 
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
 @END
 
 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:52 2015
+# Thu Sep 24 16:20:52 2015
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@@ -59,7 +58,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:53 2015
+# Thu Sep 24 16:20:53 2015
 
 ###########################################################]
 Map & Optimize Report
@@ -68,7 +67,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
 @N: MF248 |Running in 64-bit mode.
-@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
+@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:16:498:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -90,10 +89,10 @@ BI_DIR          11 uses
 IBUF            46 uses
 OBUF            15 uses
 BUFTH           3 uses
-AND2            304 uses
-INV             263 uses
-OR2             27 uses
-XOR2            14 uses
+AND2            308 uses
+INV             261 uses
+OR2             25 uses
+XOR2            15 uses
 
 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@@ -103,6 +102,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:54 2015
+# Thu Sep 24 16:20:54 2015
 
 ###########################################################]

Logic/bus68030.srf

@@ -1,12 +1,12 @@
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: C:\ispLever\synpbase
-#OS: Windows 7 6.1
+#OS: Windows 7 6.2
 #Hostname: DEEPTHOUGHT
 
 #Implementation: logic
 
 $ Start of Compile
-#Thu Jul 09 18:48:52 2015
+#Thu Sep 24 16:20:52 2015
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
 @N|Running in 64-bit mode
@@ -42,14 +42,13 @@ State machine has 8 reachable states with original encodings of:
    110
    111
 @N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
-@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused 
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
 @END
 
 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:52 2015
+# Thu Sep 24 16:20:52 2015
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@@ -59,7 +58,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:53 2015
+# Thu Sep 24 16:20:53 2015
 
 ###########################################################]
 Map & Optimize Report
@@ -68,7 +67,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
 @N: MF248 |Running in 64-bit mode.
-@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
+@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:16:498:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -90,10 +89,10 @@ BI_DIR          11 uses
 IBUF            46 uses
 OBUF            15 uses
 BUFTH           3 uses
-AND2            304 uses
-INV             263 uses
-OR2             27 uses
-XOR2            14 uses
+AND2            308 uses
+INV             261 uses
+OR2             25 uses
+XOR2            15 uses
 
 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@@ -103,6 +102,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:54 2015
+# Thu Sep 24 16:20:54 2015
 
 ###########################################################]

Logic/dm/BUS68030_comp.xdm

@@ -26,8 +26,8 @@ S7RCVMI="F3s	Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
 SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
 />SqS<R"M=3ONsEDVHCP"R=""(/S>
 SR<qM3="lkF8DHCVDRC"P(=""
-/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.j"
-/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j6jnj"
+/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
+/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
 />SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
 <SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
 SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"

Logic/run_options.txt

@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version I-2014.03LC 
 #--  Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
-#--  Written on Thu Jul 09 18:48:52 2015
+#--  Written on Thu Sep 24 16:20:52 2015
 
 
 #project files

Logic/synlog/BUS68030_multi_srs_gen.srr

@@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:53 2015
+# Thu Sep 24 16:20:53 2015
 
 ###########################################################]

Logic/synlog/bus68030_fpga_mapper.srr

@@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
 @N: MF248 |Running in 64-bit mode.
-@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
+@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:16:498:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -24,10 +24,10 @@ BI_DIR          11 uses
 IBUF            46 uses
 OBUF            15 uses
 BUFTH           3 uses
-AND2            304 uses
-INV             263 uses
-OR2             27 uses
-XOR2            14 uses
+AND2            308 uses
+INV             261 uses
+OR2             25 uses
+XOR2            15 uses
 
 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@@ -37,6 +37,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:54 2015
+# Thu Sep 24 16:20:54 2015
 
 ###########################################################]

Logic/synlog/report/BUS68030_compiler_runstatus.xml

@@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
   <report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
   </info>
 			<info name="Warnings">
-  <data>13</data>
+  <data>12</data>
   <report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
   </info>
 			<info name="Errors">
@@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
   <data>-</data>
   </info>
 			<info name="Date &amp;Time">
-  <data type="timestamp">1436460532</data>
+  <data type="timestamp">1443104452</data>
   </info>
 			</job_info>
 </job_run_status>

Logic/synlog/report/BUS68030_compiler_warnings.txt

@@ -9,6 +9,5 @@
 @W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
 @W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
 @W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused 
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
 

Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml

@@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
 <data>105MB</data>
 </info>
 <info name="Date &amp; Time">
-<data type="timestamp">1436460534</data>
+<data type="timestamp">1443104454</data>
 </info>
 </job_info>
 </job_run_status>

Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt

@@ -1,2 +1,2 @@
-@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
+@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:16:498:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
 @W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE

Logic/syntmp/BUS68030_srr.htm

@@ -1,38 +1,38 @@
 <html><body><samp><pre>
-<!@TC:1436460532>
+<!@TC:1443104452>
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: C:\ispLever\synpbase
-#OS: Windows 7 6.1
+#OS: Windows 7 6.2
 #Hostname: DEEPTHOUGHT
 
 #Implementation: logic
 
 <a name=compilerReport1>$ Start of Compile</a>
-#Thu Jul 09 18:48:52 2015
+#Thu Sep 24 16:20:52 2015
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: : <!@TM:1436460532> | Running in 64-bit mode 
+@N: : <!@TM:1443104452> | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1436460532> | Setting time resolution to ns
-@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1436460532> | Top entity is set to BUS68030.
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1443104452> | Setting time resolution to ns
+@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1443104452> | Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1436460532> | Synthesizing work.bus68030.behavioral 
-<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:7:126:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1436460532> | Signal clk_out_pre is undriven </font>
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1443104452> | Synthesizing work.bus68030.behavioral 
+<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:7:126:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1443104452> | Signal clk_out_pre is undriven </font>
 Post processing for work.bus68030.behavioral
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1436460532> | Pruning register AMIGA_BUS_ENABLE_INT_4  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1436460532> | Pruning register CLK_000_D4_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1436460532> | Pruning register CLK_000_D3_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1436460532> | Pruning register CLK_000_D2_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:35:127:38:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1436460532> | Pruning register CLK_OUT_INT_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:36:124:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1436460532> | Pruning register CLK_OUT_PRE_50_D_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1436460532> | Pruning register CLK_030_D0_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:135:61:135:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(135)</a><!@TM:1436460532> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
-<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1436460532> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
-<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1436460532> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
-@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1436460532> | Trying to extract state machine for register SM_AMIGA
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Pruning register AMIGA_BUS_ENABLE_INT_4  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1443104452> | Pruning register CLK_000_D4_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1443104452> | Pruning register CLK_000_D3_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1443104452> | Pruning register CLK_000_D2_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:35:127:38:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1443104452> | Pruning register CLK_OUT_INT_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:36:124:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1443104452> | Pruning register CLK_OUT_PRE_50_D_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1443104452> | Pruning register CLK_030_D0_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:135:61:135:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(135)</a><!@TM:1443104452> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
+<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1443104452> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
+<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -43,25 +43,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1436460532> | Trying to extract state machine for register cpu_est
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1436460532> | Input port bits 23 to 20 of a(31 downto 2) are unused </font>
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1436460532> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Trying to extract state machine for register cpu_est
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1443104452> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
 @END
 
 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:52 2015
+# Thu Sep 24 16:20:52 2015
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: : <!@TM:1436460533> | Running in 64-bit mode 
+@N: : <!@TM:1443104453> | Running in 64-bit mode 
 File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:53 2015
+# Thu Sep 24 16:20:53 2015
 
 ###########################################################]
 Map & Optimize Report
@@ -69,8 +68,8 @@ Map & Optimize Report
 <a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014</a>
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1436460534> | Running in 64-bit mode. 
-<font color=#A52A2A>@W:<a href="@W:MO111:@XP_HELP">MO111</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:497:16:497:19:@W:MO111:@XP_MSG">68030-68000-bus.vhd(497)</a><!@TM:1436460534> | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) </font>
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1443104454> | Running in 64-bit mode. 
+<font color=#A52A2A>@W:<a href="@W:MO111:@XP_HELP">MO111</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:498:16:498:19:@W:MO111:@XP_MSG">68030-68000-bus.vhd(498)</a><!@TM:1443104454> | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) </font>
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -81,8 +80,8 @@ original code -> new code
    101 -> 00100001
    110 -> 01000001
    111 -> 10000001
-@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:190:4:190:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(190)</a><!@TM:1436460534> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
-<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1436460534> | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE</font>
+@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:190:4:190:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(190)</a><!@TM:1443104454> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1443104454> | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE</font>
 ---------------------------------------
 <a name=resourceUsage3>Resource Usage Report</a>
 
@@ -92,20 +91,20 @@ BI_DIR          11 uses
 IBUF            46 uses
 OBUF            15 uses
 BUFTH           3 uses
-AND2            304 uses
-INV             263 uses
-OR2             27 uses
-XOR2            14 uses
+AND2            308 uses
+INV             261 uses
+OR2             25 uses
+XOR2            15 uses
 
 
-@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1436460534> | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1443104454> | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:54 2015
+# Thu Sep 24 16:20:54 2015
 
 ###########################################################]
 

Logic/syntmp/BUS68030_toc.htm

@@ -16,7 +16,7 @@
 <li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>  
 <ul rel="open" >
 <li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li></ul></li>
-<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (18:48 09-Jul)</a>  
+<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (16:20 24-Sep)</a>  
 <ul  ></ul></li>         </ul>
         </li>
    </ul>

Logic/syntmp/run_option.xml

@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Thu Jul 09 18:48:52 2015
+  Written on Thu Sep 24 16:20:52 2015
 
 
 --> 

Logic/syntmp/statusReport.html

@@ -33,12 +33,12 @@
   <tr>
   <td class="optionTitle">Compile Input</td><td>Complete</td>
  <td>6</td>
- <td>13</td>
+ <td>12</td>
 <td>0</td>
 <td>-</td>
 <td>0m:00s</td>
 <td>-</td>
-<td><font size="-1">09.07.2015</font><br/><font size="-2">18:48:52</font></td>
+<td><font size="-1">24.09.2015</font><br/><font size="-2">16:20:52</font></td>
 </tr> 
 
  <tr>
@@ -49,12 +49,12 @@
 <td>0m:00s</td>
 <td>0m:00s</td>
 <td>105MB</td>
-<td><font size="-1">09.07.2015</font><br/><font size="-2">18:48:54</font></td>
+<td><font size="-1">24.09.2015</font><br/><font size="-2">16:20:54</font></td>
 </tr> 
 
 <tr>
   <td class="optionTitle">Multi-srs Generator</td>
-  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">09.07.2015</font><br/><font size="-2">18:48:53</font></td> 		</tbody>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">24.09.2015</font><br/><font size="-2">16:20:53</font></td> 		</tbody>
      </table>
  </td></tr></table></body> 
  </html>

Logic/synwork/BUS68030_comp.fdep

@@ -9,7 +9,7 @@
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1436460513
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1443104440
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)

Logic/synwork/BUS68030_comp.fdeporig

@@ -9,7 +9,7 @@
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1436460513
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1443104440
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)

Logic/synwork/BUS68030_comp.tlg

@@ -23,5 +23,4 @@ State machine has 8 reachable states with original encodings of:
    110
    111
 @N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
-@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused 
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused