Warp-LC/fpga/WarpLC.prj

verilog work "ipcore_dir/PLL.v"
verilog work "ipcore_dir/L2WayRAM.v"
verilog work "L2CacheWay.v"
verilog work "ipcore_dir/PrefetchTagRAM.v"
verilog work "ipcore_dir/PrefetchDataRAM.v"
verilog work "SizeDecode.v"
verilog work "Prefetch.v"
verilog work "L2Cache.v"
verilog work "CS.v"
verilog work "ClkGen.v"
verilog work "WarpLC.v"
idk 2021-10-31 15:39:28 -04:00			`verilog work "ipcore_dir/PLL.v"`
More cache stuff 2021-11-02 00:38:46 -04:00			`verilog work "ipcore_dir/L2WayRAM.v"`
			`verilog work "L2CacheWay.v"`
idk 2021-10-31 15:39:28 -04:00			`verilog work "ipcore_dir/PrefetchTagRAM.v"`
More cache stuff 2021-11-02 00:38:46 -04:00			`verilog work "ipcore_dir/PrefetchDataRAM.v"`
idk 2021-10-31 15:39:28 -04:00			`verilog work "SizeDecode.v"`
Cache stuff 2021-11-01 12:12:16 -04:00			`verilog work "Prefetch.v"`
More cache stuff 2021-11-02 00:38:46 -04:00			`verilog work "L2Cache.v"`
			`verilog work "CS.v"`
idk 2021-10-31 15:39:28 -04:00			`verilog work "ClkGen.v"`
screwing around 2021-10-29 10:04:15 -04:00			`verilog work "WarpLC.v"`