Warp-SE/cpld/WarpSE.v

158 lines
3.4 KiB
Coq
Raw Normal View History

2022-03-29 08:23:54 +00:00
module WarpSE(
2021-10-29 10:04:59 +00:00
input [23:1] A_FSB,
input nAS_FSB,
input nLDS_FSB,
input nUDS_FSB,
input nWE_FSB,
output nDTACK_FSB,
output nVPA_FSB,
output nBERR_FSB,
2023-03-22 01:11:58 +00:00
input FCLK,
input C16M,
input C8M,
input E,
2021-10-29 10:04:59 +00:00
input nDTACK_IOB,
input nVPA_IOB,
output nVMA_IOB,
output nAS_IOB,
output nUDS_IOB,
output nLDS_IOB,
2022-03-28 03:45:53 +00:00
output nBR_IOB,
input nBG_IOB,
2021-10-29 10:04:59 +00:00
input nBERR_IOB,
2022-09-04 01:32:05 +00:00
inout nRES,
2022-03-28 03:45:53 +00:00
input nIPL2,
2021-10-29 10:04:59 +00:00
output nROMCS,
output nRAMLWE,
output nRAMUWE,
output nROMWE,
output nRAS,
output nCAS,
output [11:0] RA,
output nOE,
output nADoutLE0,
output nADoutLE1,
output nAoutOE,
output nDoutOE,
output nDinOE,
2022-03-28 03:45:53 +00:00
output nDinLE,
2022-09-04 01:32:05 +00:00
input [3:1] SW,
2023-04-08 09:46:45 +00:00
input C20MEN,
2023-03-26 08:33:59 +00:00
output C25MEN);
2023-04-08 09:46:45 +00:00
/* FSB clock oscillator enable */
2023-03-26 08:33:59 +00:00
assign C25MEN = 1;
2022-03-28 03:45:53 +00:00
2022-09-04 01:32:05 +00:00
/* Reset input and open-drain output */
wire nRESin = nRES;
wire nRESout;
assign nRES = !nRESout ? 1'b0 : 1'bZ;
2021-10-29 10:04:59 +00:00
/* AS cycle detection */
wire BACT;
/* Refresh request/ack signals */
2023-03-26 08:33:59 +00:00
wire RefReq, RefUrg;
2021-10-29 10:04:59 +00:00
2023-03-22 01:11:58 +00:00
/* FSB chip select signals */
wire IOCS, IOPWCS, IACS;
2023-04-09 08:19:06 +00:00
wire ROMCS, ROMCS4X, SndROMCS;
2023-04-08 09:46:13 +00:00
wire RAMCS, RAMCS0X, SndRAMCSWR;
2021-10-29 10:04:59 +00:00
CS cs(
/* MC68HC000 interface */
2023-03-22 01:11:58 +00:00
A_FSB[23:08], FCLK, nRESin, nWE_FSB,
2021-10-29 10:04:59 +00:00
/* AS cycle detection */
BACT,
/* Device select outputs */
IOCS, IOPWCS, IACS,
2023-04-09 08:19:06 +00:00
ROMCS, ROMCS4X, SndROMCS,
2023-04-08 09:46:13 +00:00
RAMCS, RAMCS0X, SndRAMCSWR);
2021-10-29 10:04:59 +00:00
wire RAMReady;
2021-10-29 10:04:59 +00:00
RAM ram(
/* MC68HC000 interface */
2023-03-22 01:11:58 +00:00
FCLK, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */
2021-10-29 10:04:59 +00:00
BACT,
/* Select and ready signals */
RAMCS, ROMCS, RAMReady,
2021-10-29 10:04:59 +00:00
/* Refresh Counter Interface */
2023-03-26 08:33:59 +00:00
RefReq, RefUrg,
2021-10-29 10:04:59 +00:00
/* DRAM and NOR flash interface */
RA[11:0], nRAS, nCAS,
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
wire IONPReady, IOPWReady;
wire IORDREQ, IOWRREQ;
wire IOL0, IOU0;
2021-10-29 10:04:59 +00:00
wire ALE0S, ALE0M, ALE1;
assign nADoutLE0 = ~(ALE0S || ALE0M);
assign nADoutLE1 = ~ALE1;
wire IOACT, IODONE, IOBERR;
2021-10-29 10:04:59 +00:00
IOBS iobs(
/* MC68HC000 interface */
2023-03-22 01:11:58 +00:00
FCLK, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */
2021-10-29 10:04:59 +00:00
BACT,
2023-03-30 15:50:05 +00:00
/* Select signals */
IOCS, IOPWCS, ROMCS,
/* FSB cycle termination outputs */
IONPReady, IOPWReady, nBERR_FSB,
2021-10-29 10:04:59 +00:00
/* Read data OE control */
nDinOE,
/* IOB Master Controller Interface */
IORDREQ, IOWRREQ,
IOACT, IODONE, IOBERR,
2021-10-29 10:04:59 +00:00
/* FIFO primary level control */
ALE0S, IOL0, IOU0,
2021-10-29 10:04:59 +00:00
/* FIFO secondary level control */
ALE1);
2022-03-28 03:45:53 +00:00
2023-03-20 05:13:11 +00:00
wire AoutOE;
2023-03-25 07:49:44 +00:00
assign nAoutOE = !AoutOE;
2022-03-28 03:45:53 +00:00
wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
2023-03-25 07:49:44 +00:00
assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
2021-10-29 10:04:59 +00:00
IOBM iobm(
/* PDS interface */
2023-03-26 08:33:59 +00:00
C16M, C8M, E,
2022-09-04 01:32:05 +00:00
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
2023-03-25 07:49:44 +00:00
nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
2021-10-29 10:04:59 +00:00
/* PDS address and data latch control */
2023-03-20 04:53:10 +00:00
AoutOE, nDoutOE, ALE0M, nDinLE,
2021-10-29 10:04:59 +00:00
/* IO bus slave port interface */
IORDREQ, IOWRREQ, IOL0, IOU0,
IOACT, IODONE, IOBERR);
2021-10-29 10:04:59 +00:00
2023-04-08 09:46:13 +00:00
wire QoSReady;
2021-10-29 10:04:59 +00:00
CNT cnt(
2023-03-26 08:33:59 +00:00
/* FSB clock and E clock inputs */
FCLK, E,
2021-10-29 10:04:59 +00:00
/* Refresh request */
2023-03-26 08:33:59 +00:00
RefReq, RefUrg,
/* Reset, button */
nRESout, nIPL2,
2023-03-20 04:53:10 +00:00
/* Mac PDS bus master control outputs */
2023-04-08 09:46:13 +00:00
AoutOE, nBR_IOB,
/* Sound QoS */
2023-04-09 08:19:06 +00:00
BACT, nWE_FSB,
SndROMCS, SndRAMCSWR, RAMCS0X,
QoSReady);
2021-10-29 10:04:59 +00:00
FSB fsb(
/* MC68HC000 interface */
2023-03-22 01:11:58 +00:00
FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
/* FSB cycle detection */
BACT,
/* Ready inputs */
ROMCS4X,
RAMCS0X, RAMReady,
IOPWCS, IOPWReady, IONPReady,
2023-04-09 08:19:06 +00:00
QoSReady,
2021-10-29 10:04:59 +00:00
/* Interrupt acknowledge select */
2023-04-09 08:19:06 +00:00
IACS);
2021-10-29 10:04:59 +00:00
endmodule