ce9a1a6d9e
A bit more clean-up
2024-05-09 19:09:06 -07:00
a95b06f703
Minor code clean-up
2024-05-08 07:07:32 -07:00
cb88bab67d
ppcopcodes: Fixes for SPRs.
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- Rename DEC to DEC_S and add DEC_U.
- MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction.
- For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601.
- For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC.
- For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
2024-04-10 07:21:54 -07:00
67a5c39b1c
ppcopcodes: Add Privileged exception for SPRs.
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Accessing an SPR with bit 4 set (> 15) requires supervisor privilege and should cause a supervisor-level instruction exception (privileged instruction type program exception).
2024-04-10 07:21:23 -07:00
0273867c49
ppcopcodes: Cleanup ppc_changecrf0.
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- Use one assignment to set ppc_state.cr.
- Use enums for CR and XER bits.
- Use < to check sign bit.
2024-04-10 06:47:10 -07:00
1e50d88183
ppcopcodes: Use macro to grab instruction fields.
2024-04-10 06:46:46 -07:00
29a832c68d
ppcopcodes: Use < 0 instead of & 0x8000000.
2024-04-10 06:45:31 -07:00
cb05bd05eb
cpu: Add ppc_grab_regssash macro.
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This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
2024-04-10 06:43:34 -07:00
b9c12e44a4
ppcopcodes: Cleanup 3.
2024-03-28 07:36:40 -07:00
094f44e92c
ppcopcodes: Make MQ read only on non-601 CPUs.
2024-03-28 07:29:50 -07:00
5b4ed01bec
ppcexec: Make separate enum for shift instructions.
2024-03-27 18:43:46 -07:00
64df253053
ppcexec: Rename bool function enums.
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Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
b5b14b2f9d
ppcopcodes: cosmetic improvements.
2024-03-27 03:36:17 +01:00
9b429cc751
ppcopcodes: replace magic numbers with XER constants.
2024-03-27 03:36:17 +01:00
19ba15f2f1
ppc: Separate enums for separate fields.
2024-03-26 06:44:26 -07:00
9da9967b83
ppcopcodes: Cleanup 2.
2024-03-26 06:37:45 -07:00
3c3d0b46db
Merge branch 'master' into cpu-refactor2
2024-03-25 07:45:21 -07:00
b9aae48517
ppcopcodes: Fix templated st.
2024-03-25 07:37:54 -07:00
e2864ab08c
ppcopcodes: Fix templated add.
2024-03-25 07:37:52 -07:00
30802affd4
Continued fixes for tables
2024-03-24 17:24:36 -07:00
eab021a5cb
Regression fixes
2024-03-24 16:34:42 -07:00
5631485465
Cleaning up templating
2024-03-24 14:06:07 -07:00
c281b27220
Attempted templating for interpreter
2024-03-24 12:21:19 -07:00
4ef3c792de
Refactoring interpreter, pt. 1
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Reduce the number of global variables used by interpreter
2024-03-22 08:01:29 -07:00
3b3634bf5f
Continued cleanup for bcl
2024-03-08 19:28:51 -07:00
daeecbe99e
Clean-up bc and bcl
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Using templating to make the code a touch more readable
2024-03-08 19:22:25 -07:00
eb07a3c2f1
Templating bclr to match with bcctr
2024-03-07 20:44:36 -07:00
e1d43b8eb2
ppcopcodes: Cleanup branch instructions.
2024-03-07 06:56:37 -07:00
67bd47f11f
ppcopcodes: Fixes for bcctr(l)?.
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Add MPC601 variants. Variants that decrement and test the ctr are invalid bon't don't appear to trigger an exception. The manual says MPC601 can decrement the counter. Other CPUs do not decrement the counter but will branch based on the value.
2024-03-07 06:55:54 -07:00
c9aed600b6
More opcode clean-up
2024-03-02 07:57:15 -07:00
2b3cf58b8a
Continued clean-up
2024-03-01 19:40:46 -07:00
ebac8b92ba
Clean-up for loading instructions
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Expanding the scope of the clean-up from lscbx to other loading/storing instructions.
2024-03-01 07:57:46 -07:00
fe05b1de12
Fix compiler warnings.
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Xcode build has compiler warnings involving loss of precision. Remove them by adding type casts. Check results in some cases for overflow.
2024-02-29 18:49:14 -07:00
8e9123bdce
Slightly less clumsy check for compiler
2024-02-21 07:14:21 -07:00
2ea80b0aab
ppcopcodes: Cleanup.
2024-02-20 01:59:54 +01:00
5bbf5ee3af
ppcopcodes: Fix divw overflow result.
2024-02-20 01:59:40 +01:00
748e9c5d86
ppcopcodes: Write protect XER zero bits.
2024-02-20 01:59:01 +01:00
8764beba39
ppcopcodes: Fix lswx.
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- Remove invalid form check unless you know for sure it's supposed to cause an exception.
- Add register skip for 601 CPU. This needs testing.
2024-02-20 01:57:00 +01:00
cf4ce01ddd
ppcopcodes: set DSISR for alignment exception.
2024-02-20 01:22:55 +01:00
29f3ffd474
Continued clean-up, part 2
2024-02-18 07:06:27 -07:00
b160e38f8f
Continued code clean-up
2024-02-16 06:55:13 -07:00
38d94e509f
Further code cleanup
2024-02-14 22:19:08 -07:00
ec23a532f6
Minor clean-up for branching instructions
2024-02-12 20:59:04 -07:00
d0b0b8070c
ppcopcodes: Fix l*ux? invalid form check.
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Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
2024-02-11 07:41:13 -07:00
ff895aa8a4
ppcfpopcodes: Remove some globals.
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ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
2024-02-10 13:56:07 -07:00
6c49b87a06
ppcopcodes: Fix rlwnm when shift > 31.
2024-02-10 12:54:41 -07:00
29e5bbdcc0
ppcopcodes: Fix divw.
2024-02-10 12:54:12 -07:00
52dfc0cf93
Slightly faster typecasting
2024-01-31 08:06:33 -07:00
bf425884fb
ppcopcodes: Add ppc_grab_dab.
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For instructions that don't use the general purpose registers.
2024-01-19 12:09:24 +01:00
4430fd89a9
ppcopcodes: Fix subfic.
2024-01-19 12:00:55 +01:00
dingusdev
joevt
Maxim Poliakovski