60a76e9348
ppcexec: Fix branch check in ppc_exec_single.
2024-03-28 07:17:13 -07:00
f55ad323b4
ppcdisasm: Fix order of operands.
...
For cntlzw, extsh, extsb.
2024-03-28 07:09:50 -07:00
78558e4c52
debugger: Ensure space between opcode and operand.
...
Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
2024-03-28 06:54:23 -07:00
c9d4cc3321
ppcmmu: Remove old and slow code.
2024-03-27 20:13:45 -07:00
0f8a464157
ppcmmu: Use MSR enums for calculating mmu_mode.
2024-03-27 18:44:59 -07:00
e4a675babb
ppcmmu: Remove line feed from log messages.
2024-03-27 18:44:42 -07:00
5b4ed01bec
ppcexec: Make separate enum for shift instructions.
2024-03-27 18:43:46 -07:00
64df253053
ppcexec: Rename bool function enums.
...
Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
d8129bd643
ppcexec: Add comments for macros.
2024-03-27 18:43:15 -07:00
6aa54b8dda
ppcexec: break long lines, improve indentation.
2024-03-27 13:55:05 +01:00
0ff911cc26
poweropcodes: cosmetic improvements.
2024-03-27 03:45:22 +01:00
b5b14b2f9d
ppcopcodes: cosmetic improvements.
2024-03-27 03:36:17 +01:00
2b6f41e0d0
poweropcodes: use XER constants instead of magic numbers.
2024-03-27 03:36:17 +01:00
9b429cc751
ppcopcodes: replace magic numbers with XER constants.
2024-03-27 03:36:17 +01:00
ec56dffd19
Adding missing includes
2024-03-26 19:25:05 -07:00
a09f2093b5
Optimize register initialization
...
Courtesy of joevt, adapted to fit the C++ standard
2024-03-26 18:52:56 -07:00
b15d3be88a
Moving is_601 up, so the opcodes get initialized correctly
2024-03-26 18:41:16 -07:00
224ae50e91
ppcexec: Make more instructions illegal for 601.
2024-03-26 06:50:33 -07:00
03d7728d46
ppcexec: Use macros to assign subopcode functions.
2024-03-26 06:50:17 -07:00
19ba15f2f1
ppc: Separate enums for separate fields.
2024-03-26 06:44:26 -07:00
9da9967b83
ppcopcodes: Cleanup 2.
2024-03-26 06:37:45 -07:00
1510c45ecb
Fixed 601 flags
2024-03-26 06:36:32 -07:00
9b76c9fe3e
Fix for mffs in opcode table
2024-03-25 20:04:13 -07:00
3c3d0b46db
Merge branch 'master' into cpu-refactor2
2024-03-25 07:45:21 -07:00
f08d9ba81e
ppcexec: Fix templated lhzux.
2024-03-25 07:43:34 -07:00
b9aae48517
ppcopcodes: Fix templated st.
2024-03-25 07:37:54 -07:00
e2864ab08c
ppcopcodes: Fix templated add.
2024-03-25 07:37:52 -07:00
effe0198ce
ppcexec: Fix bcctr templated parameters.
2024-03-25 07:36:46 -07:00
c5ac862cef
debugger: Add list of input and output registers.
...
So the debugger can show them during stepping.
The fmt_* functions now take a PPCDisasmContext instead of just the ctx->instr_str so that they can alter the context.
Some fmt_* functions have an alternate (e.g. fmt_twoop_in for fmt_twoop) to indicate a difference in input/output registers.
The mtsrin and mfsrin instructions use a register to indicate which sr register to use.
The string instructions may affect multiple registers but only the first is included in the list.
Removed some extra blank lines.
Fixes:
lscbx: Add r0 check.
mftb: Do simplified if the spr is illegal. Maybe should do illegal opcode instead?
2024-03-24 19:34:29 -07:00
cd77e361ab
ppcexceptions: Use MSR enums.
2024-03-24 18:53:05 -07:00
bc5fd44172
ppcmmu: Don't log mmu_mode 1.
2024-03-24 18:52:49 -07:00
c781820bf6
Continued table fixes
2024-03-24 17:43:14 -07:00
30802affd4
Continued fixes for tables
2024-03-24 17:24:36 -07:00
eab021a5cb
Regression fixes
2024-03-24 16:34:42 -07:00
505b5e6468
Slight tweak to PPC Macros
2024-03-24 15:35:11 -07:00
5631485465
Cleaning up templating
2024-03-24 14:06:07 -07:00
c281b27220
Attempted templating for interpreter
2024-03-24 12:21:19 -07:00
1d5502dc3c
ppcemu: Make flags atomic.
...
For flags that might be accessed by other threads.
2024-03-22 19:04:51 -07:00
4ef3c792de
Refactoring interpreter, pt. 1
...
Reduce the number of global variables used by interpreter
2024-03-22 08:01:29 -07:00
833f74dce6
timemanager: Remove unnecessary parameter.
2024-03-16 11:36:41 -07:00
bc5153dd4a
ppcmmu: Make sure dummy page is 8 byte aligned.
2024-03-13 21:45:56 -07:00
aed74479fd
ppcmmu: Handle undefined mmu mode.
2024-03-13 21:38:26 -07:00
3b3634bf5f
Continued cleanup for bcl
2024-03-08 19:28:51 -07:00
daeecbe99e
Clean-up bc and bcl
...
Using templating to make the code a touch more readable
2024-03-08 19:22:25 -07:00
57e6e90002
Add support for the CUDA_RESTART_SYSTEM command
...
There are cases where when it's necessary (e.g. given uninitialized NVRAM,
the Beige G3 with the 10.2 install CD inserted will update the boot
device and restart to boot from it).
Restart support was done by wrapping the ppc_exec function in a loop and
checking for a restart power off reason. We also need to disconnect all
event listeners, since they will be recreated when the machine is
re-initialized.
2024-03-07 23:32:23 -08:00
c7d2eb87ac
Initialize MMU recently used regions in ppc_mmu_init
...
More encapsulated and allows re-initialization.
2024-03-07 23:31:56 -08:00
eb07a3c2f1
Templating bclr to match with bcctr
2024-03-07 20:44:36 -07:00
e1d43b8eb2
ppcopcodes: Cleanup branch instructions.
2024-03-07 06:56:37 -07:00
67bd47f11f
ppcopcodes: Fixes for bcctr(l)?.
...
Add MPC601 variants. Variants that decrement and test the ctr are invalid bon't don't appear to trigger an exception. The manual says MPC601 can decrement the counter. Other CPUs do not decrement the counter but will branch based on the value.
2024-03-07 06:55:54 -07:00
e44676e491
ppcfpopcodes: Template mffs variants.
2024-03-07 06:45:46 -07:00
30c6cbefbd
ppcexec: fix indentation, break long lines.
2024-03-06 23:28:40 +01:00
20b4a33c00
ppcexec: Remove EXHAUSTIVE_DEBUG.
2024-03-05 07:05:03 -07:00
f61055ebc0
ppcexec: Convert if to switch for ppc_opcode19.
2024-03-05 07:03:16 -07:00
177098c957
debugger: Fix interrupt signal.
...
Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return.
Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops).
Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F.
An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
2024-03-02 12:57:02 -07:00
de73a36399
ppcmmu: Move defines to the top.
2024-03-02 07:58:25 -07:00
c9aed600b6
More opcode clean-up
2024-03-02 07:57:15 -07:00
318e035344
ppcmmu: Shorten tlb_flush_entries.
2024-03-02 07:56:26 -07:00
cd097232cb
ppcmmu: Shorten tlb_flush_entry.
...
Don't need a weird short loop.
2024-03-02 07:56:17 -07:00
b7b783b6be
ppcmmu: Shorten ppc_mmu_init.
...
Also, initialize all the fields.
2024-03-02 07:50:02 -07:00
968f503d80
debugger: Improve my_sprintf for short strings.
...
Don't need to repeat snprintf with memory allocation if the string is short.
2024-03-02 07:24:17 -07:00
3bea3ec3d8
ppcmmu: Fix compiler warnings.
2024-03-01 20:12:42 -07:00
0f66d454c1
ppcmmu: Cleanup the cleanup.
2024-03-01 20:05:10 -07:00
6738d7472e
ppcmmu: Add a function to get phys address.
...
Since the function is for the debugger during stepping or disassembly, don't do extra logging.
2024-03-01 19:48:52 -07:00
500f38a496
ppcmmu: Add phys address to mmu_translate_imem.
...
For debugging.
2024-03-01 19:45:09 -07:00
3a5a70b56d
ppcmmu: Allow convert virtual to physical address.
...
The TLBEntries allow converting virtual guest address to virtual host address but there's no easy way to get a guest physical address for debugging purposes.
Add a phys_tag field to fix that.
2024-03-01 19:42:25 -07:00
15e132c824
cmake: Add header files in CMakeLists.txt.
...
So they will appear in Xcode project.
mkdir -p dingusppc/build-xcode
cd dingusppc/build-xcode
cmake -G Xcode ..
xcodebuild -configuration Release
2024-03-01 19:41:43 -07:00
2b3cf58b8a
Continued clean-up
2024-03-01 19:40:46 -07:00
ebac8b92ba
Clean-up for loading instructions
...
Expanding the scope of the clean-up from lscbx to other loading/storing instructions.
2024-03-01 07:57:46 -07:00
6a4326af39
poweropcodes: lscbx cleanup.
2024-03-01 07:46:04 -07:00
ff5c43e6cb
debugger: Add mregs command.
...
To dump more registers.
2024-02-29 21:46:44 -07:00
7cd3aae753
debugger: Fix repeated until.
...
The loop needs to be do while instead of while do.
2024-02-29 18:57:11 -07:00
fe05b1de12
Fix compiler warnings.
...
Xcode build has compiler warnings involving loss of precision. Remove them by adding type casts. Check results in some cases for overflow.
2024-02-29 18:49:14 -07:00
1903c8b557
debugger: Fix reg_op for floating point registers.
2024-02-29 18:48:59 -07:00
456a96042f
debugger: Shorten try catch in reg_op.
...
Because SPGR0 matches SPR but stoul causes an exception.
2024-02-29 07:55:09 -07:00
888df0ac53
debugger: Add more register names for reg_op.
...
So the debugger can output their values.
2024-02-29 07:46:16 -07:00
0c3f399de3
poweropcodes: fix compiler warning.
2024-02-24 22:51:05 +01:00
45ccabb11d
poweropcodes: improve lscbx emulation.
2024-02-24 22:46:54 +01:00
d71a213c4b
Continued clean-up, part 3
2024-02-22 19:46:34 -07:00
8e9123bdce
Slightly less clumsy check for compiler
2024-02-21 07:14:21 -07:00
9dad9ea38b
Revert Memory exceptions use mmu handler.
2024-02-20 18:22:55 -07:00
1d938c93b6
Mask fixes for sr(*)
2024-02-20 18:15:08 -07:00
35bc1bcb44
poweropcodes: Fix sriq.
2024-02-20 18:07:38 -07:00
1438ebc12a
poweropcodes: Fix compiler warnings.
2024-02-20 18:07:26 -07:00
61b29f6fab
ppcexceptions: Memory exceptions use mmu handler.
2024-02-20 18:07:04 -07:00
0e3eaf724b
ppcfpopcodes: Fix stfs*, attempt #2 .
2024-02-20 02:04:02 +01:00
2a05ccbee1
ppcfpopcodes: Fix fres.
...
Don't convert to float until the end.
2024-02-20 02:03:41 +01:00
59bee01c0a
ppcfpopcodes: Fix fmsubs inf nan check.
...
There's probably still an issue with the inf_nan check
using reg_a for the first value instead of reg_a * reg_c.
This will probably need rewriting anyway.
2024-02-20 02:02:58 +01:00
4e4c8d71be
ppcfpopcodes: Fix fadds inf nan check.
2024-02-20 02:01:55 +01:00
c7ae31dfce
ppcfpopcodes: Spaces.
2024-02-20 02:01:37 +01:00
2ea80b0aab
ppcopcodes: Cleanup.
2024-02-20 01:59:54 +01:00
5bbf5ee3af
ppcopcodes: Fix divw overflow result.
2024-02-20 01:59:40 +01:00
748e9c5d86
ppcopcodes: Write protect XER zero bits.
2024-02-20 01:59:01 +01:00
8764beba39
ppcopcodes: Fix lswx.
...
- Remove invalid form check unless you know for sure it's supposed to cause an exception.
- Add register skip for 601 CPU. This needs testing.
2024-02-20 01:57:00 +01:00
cf4ce01ddd
ppcopcodes: set DSISR for alignment exception.
2024-02-20 01:22:55 +01:00
29f3ffd474
Continued clean-up, part 2
2024-02-18 07:06:27 -07:00
b160e38f8f
Continued code clean-up
2024-02-16 06:55:13 -07:00
38d94e509f
Further code cleanup
2024-02-14 22:19:08 -07:00
ec23a532f6
Minor clean-up for branching instructions
2024-02-12 20:59:04 -07:00
d0b0b8070c
ppcopcodes: Fix l*ux? invalid form check.
...
Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
2024-02-11 07:41:13 -07:00
fd81d7b040
ppcfpopcodes: Fix load float.
...
Type casting an int to a float assigns the value of the int to the float which is not what is needed here.
2024-02-11 07:40:17 -07:00
joevt
Maxim Poliakovski
dingusdev
Mihai Parparita