Commit Graph

536 Commits

Author SHA1 Message Date
joevt
456a96042f debugger: Shorten try catch in reg_op.
Because SPGR0 matches SPR but stoul causes an exception.
2024-02-29 07:55:09 -07:00
joevt
888df0ac53 debugger: Add more register names for reg_op.
So the debugger can output their values.
2024-02-29 07:46:16 -07:00
Maxim Poliakovski
0c3f399de3 poweropcodes: fix compiler warning. 2024-02-24 22:51:05 +01:00
Maxim Poliakovski
45ccabb11d poweropcodes: improve lscbx emulation. 2024-02-24 22:46:54 +01:00
dingusdev
d71a213c4b Continued clean-up, part 3 2024-02-22 19:46:34 -07:00
dingusdev
8e9123bdce Slightly less clumsy check for compiler 2024-02-21 07:14:21 -07:00
dingusdev
9dad9ea38b Revert Memory exceptions use mmu handler. 2024-02-20 18:22:55 -07:00
dingusdev
1d938c93b6 Mask fixes for sr(*) 2024-02-20 18:15:08 -07:00
joevt
35bc1bcb44 poweropcodes: Fix sriq. 2024-02-20 18:07:38 -07:00
joevt
1438ebc12a poweropcodes: Fix compiler warnings. 2024-02-20 18:07:26 -07:00
joevt
61b29f6fab ppcexceptions: Memory exceptions use mmu handler. 2024-02-20 18:07:04 -07:00
joevt
0e3eaf724b ppcfpopcodes: Fix stfs*, attempt #2. 2024-02-20 02:04:02 +01:00
joevt
2a05ccbee1 ppcfpopcodes: Fix fres.
Don't convert to float until the end.
2024-02-20 02:03:41 +01:00
joevt
59bee01c0a ppcfpopcodes: Fix fmsubs inf nan check.
There's probably still an issue with the inf_nan check
using reg_a for the first value instead of reg_a * reg_c.
This will probably need rewriting anyway.
2024-02-20 02:02:58 +01:00
joevt
4e4c8d71be ppcfpopcodes: Fix fadds inf nan check. 2024-02-20 02:01:55 +01:00
joevt
c7ae31dfce ppcfpopcodes: Spaces. 2024-02-20 02:01:37 +01:00
joevt
2ea80b0aab ppcopcodes: Cleanup. 2024-02-20 01:59:54 +01:00
joevt
5bbf5ee3af ppcopcodes: Fix divw overflow result. 2024-02-20 01:59:40 +01:00
joevt
748e9c5d86 ppcopcodes: Write protect XER zero bits. 2024-02-20 01:59:01 +01:00
joevt
8764beba39 ppcopcodes: Fix lswx.
- Remove invalid form check unless you know for sure it's supposed to cause an exception.
- Add register skip for 601 CPU. This needs testing.
2024-02-20 01:57:00 +01:00
joevt
cf4ce01ddd ppcopcodes: set DSISR for alignment exception. 2024-02-20 01:22:55 +01:00
dingusdev
29f3ffd474 Continued clean-up, part 2 2024-02-18 07:06:27 -07:00
dingusdev
b160e38f8f Continued code clean-up 2024-02-16 06:55:13 -07:00
dingusdev
38d94e509f Further code cleanup 2024-02-14 22:19:08 -07:00
dingusdev
ec23a532f6 Minor clean-up for branching instructions 2024-02-12 20:59:04 -07:00
joevt
d0b0b8070c ppcopcodes: Fix l*ux? invalid form check.
Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
2024-02-11 07:41:13 -07:00
joevt
fd81d7b040 ppcfpopcodes: Fix load float.
Type casting an int to a float assigns the value of the int to the float which is not what is needed here.
2024-02-11 07:40:17 -07:00
joevt
267a9448ea ppctest: Fix floating-point tests.
genppctests.py
- Fix incorrect bits for some floating-point instruction opcodes or fields.
- Use separate register for FP results like DolphinPPCTests does.
- Remove extra FMULS.
- Use a regular expression for parsing ppcfloattest.txt. Don't parse the values, just put them in the output ppcloattests.csv file.

ppcfloattest.txt
- Clear crf0 and crf7 because we only care about crf1.
- Use values from DolphinPPCTests (0.0, 0.5, 1.0, 3.5, DBL_MAX, FLT_MAX, 2.4679999352, 4.9359998704, etc.). Some of the values were rounded. This will un-round them. Specify snan or qnan instead of nan.
- One of the FCMPO and FCMPU tests had qnan instead of snan input values.

ppcfloattest.csv
- Regenerate this file using the updated genppctests.py which uses the updated ppcfloattest.txt.

ppctests
- Update double_from_string to be able to parse the new values (snan, qnan, FLT_MAX, DBL_MAX).
2024-02-10 14:56:21 -07:00
joevt
01e45d656e ppcfpopcodes: Update header date. 2024-02-10 14:47:46 -07:00
joevt
9199b1e520 ppcfpopcodes: Fix multiply add opcodes.
Use std::fma for all of them for max accuracy.
For single precision opcodes, convert only the result, not the operands.
2024-02-10 14:19:09 -07:00
joevt
3be22dac99 ppcfpopcodes: No float cast for operand check. 2024-02-10 14:18:49 -07:00
joevt
ff895aa8a4 ppcfpopcodes: Remove some globals.
ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
2024-02-10 13:56:07 -07:00
joevt
c9c4280e6e ppcfpopcodes: No float cast for operand check. 2024-02-10 13:02:49 -07:00
joevt
dac9c1e52c ppcfpopcodes: Fix fctiw* round to nearest.
0.3 should not round up to 1.
2024-02-10 12:58:58 -07:00
joevt
a7e6ab33a1 ppcfpopcodes: Make fctiw* results QNaN. 2024-02-10 12:58:29 -07:00
joevt
6c49b87a06 ppcopcodes: Fix rlwnm when shift > 31. 2024-02-10 12:54:41 -07:00
joevt
29e5bbdcc0 ppcopcodes: Fix divw. 2024-02-10 12:54:12 -07:00
joevt
4fcb357e2f ppcfpopcodes: add 601 variant of mffs. 2024-02-10 12:51:48 -07:00
joevt
ddb5259464 ppcexec: Make illegal operations per CPU model. 2024-02-10 12:51:00 -07:00
dingusdev
52dfc0cf93 Slightly faster typecasting 2024-01-31 08:06:33 -07:00
joevt
bf425884fb ppcopcodes: Add ppc_grab_dab.
For instructions that don't use the general purpose registers.
2024-01-19 12:09:24 +01:00
joevt
4430fd89a9 ppcopcodes: Fix subfic. 2024-01-19 12:00:55 +01:00
dingusdev
a0b1d6394a Another revert
This affects Virtus VR - With the lmw checks, the opening sign doesn't display and the intro crashes sooner
2024-01-07 17:45:05 -07:00
dingusdev
c6af1e31fe Partial revert of previous commit 2024-01-07 17:21:11 -07:00
dingusdev
a5ce6a806f CPU clean-up 2024-01-07 17:04:51 -07:00
dingusdev
a59475af1c Further lha(*) fixes 2024-01-05 19:10:05 -07:00
dingusdev
1cc1ac2e68 Fixing lha(*) opcodes 2024-01-05 17:19:03 -07:00
dingusdev
924b80574a Further fix from last commit 2024-01-05 15:53:56 -07:00
dingusdev
f3a759c80d CPU code clean-up 2024-01-05 15:11:37 -07:00
Maxim Poliakovski
9b30dfb474 ppcfpopcodes: refactor fctiw/fctiwz emulation. 2024-01-03 01:27:21 +01:00
joevt
0100e67ebf ppcfpopcodes: Fix fctiw/fctiwz. 2024-01-03 01:07:53 +01:00
joevt
bd419912b5 ppcfpopcodes: Fix stfs*.
It should try to convert its operand to a single precision
floating point number at least.
2024-01-02 21:53:03 +01:00
Maxim Poliakovski
cb85d358d1 Remove unused globals. 2024-01-02 17:51:12 +01:00
Maxim Poliakovski
5b114c2412 ppcopcodes: refactor mtcrf emulation. 2024-01-02 17:44:35 +01:00
Maxim Poliakovski
c25b027de4 ppcfpopcodes: fix mtfsf emulation. 2024-01-02 17:21:08 +01:00
Maxim Poliakovski
8595dd7d99 ppcfpopcodes: fix mtfsfi emulation. 2024-01-02 17:21:08 +01:00
joevt
61a90e2cfb ppcfpopcodes: Fix mcrfs. 2024-01-02 15:52:30 +01:00
Maxim Poliakovski
593508df22 Refactor subfze. 2024-01-02 13:44:56 +01:00
joevt
1f3505f371 ppcopcodes: Fix subfze. 2024-01-02 13:44:13 +01:00
Maxim Poliakovski
fef5bde0c7 Refactor recent subfme fix. 2023-12-24 02:56:47 +01:00
joevt
dc00879419 ppcopcodes: Fix subfme. 2023-12-24 02:36:34 +01:00
joevt
bae488fd97 ppcfpopcodes: Fix lfs* opcodes. 2023-12-22 13:11:13 +01:00
joevt
0a8c1df968 ppcopcodes: Fix sraw. 2023-12-19 16:30:02 +01:00
joevt
4c49558120 ppcopcodes: Fix subfe. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
750f91e339 ppcemu.h: add enum for XER bits. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
d24b5d21b8 CRx_bit enum stores masks for now. 2023-12-19 14:27:57 +01:00
Maxim Poliakovski
9dbfde1a4c Cleanup previous commit. 2023-12-19 13:15:10 +01:00
joevt
7f229b0fe8 ppcfpopcodes: Fix fcmpo/fcmpu.
It was always changing CR1 (starting at CR bit 4) instead of the CR selected by crfD.
Also, it was clearing all but the FL,FG,FE,FU bits of FPRF of FPSCR.
2023-12-19 13:15:10 +01:00
dingusdev
7cf3d9cd94
Merge pull request #72 from mihaip/upstream-ub
Avoid some undefined behavior
2023-12-08 06:45:44 -07:00
joevt
c28e1fa0be ppcmmu: Fix write accesses to read-only memory. 2023-12-08 11:15:04 +01:00
Mihai Parparita
e9bc8926ab Avoid some undefined behavior
The `SubOpcode31Grabber[1024] = { ppc_illegalop }` initializer only
populates the first entry with ppc_illegalop (at least on some compilers),
switch to explicitly initializing the entire array with std::fill_n.

Also fix a couple of sign and overflow issues flagged by the Xcode
undefined behavior sanitizer.
2023-12-07 23:59:49 -08:00
Maxim Poliakovski
99ae0c3d31 ppcemu.h: add PVR definition for MPC604e. 2023-12-03 20:05:19 +01:00
Mihai Parparita
6582536591 Inline ppc_set_cur_instruction
It's used in the main emulator loop (ppc_exec_inner), and the function
call overhead adds up.

By inlining it, time to boot to the Finder using a 7.1.2 install CD
and a 6100 ROM goes from ~6700ms to ~6400ms (with clang 14 on a
M2 Max)
2023-12-02 15:12:02 -08:00
Maxim Poliakovski
819d475181 poweropcodes: fix div emulation.
Clean up power_doz and power_maskir as well.
2023-12-01 20:41:22 +01:00
dingusdev
277be165b6
Merge pull request #67 from mihaip/upstream-power
Fix emulation of doz, dozi, and nabs POWER instructions
2023-12-01 07:48:38 -07:00
Mihai Parparita
1b4de3b64e Fix emulation of doz, dozi, and nabs POWER instructions
doz and dozi were storing the result into the wrong register.

nabs was not taking into account two's complement storage of numbers
and was just setting the signed bit.

These two instructions are used in the implementation of text
measurement in native QuickDraw on 7.1.2/the PDM ROM, and the incorrect
values were resulting in nothing being rendered. With the fix text
appears when booting from the 7.1.2 CD.
2023-12-01 01:34:12 -08:00
Maxim Poliakovski
a1d8f8aa4e ppctests: fix test cases with SNaN/QNaN operands. 2023-11-30 17:44:46 +01:00
Maxim Poliakovski
8c3dfe94c7 ppcfpopcodes: infinities should set FPCC_FUNAN. 2023-11-30 12:53:10 +01:00
Maxim Poliakovski
0a9107b602 ppcfloattests.csv: remove unrelated CR7 changes. 2023-11-30 12:28:32 +01:00
Maxim Poliakovski
680cab52f3 ppcfpopcodes: fix ppc_fadds. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
6abb07e61b Add rounding control for the host FPU. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
b59c2be12d ppcfpopcodes: fix fpresult_update(). 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
d49d03846f ppcemu: fix and beatify FPSCR enum. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
b51670cb25 ppcfpopcodes: improve mffs, mtfsb0 and mtfsb1. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
487c6c2c7c ppcfpopcodes: remove dead code. 2023-11-30 12:06:44 +01:00
dingusdev
87b8a8e0a0 Correcting multiply tests 2023-11-28 19:02:48 -07:00
Maxim Poliakovski
47e0c23e64 Fix CR1 updates for floating-point instructions. 2023-11-28 16:31:51 +01:00
dingusdev
dd454689e0 Fixes for condition reg move instructions 2023-11-28 07:06:04 -07:00
dingusdev
4753ba5361 Continued clean-up 2023-11-23 16:56:58 -07:00
dingusdev
7835aec034 Further CPU cleanup 2023-11-21 08:06:50 -07:00
dingusdev
f4f035682c Fixed cfloat include 2023-11-19 20:34:40 -07:00
dingusdev
d1f9b5631a Added missing include for cfloat 2023-11-19 20:07:00 -07:00
dingusdev
d92ae6136a CPU code clean-up in progress
Happened to fix one case in the process.
2023-11-19 17:56:30 -07:00
dingusdev
074a760b6a FP compare fixes
This is the start of several fixes for the floating point emulation.
2023-11-13 07:30:31 -07:00
Mihai Parparita
35c86ad6bf Clean up #includes
Result of running IWYU (https://include-what-you-use.org/) and
applying most of the suggestions about unncessary includes and
forward declarations.

Was motivated by observing that <thread> was being included in
ppcopcodes.cpp even though it was unused (found while researching
the use of threads), but seems generally good to help with build
times and correctness.
2023-11-03 00:33:47 -07:00
dingusdev
6ffc2b2f10 Optimize string word instructions
Partially unrolled the loop. Boots 7.1.2 Disk Tools slightly faster.
2023-10-29 17:23:31 -07:00
joevt
5b366e592c Fix spelling. 2023-10-02 15:06:51 +02:00
joevt
170a9d78e7 Fix comment. 2023-10-02 15:06:06 +02:00
Maxim Poliakovski
a5fb124e69 pdmonboard: switch to mmu_map_dma_mem. 2023-10-02 15:00:12 +02:00
Maxim Poliakovski
8cf290c034 ppcmmu: add mmu_map_dma_mem method. 2023-10-02 02:20:42 +02:00
joevt
67146028bf ppcmmu: Add 64-bit accesses to I/O.
Also add an exception for unaligned 64 bit. 64 bit accesses require dword alignment.
2023-09-30 00:29:01 +02:00
joevt
acdb14a10a Recalculate execution block after RFI.
While booting Mac OS X 10.2 installer CD, a return from RFI didn't change the instruction address virtual memory page but did change the physical memory page so we must always recalculate the physical address after RFI.
Perhaps there are other cases where this may be required?
2023-09-26 00:13:11 +02:00
joevt
dcd4384d46 Fix eb_end calculation.
- Subtract one so that it can't overflow to zero.
- Use page_start as the base so mask operation is not required.
- Recalculate it only when the page changes.
2023-09-26 00:04:07 +02:00
joevt
8348370142 Add separate flags for instruction and data TLBs.
The same flag was being used for flushing both instruction and data TLBs so sometimes a flush for one TLB list would not occur if the flag was cleared when flushing the other TLB list.
2023-09-25 23:42:32 +02:00
joevt
6b3cdad877 ppcmmu: Fix BAT update.
Need to schedule flush of both BAT and PAT type TLBs because BAT takes precedence over PAT which means updating a BAT can invalidate a PAT.
2023-09-25 23:27:00 +02:00
joevt
6b40caf63a ppcmmu: fix setting of LRU bits. 2023-09-25 23:17:57 +02:00
Maxim Poliakovski
6cfde29f00 heathrow: implement native interrupt mode. 2023-09-25 12:22:17 +02:00
Maxim Poliakovski
278799795c Disable decrementer exceptions for MPC601. 2023-09-18 21:20:59 +02:00
Maxim Poliakovski
c47cbb354d Add is_601 flag for selecting MPC601 specific behavior. 2023-09-18 21:20:59 +02:00
Maxim Poliakovski
8ff2125312 Revert "Minor checks for Data Cache opcodes and LMW"
This reverts commit fd6327ab62.
2023-09-18 21:20:59 +02:00
Maxim Poliakovski
a69763c6de dbdma: noop incomplete LOAD_QUAD & STORE_QUAD. 2023-09-18 20:20:25 +02:00
dingusdev
5e32b599d6 Merge branch 'master' of https://github.com/dingusdev/dingusppc 2023-09-04 07:22:27 -07:00
dingusdev
fd6327ab62 Minor checks for Data Cache opcodes and LMW 2023-09-04 07:21:00 -07:00
Maxim Poliakovski
45528bfc6d ppcmmu: fix flushing of the secondary ITLB. 2023-08-22 23:36:48 +02:00
Maxim Poliakovski
932f2bbceb ppcopcodes: fix stwcx. emulation. 2023-08-21 04:50:02 +02:00
dingusdev
a7ef177164 Preliminary DBDMA expansion 2023-08-13 16:38:15 -07:00
joevt
300965ab10 Decrementer exception changes. 2023-08-10 00:46:04 +02:00
Maxim Poliakovski
d2e7c9a5df ppcexceptions: fix next address for decrementer exceptions. 2023-08-09 12:53:48 +02:00
Maxim Poliakovski
de1f0c8a9b ppc_mmu: rename reg_desc to rgn_desc to improve readability. 2023-08-07 13:56:49 +02:00
Maxim Poliakovski
52a64168d7 Clean up previous merge. 2023-08-07 13:45:26 +02:00
Maxim Poliakovski
b571ff8412 Revert "ppcmmu: Add 64-bit accesses to I/O"
This reverts commit 16123dea45.
2023-08-07 13:06:11 +02:00
joevt
ac64f9e30d ppcmmu: Fix mmio read/write offset calculation.
For TLBs referencing an mmio region, calculate an offset that will translate a guest virtual address to an offset in the mmio region.
2023-08-04 20:16:13 -07:00
joevt
16123dea45 ppcmmu: Add 64-bit accesses to I/O
Also add an exception for unaligned 64 bit. 64 bit accesses require dword alignment.
2023-08-04 20:16:13 -07:00
joevt
814260f0b6 ppcmmu: Reduce unmapped physical memory logging.
Don't log consecutive accesses to unmapped physical memory addresses. This saves a couple hundred thousand lines in the log in some cases.
This is only a partial fix. Any access that isn't logged should be queued and output if a log message is output that is not this log message or after a time period.
2023-08-04 20:16:13 -07:00
Maxim Poliakovski
25150268cd ppcexceptions: fix ISI exception target address. 2023-07-10 14:06:20 +02:00
dingusdev
4364c89fd4 Slight clean-up for execution type 2023-06-19 22:36:27 -07:00
Maxim Poliakovski
73d0356058 ppcopcodes: fix dcbz for BlockZero in Mac OS 8.x 2023-06-17 20:57:48 +02:00
Maxim Poliakovski
03595c3940 Merge remote-tracking branch 'origin/machine-yosemite' 2023-04-21 12:49:58 +02:00
Maxim Poliakovski
cf0d361918 Merge 'hard-disks' branch. 2023-04-17 01:20:38 +02:00
Maxim Poliakovski
597c077b19 Implement PPC decrementer. 2023-02-15 02:36:40 +01:00
Maxim Poliakovski
9fcf5ba51a ppcmmu: fix bug in mmu_change_mode(). 2023-02-15 02:18:31 +01:00
joevt
19adb54cd8 Fix compiler warnings.
These were detected by github Actions but not by Xcode.
2023-01-11 01:17:13 -08:00
joevt
5294a8b71c Fix compiler warnings: unused variables. 2023-01-11 01:17:12 -08:00
joevt
46bc8567e9 Fix compiler warnings: uninitialized variables.
- mpc601_block_address_translation will now return 0 for prot and pa when bat_hit is false (when the if statement is not positive during the for loop). The calling function doesn't care what prot and pa are when bat_hit is false, but we do this to remove the compiler warining.
- For tlb_flush_entry, the compiler thinks m might not always be in the range 0 to 5 so tlb1 and tlb2 might not get initialized by the switch statement. Add default to get around this warning.
2023-01-11 01:17:12 -08:00
joevt
64fec88436 Fix compiler warnings: cast loses precision.
Use explicit cast when converting large integer types to smaller integer types when it is known that the most significant bytes are not required.
For pcidevice, check the ROM file size before casting to int. We'll allow expansion ROM sizes up to 4MB but usually they are 64K, sometimes 128K, rarely 256K.
for machinefactory, change the type to size_t so that it can correctly get the size of files that are larger than 4GB; it already checks the file size is 4MB before we need to cast to uint32_t.
For floppyimg, check the image size before casting to int. For raw images, only allow files up to 2MB. For DiskCopy42 images, it already checks the file size, so do the cast after that.
2023-01-11 01:17:12 -08:00
Maxim Poliakovski
7ba8921649 ppcemu: add PVR for 603ev. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
648dfcd47b ppcmmu: fix BAT state updates. 2022-12-20 14:58:45 +01:00
Maxim Poliakovski
9f4c248e4c Rework DBDMA logic for bidirectional channels. 2022-11-17 18:03:18 +01:00
dingusdev
a58ce8aeb3 Slight tweak to lscbx 2022-11-15 08:01:57 -07:00
dingusdev
8f99510af0 Fixed lscbx 2022-11-15 07:40:37 -07:00
dingusdev
647ae456e5 Slight typo squash for lscbx 2022-11-12 20:18:33 -07:00
dingusdev
1b7ff084ab Cleaned lscbx 2022-11-12 20:17:04 -07:00
dingusdev
1ed6e25d1b Removed redundant variable
Slight clean-up for lswi and lswx
2022-11-12 20:16:29 -07:00
joevt
6f0d3b48ba Fix TBR range
Fixed an issue where TBR doesn't have full 64-bit range. The original calculation was 64 bit and ended with a ÷ 10^9. This means the max for the upper 32 bits is 2^32/10^9 = 4. The solution is to use a multiplication method that supports a 96 bit product. core/mathutils.h contains functions for that. TBR driving frequency is assumed to be less than 1 GHz. Some minor modification is required for future > 1 GHz support.
2022-09-15 21:22:37 -07:00
joevt
b665f2cb4e Fix RTC units
Fixed an issue where get-msecs-601 and get-msecs-60x were not returning the same value. RTC was being calculated using timebase frequency instead of nanosecond frequency. 601 uses RTC. 60x uses TBR. On a real Mac, a G3 CPU won't have a RTC and accessing RTC would cause an exception. This is not the case for dingusppc but I don't think that's a problem.
2022-09-15 21:05:08 -07:00
joevt
ed424ad544 Fix setting RTC
Fixed an issue where setting RTC upper or lower doesn't adjust the other (since the current time has changed since the last timestamp).
2022-09-15 20:59:56 -07:00
joevt
50dbd5eccd Fix RTC not always updating
Fixed an issue where RTC was not being updated if only the upper 32 bits (seconds) was read.
Also simplified things by always updating the timestamp instead of only when the seconds changes.
2022-09-15 20:54:22 -07:00
joevt
01d7d6bac3 Make accessing RTC or TBR not affect the other
Fixed an issue where the following would cause inconsistent results (tb in the left column would sometimes decrement instead of always incrementing):
2 0 do 2 0 do cr tb@ 8 u.r ." ." 8 u.r loop 2 0 do cr 12 spaces rtc@ 8 u.r ." ." 8 u.r loop 2 0 do cr tb@ 8 u.r ." ." 8 u.r space rtc@ 8 u.r ." ." 8 u.r loop loop

RTC and TBR could not be used simultaneously because they are both incremented by an amount based on the last time stamp but that time stamp can be changed by accessing either RTC or TBR. The solution is to have a different time stamp for each.
2022-09-15 20:21:54 -07:00
joevt
ce925f5e56 Fix RTC upper
Fixed a typo that caused rtc@ to always return 0 for the upper 32 bits (represents seconds).
The problem could cause the following to hang on Power Mac 7500:
cr 2000 0 do get-msecs u. 1 ms loop
2022-09-15 19:34:46 -07:00
Maxim Poliakovski
b38d00ce2d cpu/ppc: improve support for external interrupts.
Support generating of external interrupt exception
in MTMSR and RFI when MSR[EE] is re-enabled and
external interrupt still pending.
2022-08-24 14:15:47 +02:00