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32133b2261
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Author SHA1 Message Date
gbeauche
32133b2261 Add PPC_PROFILE_GENERIC_CALLS, don't enable PPC_PROFILE_COMPILE_TIME by 
default.
 2003-12-01 13:51:35 +00:00
gbeauche
e2ca6270f8 Implement ISYNC, MTCRF, MCRF. 2003-12-01 13:40:38 +00:00
gbeauche
054748532a NOP'ize unimplemented instructions 2003-12-01 13:21:41 +00:00
gbeauche
dd956c78db gather some stats on untranslated instructions 2003-12-01 13:07:26 +00:00
gbeauche
32f34c07c5 fix stack allocation, really roundup to next 16 KB boundaries 2003-12-01 11:02:13 +00:00
gbeauche
f034ae704f handle ROM areas and put associated blocks into dormant state 2003-12-01 00:16:21 +00:00
gbeauche
ceb9b4a428 cleanups & optimize for constant branches (i.e. follow them). 2003-12-01 00:03:02 +00:00
gbeauche
4a3cd024ed better handling of static translation cache allocation, handle nested 
execution paths from the cpu core, cleanups for KPX_MAX_CPUS == 1.
 2003-11-30 17:21:53 +00:00
gbeauche
c1dba58808 fix & reenable asm compare ops for ppc 2003-11-30 17:18:17 +00:00
gbeauche
10db506aa5 handle CR cache though it's not efficient with current approach without 
superblock (traces) optimization.
 2003-11-30 17:17:32 +00:00
gbeauche
7594e26d36 fix new block creation on full cache that was just invalidated, add 
provisions for following constants jumps in next commit.
 2003-11-30 17:16:24 +00:00
gbeauche
833fc0c935 remove dead code 2003-11-30 17:13:10 +00:00
gbeauche
efad4ff3b6 Handle even more XER test masks to be preserved or to be set. 2003-11-30 09:07:36 +00:00
gbeauche
d0a2277325 Gather stats about compile time. Define KPX_MAX_CPUS to 1 for allowing 
allocation of translation cache into .data section on PowerPC.
 2003-11-28 22:13:50 +00:00
gbeauche
0301afb3eb first part of CR caching fixes 2003-11-28 22:11:59 +00:00
cebix
ea0d909ce5 run depmod after installing module 2003-11-28 15:49:16 +00:00
gbeauche
6a7c8f7e83 Add PowerPC tester glue for Microlib CPU core 2003-11-28 15:12:37 +00:00
gbeauche
3bea82fa1c fix merge, hunks were missing 2003-11-27 23:59:00 +00:00
gbeauche
8ca440d0b5 Fix SRAW on non PowerPC platforms. 2003-11-27 23:53:41 +00:00
gbeauche
8711c4afd6 Add support for external results file for non PowerPC platforms. 2003-11-27 23:52:19 +00:00
gbeauche
687b9c5a74 I manually synchronize with Kheperix code. 2003-11-27 20:07:33 +00:00
gbeauche
aee3e05e4b The JIT should work now but there is an extra bottleneck causing it to 
not match Kheperix speeds while executing Linux/ppc binaries.

Fix x86 DYNGEN_OP_FLAGS settings. Only allocate translation cache in .data
on PPC since x86 can do jumps anywhere.
 2003-11-27 11:09:38 +00:00
gbeauche
2bacb2fd01 Workaround CR expectations in MODE_68K execution 2003-11-27 11:06:23 +00:00
gbeauche
d7ac6a0e68 Fix SLW & SRW, an x86 does not work the same way as a ppc 2003-11-27 10:53:37 +00:00
gbeauche
ae2d91912c fix dummy includes 2003-11-27 10:06:27 +00:00
gbeauche
36ce9c07e6 Statically allocate the translation cache on PowerPC. This makes it possible 
to generate direct bl instructions for function invokation.
 2003-11-27 00:26:35 +00:00
gbeauche
e30001bc00 Fix BCCTR & BCLR. However, conditions are still wrong somehow, disabled 
this case. Factored & optimized branch instructions.
 2003-11-26 23:58:14 +00:00
gbeauche
2eba241021 self credit cpu emulator ;-) 2003-11-25 10:27:59 +00:00
gbeauche
73d51962f6 Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC. 
The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.

Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.
 2003-11-24 23:45:52 +00:00
gbeauche
7968a20100 Handle "JIT1" engine but disable it for now since there are some problems 
with SheepShaver integration from Kheperix.
 2003-11-24 23:39:35 +00:00
gbeauche
10c04e2654 Enable possibility to manually pass VM_MAP_32BIT & friends. This is needed 
for the PowerPC "JIT1" engine.
 2003-11-24 23:27:18 +00:00
gbeauche
09a774ae51 Add link to B2 Unix/config.{guess,sub} 2003-11-24 22:19:35 +00:00
gbeauche
2a0f750a83 Optimize memory accesses on little endian systems that can do unaligned 
accesses to memory. Fix build when vm.hpp is included in a C program.
 2003-11-24 21:30:17 +00:00
gbeauche
04349eebce Optimized bswap_32() for AMD64 2003-11-24 21:20:47 +00:00
gbeauche
1dbe1179c6 Merge in "keycodes" support from Basilisk II. e.g. make French keyboard 
layout work correctly for me.
 2003-11-21 17:01:33 +00:00
gbeauche
45df157a5e Implement lazy icache range invalidation. Disable for now until it shows 
a real benefit over only 2%
 2003-11-21 14:20:01 +00:00
gbeauche
1af0362296 fix loff_t & caddr_t type checks 2003-11-21 14:16:02 +00:00
gbeauche
3630404307 fix fp_do_sgn1() for "double"-targets 2003-11-21 13:27:47 +00:00
gbeauche
5b950fa2ef fix shm screen image allocation. 2003-11-20 16:24:57 +00:00
gbeauche
b7c917e6d1 little endian fixes to name registry 2003-11-20 15:54:10 +00:00
nigel
d9a7e20b8b Latest changes from Unix version (which I don't think work) 2003-11-18 11:19:35 +00:00
nigel
39cc371988 Latest changes from Unix version (mostly signal/page zero fixes) 2003-11-18 11:17:55 +00:00
nigel
ee0958380c Compile fix for OS X (which does not define loff_t) 2003-11-18 11:14:43 +00:00
gbeauche
e9f3546539 Remove even more obsolete code. Drop TBL/TBU registers, they are manually 
handled through the mftb instruction accessor.
 2003-11-11 11:44:34 +00:00
gbeauche
cf0ed72f24 Remove obsolete code related to PPC_NO_FPSCR_UPDATE, PPC_LAZY_PC_UPDATE, 
PPC_LAZY_CC_UPDATE, PPC_HAVE_SPLIT_CR defines.
 2003-11-11 11:32:27 +00:00
gbeauche
d4ad77d734 really fix writes to byte registers 2003-11-11 00:10:39 +00:00
gbeauche
4bce0876c0 fix configure tests. i.e. move up arch_insn_skipper_tests() 2003-11-10 23:54:31 +00:00
gbeauche
1169001df7 Extend x86 instruction skipper to AMD64. Add plenty of arch dependent 
opcodes to test it. Also fix DEBUG output & writes (zero'ing) to %xH regs
 2003-11-10 23:47:39 +00:00
gbeauche
b66d8ef433 Fix "ignoresegv" case to actually skip the faulty instruction. Merge 
conditions to skip instruction on SIGSEGVfrom PowerPC native mode. The
instruction skipper takes care to set the output register to 0.
 2003-11-10 16:23:58 +00:00
gbeauche
26ec1b8899 Merge Set_pthread_attr() from Basilisk II. 2003-11-10 16:05:52 +00:00