Alexei Svitkine
b150b42fc6
Fix some string conversion warnings.
2017-12-10 11:27:08 -05:00
Alexei Svitkine
181634ab31
Fix more Xcode8 warnings and tweak project settings.
2016-12-17 23:31:03 -05:00
asvitkine
581ff8d86f
add prefs option to ignore illegal instructions (ignoreillegal)
2009-07-20 18:50:28 +00:00
gbeauche
3b6a579f33
Optimize lwarx/stwcx for uniprocessors and generate code for them. There is
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no performance increase even though those two instructions represented approx
18M of untranslated instructions on a simple boot to MacOS.
2007-01-18 07:02:35 +00:00
gbeauche
e020d63591
Fix frsp FPSCR[OX] condition
2006-07-04 23:17:37 +00:00
gbeauche
78952866b4
Fix mtfsb0 & mtfsb1 (VEX's xlc_dbl_u32 + code review)
2006-07-04 10:41:48 +00:00
gbeauche
7efab4276f
Improve FPU emulation accurracy. However, PPC_ENABLE_FPU_EXCEPTIONS is still
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set to 0 until generated code is optimized enough (current slow down factor
is 3x vs. previous core, expectations are about 50% slower FP code).
The main benefit is exception bits are accurate. All glibc test-fenv,
test-arith{,f}, test-double, test-float pass on ppc, and mostly on x86_64
with gcc 4.0.1. Yes, this is also compiler dependent.
FIXME: find a real Mac application that depends on precise FPSCR bits... I
think I don't want to care optimizing yet until someone shows me a real world
application.
2006-07-04 07:19:18 +00:00
gbeauche
dc3df920c5
Fix fctiw emulation (VEX's jm-ppc-test -f, handle current rounding mode)
2006-07-04 06:58:24 +00:00
gbeauche
635ee55a5d
Fix floating-point single precision load/store (VEX's jm-ppc-test -f)
2006-07-04 04:21:02 +00:00
gbeauche
022d09375f
Merge from KPX: new exit() handling code; make "syscall" illegal for MacOS
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emulation (SheepShaver)
2006-01-28 21:57:52 +00:00
gbeauche
dd2b9a95d5
Align PowerPC registers struct manually, i.e. don't depend on non-portable
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compiler extensions (e.g. GCC __attribute__((aligned(N)))).
2005-12-06 22:25:13 +00:00
gbeauche
8db2a3ef62
implement lvsl/lvsr instructions
2005-04-15 17:03:49 +00:00
gbeauche
7cc49ca739
fix vsldoi implementation and testsuite
2005-03-13 11:38:35 +00:00
gbeauche
7df6429591
Support NetBSD 2.0 for x86:
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- implement trunc() function, isless() and isgreater() macros
- execute genexec.pl through a real perl executable
- disable generation of debug info from dyngen u-ops
2005-02-13 15:32:11 +00:00
gbeauche
df0d5d2a41
Happy New Year 2005!
2005-01-30 21:48:22 +00:00
gbeauche
a8a235345c
implement mcrxr instruction
2004-12-18 22:13:47 +00:00
gbeauche
26a128bf6a
use new ieeefp.hpp wrapping over <fenv.h>
2004-11-22 22:55:50 +00:00
gbeauche
0669b02e5f
Introducce TimebaseSpeed which represents exact timebase-frequency instead
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of supposing it to be (BusClockSpeed/4), which is no longer true on G5 et al.
2004-07-03 10:39:07 +00:00
gbeauche
1988a45a16
More realistic "mftb" implementation, aka. fix AbsoluteToNanoseconds() and
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generally speaking UpTime()-based stopwatchers.
2004-06-22 15:48:50 +00:00
gbeauche
ea3c6801ab
Experiment with generic AltiVec optimizations for V4SF, V2DI operands (+60%)
2004-02-16 23:17:27 +00:00
gbeauche
d10a3586f1
Year got increased "recently". ;-)
2004-02-16 10:57:07 +00:00
gbeauche
313cddeeb2
AltiVec emulation! ;-)
2004-02-15 17:17:37 +00:00
gbeauche
82808234fa
Merge in FP exceptions support but disable it for now as it is incomplete
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and slower. Implement mcrfs. Fix and optimize fctiw with native rounding.
2004-01-24 16:43:45 +00:00
gbeauche
07f0be19b5
Fix FP single operations. aka fix scrollbar & Graphing Calculator bugs.
2004-01-13 23:50:09 +00:00
gbeauche
8ca440d0b5
Fix SRAW on non PowerPC platforms.
2003-11-27 23:53:41 +00:00
gbeauche
73d51962f6
Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC.
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The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.
Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.
2003-11-24 23:45:52 +00:00
gbeauche
e9f3546539
Remove even more obsolete code. Drop TBL/TBU registers, they are manually
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handled through the mftb instruction accessor.
2003-11-11 11:44:34 +00:00
gbeauche
cf0ed72f24
Remove obsolete code related to PPC_NO_FPSCR_UPDATE, PPC_LAZY_PC_UPDATE,
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PPC_LAZY_CC_UPDATE, PPC_HAVE_SPLIT_CR defines.
2003-11-11 11:32:27 +00:00
gbeauche
cd86ff9e94
- Start emulating the FPSCR. Fix mtfsf, mffs.
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- Implement mftbr so that MacOS can fully boot with extensions. However,
using clock() is probably not the right solution. Patching UpTime from
DriverServicesLib et al. may be a better solution.
2003-11-09 15:39:30 +00:00
gbeauche
59e6227c08
fix mullwo & divw on invalid inputs
2003-11-09 07:19:39 +00:00
gbeauche
175dfeea02
fix lfs/stfs breakage introduced with latest FPR type change
2003-11-04 20:56:21 +00:00
gbeauche
30bd089279
PowerPC floating-point registers are now an union of uint64 & double. This
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eases FP load/stores.
2003-11-04 15:03:15 +00:00
gbeauche
a42281aad1
Implement partial block cache invalidation. Rewrite core cached blocks
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execution loop with a Duff's device. Gather some predecode time statistics.
This shows that only around 2% of total emulation time is spent for
predecoding the instructions.
2003-11-03 21:28:32 +00:00
gbeauche
1b9876889e
- Record address range of block to invalidate. i.e. icbi records ranges
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and isync actually invalidate caches
2003-10-12 06:44:04 +00:00
gbeauche
1012da75dd
- Cleanups & make sure PPC emulator config is setup in sysdeps.h
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- Log r24 in SheepShaver mode as this represents the 68k emulator PC
2003-10-11 09:03:03 +00:00
gbeauche
5229b42622
basic implementation for missing functions (signbit/isless/isgreater) in
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older C libraries
2003-09-29 22:45:31 +00:00
gbeauche
2a86a4f62a
Handle dcbz. Ignore unaligned load/store multiple. Fix icbi/isync.
2003-09-28 21:22:59 +00:00
gbeauche
089247fcff
Merge in cpu core:
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- make cache invalidation routines public
- fix shift instructions, especially for invalid shift counts
- fix mullwo to set overflow only if the product can't be represented in
32 bits
2003-09-15 22:48:57 +00:00
gbeauche
fb8fbf71ed
PowerPC emulator fixes:
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- make divw. behaviour more realistic (vs ppc 7410) when rB == 0
- fix carry/overflow computations to fix SUBFME handling
- fix nand duplicate with wrong operand
2003-09-14 22:09:13 +00:00
gbeauche
029a7fd85b
Merge in old kpx_cpu snapshot for debugging
2003-09-07 14:25:05 +00:00
