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dev-SRAM
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19 Commits

Author SHA1 Message Date
Zane Kaminski c4844b9646 idk 2021-04-11 15:39:19 -04:00
Zane Kaminski b0b8b0dc6c Works? 2021-04-03 03:44:42 -04:00
Zane Kaminski 9eec9bf7b9 ugh 2021-03-19 16:38:48 -04:00
Zane Kaminski 116abb1a6f before remove UFM 2021-03-19 14:23:33 -04:00
Zane Kaminski 9ac2ba97ae better 2021-03-19 06:45:31 -04:00
Zane Kaminski 3816ecd0a1 ugh 2021-03-19 02:56:20 -04:00
Zane Kaminski e5da11855d Remove old CPLD stuff 2021-03-15 13:40:41 -04:00
Zane Kaminski b29662bcab Fixed previous problem, working again 2020-02-16 00:11:12 -05:00
Zane Kaminski 6e135d4305 Fixed bugs in new PLD stuff 2019-10-20 22:41:24 -04:00
Zane Kaminski f471e04244 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
 2019-10-18 15:07:38 -04:00
Zane Kaminski a8eb7940fe Recompiled just to be sure 2019-10-13 21:18:41 -04:00
Zane Kaminski 7f581f6ba0 24-bit counter, CAS fixed 2019-10-11 20:34:51 -04:00
Zane Kaminski 66fc09b402 Made AddrH high bit variable with mode input 2019-09-07 21:16:23 -04:00
Zane Kaminski 7ea556dd34 Clarified assignments 2019-09-06 17:26:42 -04:00
Zane Kaminski f52c6e4781 Pipelined addition 2019-09-04 21:45:56 -04:00
Zane Kaminski a87ee9c819 Trying again with RamFactor firmware 2019-09-02 20:56:37 -04:00
Zane Kaminski 215f5ca2c6 Clarifications and bugfixes, will try again 2019-09-02 01:42:07 -04:00
Zane Kaminski 6b2378f99a 1MB CPLD design seems to work, fails Apple BIST 2019-09-01 21:18:44 -04:00
Zane Kaminski 396cc3c03c CPLD firmware compiles 2019-08-31 22:55:04 -04:00