13 Commits

Author	SHA1	Message	Date
Zane Kaminski	7b4a492e6c	Output read data on falling edge to get more hold time	2021-04-21 09:19:57 -04:00
Zane Kaminski	d88ccfb802	Documentation update	2021-04-20 01:49:44 -04:00
Zane Kaminski	a444cc31aa	idk	2021-03-15 13:40:59 -04:00
Zane Kaminski	db594211fa	Fabbed	2021-02-17 19:29:24 -05:00
Zane Kaminski	7d6776e480	Board done?	2020-10-07 23:32:57 -04:00
Zane Kaminski	911557e38b	Removed AVR-JTAG-10 connector footprint	2020-02-09 03:40:57 -05:00
Zane Kaminski	c02ffbbe6a	Separated CSDBEN	2020-01-26 15:13:37 -05:00
Zane Kaminski	f471e04244	New PLD revision ... For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.	2019-10-18 15:07:38 -04:00
Zane Kaminski	3b0ca6584a	New schematic revision	2019-10-13 01:40:49 -04:00
Zane Kaminski	5cc0e2fe26	added some disassembly of RamFactor	2019-09-05 13:50:38 -04:00
Zane Kaminski	215f5ca2c6	Clarifications and bugfixes, will try again	2019-09-02 01:42:07 -04:00
Zane Kaminski	396cc3c03c	CPLD firmware compiles	2019-08-31 22:55:04 -04:00
Zane Kaminski	dac5bdb451	Submitted to JLCPCB	2019-07-30 17:11:31 -04:00