72 Commits

Author	SHA1	Message	Date
Steven Hugg	24d681cbb8	fixed ball_paddle.v	2018-10-09 19:37:38 -04:00
Steven Hugg	706a24c96a	updated presets, changed array syntax, ice40 fpga examples	2018-10-08 20:38:39 -04:00
Steven Hugg	190ea9fbda	verilog tank example	2018-10-03 18:49:14 -04:00
Steven Hugg	716205a2b1	fixed unit tests	2018-10-03 15:06:48 -04:00
Steven Hugg	5c5ee32a66	verilog pixel editor fix (array index must be unsized)	2018-10-02 11:24:29 -04:00
Steven Hugg	684a642ad0	fixed multiplex issue in racing_game	2018-10-01 22:03:44 -04:00
Steven Hugg	1a7480ea65	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-10-01 13:36:56 -04:00
Steven Hugg	7e00cc898b	verilog preset comments	2018-10-01 13:36:26 -04:00
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	51bf1226d0	moved declare vars to ui module imports	2018-09-17 14:45:22 -04:00
Steven Hugg	bd8c4da2d6	verilog presets; early exit from jsasm errors	2018-09-08 19:14:51 -04:00
Steven Hugg	9d70c0fb9c	changes to multisprite; moved inspect to vcs for now; local book links; z80 disasm	2018-08-28 07:44:57 -04:00
Steven Hugg	5b3c415c6f	debugging refactoring; fixed up embed.html; started DASM macro parse; Z80 stack view; replay wraps buffer > 120 secs; verilog edits	2018-08-25 13:50:18 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	b81f4d04b9	removeBOM(); new web images	2018-08-12 11:17:59 -04:00
Steven Hugg	7880602e81	nes runToVsync; debug info changes	2018-08-03 12:18:08 -04:00
Steven Hugg	318c4d8413	fixed verilog scope updating when clicked	2018-08-01 15:12:08 -04:00
Steven Hugg	2dbc60aa2e	updated presets; verilog code dup detect; need to handle local/ include files somehow	2018-07-31 23:03:53 -04:00
Steven Hugg	6e5005f613	look in cache first, fetch local/ verilog includes too; apple2 reset; platform checkmark	2018-07-25 13:02:44 -04:00
Steven Hugg	4ea23e21f2	fixed verilog local paths	2018-07-22 22:26:03 -04:00
Steven Hugg	d5a146bf71	update lsfr preset; filter verilog boring errors	2018-07-21 09:34:06 -05:00
Steven Hugg	9938a17093	moved to error line widgets	2018-07-20 16:40:38 -05:00
Steven Hugg	2fce80bc9d	fixed asmlines in inline asm; reset h/vpaddle on vsync; fixed framebuffer.v	2018-07-17 22:17:01 -05:00
Steven Hugg	d35a328246	fixed verilog inline asm	2018-07-12 06:50:40 -05:00
Steven Hugg	f466afa085	updated cpu_platform.v to have inputs	2018-07-11 19:53:05 -07:00
Steven Hugg	d6a702b929	fixed test, verilog; updated slip counter preset	2018-07-09 20:46:45 -05:00
Steven Hugg	c101292a9c	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-06-07 16:25:48 -07:00
Steven Hugg	e0e3e0bf61	paddles.v	2018-06-03 19:46:33 -07:00
Steven Hugg	0ee201b9e8	update presets; redir.html expire	2018-06-01 10:33:37 -07:00
Steven Hugg	7f972f7ced	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-05-27 11:13:27 -07:00
Steven Hugg	e29bfb5f7e	working on assembler	2018-05-27 11:13:06 -07:00
Steven Hugg	4a8380b730	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-05-25 14:11:32 -07:00
Steven Hugg	09fb489c2d	assembler: added .string .data .align	2018-04-16 20:16:58 -07:00
Steven Hugg	5b92659b97	"Save As"; command-line assembler; 32-bit limit (so far) in opcodes	2018-03-23 15:05:08 -06:00
Steven Hugg	1b3822050a	make sure inspect var is not array	2018-03-18 20:11:11 -05:00
Steven Hugg	f24213aa1d	fixed JSASM cache	2018-03-02 21:39:32 -06:00
Steven Hugg	c14e470778	can load verilog module from .asm file	2018-03-01 23:15:33 -06:00
Steven Hugg	725770ea3b	new presets	2018-03-01 20:17:37 -06:00
Steven Hugg	db005dc98e	can scroll scope when paused; updates to presets	2018-02-28 12:13:59 -06:00
Steven Hugg	8f1563f88e	sync vs async RAM	2018-02-28 09:26:37 -06:00
Steven Hugg	b5c74234f3	smoother scope transition; slowest/fastest buttons; video width tweak	2018-02-27 14:09:27 -06:00
Steven Hugg	73bb496511	pixel editor takes 8'hxx format; fixed minor bugs	2018-02-26 15:55:39 -06:00
Steven Hugg	6fa030f398	optimized scanline renderer	2018-02-25 10:53:52 -06:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	f6d320a05b	new inline verilog assembler	2018-02-18 11:14:04 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00
Steven Hugg	56ed79c14f	caspr inline assembly with __asm	2018-02-15 09:56:45 -06:00
Steven Hugg	6b4c3bdbc2	fallback to network if include fails	2018-02-14 14:58:38 -06:00
Steven Hugg	89b1c64ac8	minor changes; preset changes; rotate output	2018-02-14 13:38:50 -06:00