2021-07-23 01:16:23 +00:00
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//
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// Chipset.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef Chipset_hpp
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#define Chipset_hpp
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#include <cstddef>
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#include <cstdint>
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#include "../../Processors/68000/68000.hpp"
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2021-07-26 22:44:20 +00:00
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#include "../../Outputs/CRT/CRT.hpp"
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2021-07-23 01:16:23 +00:00
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#include "Blitter.hpp"
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2021-09-17 01:17:23 +00:00
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#include "Copper.hpp"
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#include "DMADevice.hpp"
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2021-07-23 01:16:23 +00:00
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namespace Amiga {
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2021-08-10 00:31:14 +00:00
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enum class InterruptFlag: uint16_t {
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SerialPortTransmit = 1 << 0,
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DiskBlock = 1 << 1,
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Software = 1 << 2,
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IOPortsAndTimers = 1 << 3, // i.e. CIA A.
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Copper = 1 << 4,
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VerticalBlank = 1 << 5,
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Blitter = 1 << 6,
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AudioChannel0 = 1 << 7,
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AudioChannel1 = 1 << 8,
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AudioChannel2 = 1 << 9,
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AudioChannel3 = 1 << 10,
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SerialPortReceive = 1 << 11,
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DiskSyncMatch = 1 << 12,
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External = 1 << 13, // i.e. CIA B.
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};
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enum class DMAFlag: uint16_t {
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AudioChannel0 = 1 << 0,
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AudioChannel1 = 1 << 1,
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AudioChannel2 = 1 << 2,
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AudioChannel3 = 1 << 3,
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Disk = 1 << 4,
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Sprites = 1 << 5,
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Blitter = 1 << 6,
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Copper = 1 << 7,
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Bitplane = 1 << 8,
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AllBelow = 1 << 9,
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BlitterPriority = 1 << 10,
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BlitterZero = 1 << 13,
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BlitterBusy = 1 << 14,
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};
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2021-07-23 01:16:23 +00:00
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class Chipset {
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public:
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2021-09-16 12:24:52 +00:00
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Chipset(uint16_t *ram, size_t word_size);
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2021-07-23 01:16:23 +00:00
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2021-07-24 01:24:07 +00:00
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struct Changes {
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int hsyncs = 0;
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int vsyncs = 0;
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2021-07-26 20:40:42 +00:00
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int interrupt_level = 0;
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2021-07-27 00:13:06 +00:00
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HalfCycles duration;
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2021-08-09 01:52:28 +00:00
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Changes &operator += (const Changes &rhs) {
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hsyncs += rhs.hsyncs;
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vsyncs += rhs.vsyncs;
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duration += rhs.duration;
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return *this;
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}
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2021-07-24 01:24:07 +00:00
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};
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2021-07-27 20:41:18 +00:00
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/// Advances the stated amount of time.
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Changes run_for(HalfCycles);
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/// Advances to the next available CPU slot.
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Changes run_until_cpu_slot();
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2021-07-23 01:16:23 +00:00
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/// Performs the provided microcycle, which the caller guarantees to be a memory access.
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void perform(const CPU::MC68000::Microcycle &);
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2021-07-28 23:36:30 +00:00
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/// Sets the current state of the CIA interrupt lines.
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void set_cia_interrupts(bool cia_a, bool cia_b);
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2021-07-26 20:40:42 +00:00
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/// Provides the chipset's current interrupt level.
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int get_interrupt_level() {
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return interrupt_level_;
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}
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2021-07-26 22:44:20 +00:00
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// The standard CRT set.
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void set_scan_target(Outputs::Display::ScanTarget *scan_target);
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Outputs::Display::ScanStatus get_scaled_scan_status() const;
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void set_display_type(Outputs::Display::DisplayType);
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Outputs::Display::DisplayType get_display_type() const;
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2021-07-23 01:16:23 +00:00
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private:
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2021-09-15 00:51:32 +00:00
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friend class DMADeviceBase;
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2021-08-09 21:35:09 +00:00
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2021-07-23 01:16:23 +00:00
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// MARK: - Interrupts.
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uint16_t interrupt_enable_ = 0;
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uint16_t interrupt_requests_ = 0;
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2021-07-26 20:40:42 +00:00
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int interrupt_level_ = 0;
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2021-07-23 01:16:23 +00:00
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2021-07-26 20:40:42 +00:00
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void update_interrupts();
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2021-08-10 00:31:14 +00:00
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void posit_interrupt(InterruptFlag);
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2021-07-23 01:16:23 +00:00
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2021-07-27 20:41:18 +00:00
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// MARK: - Scheduler.
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2021-08-09 01:52:28 +00:00
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template <bool stop_on_cpu> Changes run(HalfCycles duration = HalfCycles::max());
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2021-07-28 01:59:27 +00:00
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template <bool stop_on_cpu> int advance_slots(int, int);
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2021-07-27 20:41:18 +00:00
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template <int cycle, bool stop_if_cpu> bool perform_cycle();
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2021-07-28 01:33:07 +00:00
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template <int cycle> void output();
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2021-07-27 20:41:18 +00:00
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// MARK: - DMA Control, Scheduler and Blitter.
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2021-07-23 01:16:23 +00:00
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uint16_t dma_control_ = 0;
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Blitter blitter_;
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// MARK: - Sprites.
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struct Sprite {
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void set_pointer(int shift, uint16_t value);
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void set_start_position(uint16_t value);
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void set_stop_and_control(uint16_t value);
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void set_image_data(int slot, uint16_t value);
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} sprites_[8];
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2021-07-23 01:45:51 +00:00
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2021-08-10 23:01:41 +00:00
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// MARK: - Raster position and state.
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2021-07-23 01:45:51 +00:00
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2021-08-10 23:01:41 +00:00
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// Definitions related to PAL/NTSC.
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2021-07-28 01:33:07 +00:00
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int line_length_ = 227;
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2021-07-26 22:44:20 +00:00
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int frame_height_ = 312;
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2021-07-26 22:51:01 +00:00
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int vertical_blank_height_ = 29;
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2021-07-23 02:00:53 +00:00
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2021-08-10 23:01:41 +00:00
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// Current raster position.
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int line_cycle_ = 0, y_ = 0;
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// Parameters affecting bitplane collection and output.
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2021-07-23 02:00:53 +00:00
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uint16_t display_window_start_[2] = {0, 0};
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uint16_t display_window_stop_[2] = {0, 0};
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uint16_t fetch_window_[2] = {0, 0};
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2021-07-26 22:44:20 +00:00
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2021-08-10 23:01:41 +00:00
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// Ephemeral bitplane collection state.
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bool fetch_vertical_ = false, fetch_horizontal_ = false;
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2021-08-12 00:31:37 +00:00
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bool display_horizontal_ = false;
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2021-08-11 01:28:48 +00:00
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bool did_fetch_ = false;
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2021-08-10 23:01:41 +00:00
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2021-08-12 00:31:37 +00:00
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// Output state.
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uint16_t border_colour_ = 0;
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bool is_border_ = true;
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int zone_duration_ = 0;
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uint16_t *pixels_ = nullptr;
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void flush_output();
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2021-09-09 00:57:26 +00:00
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struct BitplaneData: public std::array<uint16_t, 6> {
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BitplaneData &operator >>= (int c) {
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(*this)[0] >>= c;
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(*this)[1] >>= c;
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(*this)[2] >>= c;
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(*this)[3] >>= c;
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(*this)[4] >>= c;
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(*this)[5] >>= c;
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return *this;
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}
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};
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2021-08-11 01:28:48 +00:00
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class Bitplanes: public DMADevice<6> {
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public:
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using DMADevice::DMADevice;
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template <bool is_odd> bool advance();
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void do_end_of_line();
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2021-08-11 22:47:35 +00:00
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void set_control(uint16_t);
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2021-08-11 01:28:48 +00:00
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private:
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bool is_high_res_ = false;
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int collection_offset_ = 0;
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2021-08-12 00:31:37 +00:00
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int plane_count_ = 0;
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2021-08-11 01:28:48 +00:00
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BitplaneData next;
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} bitplanes_;
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void post_bitplanes(const BitplaneData &data);
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2021-08-10 23:01:41 +00:00
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2021-09-09 00:57:26 +00:00
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BitplaneData current_bitplanes_, next_bitplanes_;
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// std::array<uint8_t, 912> even_playfield_;
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// std::array<uint8_t, 912> odd_playfield_;
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2021-08-11 22:47:35 +00:00
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int odd_delay_ = 0, even_delay_ = 0;
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2021-07-26 22:44:20 +00:00
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// MARK: - Copper.
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2021-09-17 01:17:23 +00:00
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Copper copper_;
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2021-07-30 22:24:27 +00:00
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// MARK: - Serial port.
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class SerialPort {
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public:
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void set_control(uint16_t) {}
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private:
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uint16_t value = 0, reload = 0;
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uint16_t shift = 0, receive_shift = 0;
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uint16_t status;
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} serial_;
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2021-07-26 22:44:20 +00:00
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2021-08-09 21:35:09 +00:00
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// MARK: - Disk drives.
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2021-08-11 01:28:48 +00:00
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class DiskDMA: public DMADevice<1> {
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2021-08-09 21:35:09 +00:00
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public:
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using DMADevice::DMADevice;
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void set_length(uint16_t value) {
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dma_enable_ = value & 0x8000;
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write_ = value & 0x4000;
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length_ = value & 0x3fff;
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if(dma_enable_) {
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2021-08-11 22:47:35 +00:00
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printf("Not yet implemented: disk DMA [%s of %d to %06x]\n", write_ ? "write" : "read", length_, pointer_[0]);
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2021-08-09 21:35:09 +00:00
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}
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}
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2021-08-10 11:17:01 +00:00
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bool advance();
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2021-08-10 00:31:14 +00:00
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2021-08-09 21:35:09 +00:00
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private:
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uint16_t length_;
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bool dma_enable_ = false;
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bool write_ = false;
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} disk_;
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2021-07-26 22:44:20 +00:00
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// MARK: - Pixel output.
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Outputs::CRT::CRT crt_;
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2021-07-26 22:59:11 +00:00
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uint16_t palette_[32]{};
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2021-08-11 22:47:35 +00:00
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uint16_t swizzled_palette_[32]{};
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2021-07-23 01:16:23 +00:00
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};
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}
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#endif /* Chipset_hpp */
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