2022-05-16 15:44:16 +00:00
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//
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// 68000Mk2Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef _8000Mk2Implementation_h
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#define _8000Mk2Implementation_h
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2022-05-16 20:57:40 +00:00
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#include <cassert>
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2022-05-17 18:08:50 +00:00
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#include <cstdio>
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2022-05-16 20:57:40 +00:00
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2022-05-19 20:27:39 +00:00
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#include "../../../InstructionSets/M68k/ExceptionVectors.hpp"
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2022-05-16 15:44:16 +00:00
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namespace CPU {
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namespace MC68000Mk2 {
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2022-05-18 19:35:38 +00:00
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/// States for the state machine which are named by
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/// me for their purpose rather than automatically by file position.
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/// These are negative to avoid ambiguity with the other group.
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enum ExecutionState: int {
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Reset = std::numeric_limits<int>::min(),
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Decode,
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WaitForDTACK,
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2022-05-19 14:27:51 +00:00
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/// Perform the proper sequence to fetch a byte or word operand.
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2022-05-19 14:47:57 +00:00
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FetchOperand_bw,
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2022-05-19 14:27:51 +00:00
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/// Perform the proper sequence to fetch a long-word operand.
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2022-05-19 14:47:57 +00:00
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FetchOperand_l,
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2022-05-19 14:27:51 +00:00
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2022-05-18 19:35:38 +00:00
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StoreOperand,
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2022-05-19 20:55:16 +00:00
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StoreOperand_bw,
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2022-05-19 15:23:26 +00:00
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StoreOperand_l,
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2022-05-18 19:35:38 +00:00
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2022-05-19 20:27:39 +00:00
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StandardException,
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BusOrAddressErrorException,
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2022-05-18 20:45:40 +00:00
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// Specific addressing mode fetches.
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2022-05-20 20:23:52 +00:00
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//
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// Additional context here is that I'm very much on the fence but
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// for now am telling myself:
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//
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// (1) the overwhelming majority of instructions that need an
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// effective address calculation use it for an operand read
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// immediately afterwards, so keeping those things bound
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// avoids a large number of conditional branches; and
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// (2) making a decision between byte/word and long-word once at
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// the outset also saves a conditional for any two-operand
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// instructions (which is also the majority); but
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// (3) some instructions do just need the address calculation —
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// LEA and PEA are obvious examples, but are not the
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// exhaustive list — so a third route just to do the
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// calculation is necessary.
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//
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// My internal dialogue then argues that each of these is actually
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// a small amount of code, so the need manually to duplicate (per
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// the control-flow constraints of using a switch as a coroutine)
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// isn't too ugly. Possibly even less ugly than pulling things out
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// with a macro, especially for debugging.
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//
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// Further consideration may be necessary. Especially once this is
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// up on its feet and profiling becomes an option.
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2022-05-18 20:45:40 +00:00
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2022-05-19 14:47:57 +00:00
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FetchAddressRegisterIndirect_bw,
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FetchAddressRegisterIndirectWithPostincrement_bw,
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FetchAddressRegisterIndirectWithPredecrement_bw,
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FetchAddressRegisterIndirectWithDisplacement_bw,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw,
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FetchProgramCounterIndirectWithDisplacement_bw,
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FetchProgramCounterIndirectWithIndex8bitDisplacement_bw,
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FetchAbsoluteShort_bw,
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FetchAbsoluteLong_bw,
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FetchImmediateData_bw,
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FetchAddressRegisterIndirect_l,
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FetchAddressRegisterIndirectWithPostincrement_l,
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FetchAddressRegisterIndirectWithPredecrement_l,
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FetchAddressRegisterIndirectWithDisplacement_l,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement_l,
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FetchProgramCounterIndirectWithDisplacement_l,
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FetchProgramCounterIndirectWithIndex8bitDisplacement_l,
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FetchAbsoluteShort_l,
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FetchAbsoluteLong_l,
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FetchImmediateData_l,
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2022-05-18 20:45:40 +00:00
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2022-05-20 20:23:52 +00:00
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CalcEffectiveAddress,
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CalcAddressRegisterIndirect,
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CalcAddressRegisterIndirectWithPostincrement,
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CalcAddressRegisterIndirectWithPredecrement,
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CalcAddressRegisterIndirectWithDisplacement,
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CalcAddressRegisterIndirectWithIndex8bitDisplacement,
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CalcProgramCounterIndirectWithDisplacement,
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CalcProgramCounterIndirectWithIndex8bitDisplacement,
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CalcAbsoluteShort,
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CalcAbsoluteLong,
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2022-05-18 19:35:38 +00:00
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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// indicated bus cycle.
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Perform_np,
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Perform_np_n,
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Perform_np_nn,
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2022-05-19 01:00:10 +00:00
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// MOVE has unique bus usage, so has specialised states.
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2022-05-19 01:00:10 +00:00
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MOVEw,
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MOVEwRegisterDirect,
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MOVEwAddressRegisterIndirectWithPostincrement,
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2022-05-20 11:02:02 +00:00
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TwoOp_Predec_bw,
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TwoOp_Predec_l,
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CHK,
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CHK_no_trap,
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CHK_was_over,
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CHK_was_under,
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2022-05-20 15:19:16 +00:00
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Scc_Dn,
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Scc_Dn_did_not_set,
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Scc_Dn_did_set,
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2022-05-20 15:32:06 +00:00
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DBcc,
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DBcc_branch_taken,
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DBcc_condition_true,
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DBcc_counter_overflow,
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2022-05-20 16:04:43 +00:00
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Bcc,
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Bcc_branch_taken,
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Bcc_b_branch_not_taken,
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Bcc_w_branch_not_taken,
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BSR,
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2022-05-21 14:29:36 +00:00
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JSRAddressRegisterIndirect,
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JSRAddressRegisterIndirectWithDisplacement,
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JSRAddressRegisterIndirectWithIndex8bitDisplacement,
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JSRProgramCounterIndirectWithDisplacement,
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JSRProgramCounterIndirectWithIndex8bitDisplacement,
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JSRAbsoluteShort,
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JSRAbsoluteLong,
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JSR_push,
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2022-05-20 16:58:45 +00:00
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BCHG_BSET_Dn,
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BCLR_Dn,
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2022-05-20 18:22:32 +00:00
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MOVEPtoM_w,
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MOVEPtoM_l,
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MOVEPtoR_w,
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MOVEPtoR_l,
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2022-05-20 18:29:14 +00:00
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LogicalToSR,
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2022-05-20 22:48:19 +00:00
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MOVEMtoR, MOVEMtoR_l_read, MOVEMtoR_w_read, MOVEMtoR_finish,
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2022-05-21 12:17:39 +00:00
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MOVEMtoM,
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MOVEMtoM_l_write, MOVEMtoM_w_write,
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MOVEMtoM_l_write_predec, MOVEMtoM_w_write_predec,
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MOVEMtoM_finish,
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2022-05-18 19:35:38 +00:00
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};
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2022-05-17 19:05:11 +00:00
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// MARK: - The state machine.
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2022-05-16 15:59:03 +00:00
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::run_for(HalfCycles duration) {
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// Accumulate the newly paid-in cycles. If this instance remains in deficit, exit.
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time_remaining_ += duration;
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if(time_remaining_ <= HalfCycles(0)) return;
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2022-05-16 15:59:03 +00:00
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// Check whether all remaining time has been expended; if so then exit, having set this line up as
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// the next resumption point.
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2022-05-17 00:38:17 +00:00
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#define ConsiderExit() if(time_remaining_ <= HalfCycles(0)) { state_ = __COUNTER__+1; return; } [[fallthrough]]; case __COUNTER__:
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// Subtracts `n` half-cycles from `time_remaining_`; if permit_overrun is false, also ConsiderExit()
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#define Spend(n) time_remaining_ -= (n); if constexpr (!permit_overrun) ConsiderExit()
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2022-05-17 01:00:25 +00:00
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// Performs ConsiderExit() only if permit_overrun is true.
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#define CheckOverrun() if constexpr (permit_overrun) ConsiderExit()
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2022-05-17 01:00:25 +00:00
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// Sets `x` as the next state, and exits now if all remaining time has been extended and permit_overrun is true.
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// Jumps directly to the state otherwise.
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#define MoveToState(x) { state_ = ExecutionState::x; goto x; }
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// Sets the start position for state x.
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#define BeginState(x) case ExecutionState::x: [[maybe_unused]] x
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2022-05-16 15:59:03 +00:00
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//
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// So basic structure is, in general:
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//
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// BeginState(Action):
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// do_something();
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// Spend(20);
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// do_something_else();
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// Spend(10);
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// do_a_third_thing();
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// Spend(30);
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// MoveToState(next_action);
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//
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// Additional notes:
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//
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// Action and all equivalents should be negative values, since the
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2022-05-17 00:38:17 +00:00
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// switch-for-computed-goto-for-a-coroutine structure uses __COUNTER__* for
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2022-05-16 15:59:03 +00:00
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// its invented entry- and exit-points, meaning that negative numbers are
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// the easiest group that is safely definitely never going to collide.
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//
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// (* an extension supported by at least GCC, Clang and MSVC)
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// Spare containers:
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HalfCycles delay; // To receive any additional time added on by calls to perform_bus_operation.
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2022-05-16 20:57:40 +00:00
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// Helper macros for common bus transactions:
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// Performs the bus operation and then applies a `Spend` of its length
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// plus any additional length returned by the bus handler.
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#define PerformBusOperation(x) \
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delay = bus_handler_.perform_bus_operation(x, is_supervisor_); \
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Spend(x.length + delay)
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// Performs no bus activity for the specified number of microcycles.
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#define IdleBus(n) \
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idle.length = HalfCycles(n * 4); \
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PerformBusOperation(idle)
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// Spin until DTACK, VPA or BERR is asserted (unless DTACK is implicit),
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// holding the bus cycle provided.
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#define WaitForDTACK(x) \
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if constexpr (!dtack_is_implicit && !dtack_ && !vpa_ && !berr_) { \
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awaiting_dtack = x; \
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awaiting_dtack.length = HalfCycles(2); \
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post_dtack_state_ = __COUNTER__+1; \
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state_ = ExecutionState::WaitForDTACK; \
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break; \
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} \
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[[fallthrough]]; case __COUNTER__:
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// Performs the bus operation provided, which will be one with a
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// SelectWord or SelectByte operation, stretching it to match the E
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// bus if VPA is currently asserted.
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//
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// TODO: If BERR is asserted, stop here and perform a bus error exception.
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//
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// TODO: If VPA is asserted, stretch this cycle.
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#define CompleteAccess(x) \
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PerformBusOperation(x)
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// Performs the memory access implied by the announce, perform pair,
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// honouring DTACK, BERR and VPA as necessary.
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2022-05-19 14:27:51 +00:00
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#define AccessPair(val, announce, perform) \
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perform.value = &val; \
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if constexpr (!dtack_is_implicit) { \
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announce.length = HalfCycles(4); \
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} \
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PerformBusOperation(announce); \
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WaitForDTACK(announce); \
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CompleteAccess(perform);
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2022-05-19 16:18:47 +00:00
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// Sets up the next data access size and read flags.
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#define SetupDataAccess(read_flag, select_flag) \
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2022-05-19 15:23:26 +00:00
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access_announce.operation = Microcycle::NewAddress | Microcycle::IsData | (read_flag); \
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access.operation = access_announce.operation | (select_flag);
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2022-05-19 14:27:51 +00:00
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2022-05-19 16:18:47 +00:00
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// Sets the address source for the next data access.
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#define SetDataAddress(addr) \
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access.address = access_announce.address = &addr;
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2022-05-19 14:27:51 +00:00
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// Performs the access established by SetupDataAccess into val.
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#define Access(val) \
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AccessPair(val, access_announce, access)
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// Reads the program (i.e. non-data) word from addr into val.
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2022-05-19 14:27:51 +00:00
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#define ReadProgramWord(val) \
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AccessPair(val, read_program_announce, read_program); \
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program_counter_.l += 2;
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// Reads one futher word from the program counter and inserts it into
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// the prefetch queue.
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#define Prefetch() \
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2022-05-17 12:26:35 +00:00
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prefetch_.high = prefetch_.low; \
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ReadProgramWord(prefetch_.low)
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2022-05-16 20:57:40 +00:00
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2022-05-17 18:08:50 +00:00
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using Mode = InstructionSet::M68k::AddressingMode;
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2022-05-16 15:59:03 +00:00
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// Otherwise continue for all time, until back in debt.
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// Formatting is slightly obtuse here to make this look more like a coroutine.
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2022-05-16 20:57:40 +00:00
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while(true) { switch(state_) {
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// Spin in place, one cycle at a time, until one of DTACK,
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// BERR or VPA is asserted.
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2022-05-18 19:35:38 +00:00
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BeginState(WaitForDTACK):
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2022-05-16 20:57:40 +00:00
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PerformBusOperation(awaiting_dtack);
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if(dtack_ || berr_ || vpa_) {
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state_ = post_dtack_state_;
|
2022-05-18 19:35:38 +00:00
|
|
|
continue;
|
2022-05-16 20:57:40 +00:00
|
|
|
}
|
2022-05-18 19:35:38 +00:00
|
|
|
MoveToState(WaitForDTACK);
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
// Perform the RESET exception, which seeds the stack pointer and program
|
|
|
|
// counter, populates the prefetch queue, and then moves to instruction dispatch.
|
2022-05-18 19:35:38 +00:00
|
|
|
BeginState(Reset):
|
2022-05-16 20:57:40 +00:00
|
|
|
IdleBus(7); // (n-)*5 nn
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
// Establish general reset state.
|
|
|
|
status_.is_supervisor = true;
|
|
|
|
status_.interrupt_level = 7;
|
|
|
|
status_.trace_flag = 0;
|
|
|
|
did_update_status();
|
|
|
|
|
2022-05-19 16:18:47 +00:00
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
|
2022-05-20 16:40:35 +00:00
|
|
|
SetDataAddress(temporary_address_.l);
|
2022-05-19 14:27:51 +00:00
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
temporary_address_.l = 0;
|
2022-05-19 14:27:51 +00:00
|
|
|
Access(registers_[15].high); // nF
|
2022-05-17 20:10:20 +00:00
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
temporary_address_.l += 2;
|
2022-05-19 14:27:51 +00:00
|
|
|
Access(registers_[15].low); // nf
|
2022-05-17 20:10:20 +00:00
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
temporary_address_.l += 2;
|
2022-05-19 14:27:51 +00:00
|
|
|
Access(program_counter_.high); // nV
|
2022-05-17 20:10:20 +00:00
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
temporary_address_.l += 2;
|
2022-05-19 14:27:51 +00:00
|
|
|
Access(program_counter_.low); // nv
|
2022-05-16 20:57:40 +00:00
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
2022-05-18 19:35:38 +00:00
|
|
|
MoveToState(Decode);
|
2022-05-16 15:59:03 +00:00
|
|
|
|
2022-05-19 20:27:39 +00:00
|
|
|
// Perform a 'standard' exception, i.e. a Group 1 or 2.
|
|
|
|
BeginState(StandardException):
|
|
|
|
captured_status_.w = status_.status();
|
|
|
|
|
|
|
|
// Switch to supervisor mode.
|
|
|
|
status_.is_supervisor = true;
|
|
|
|
status_.trace_flag = 0;
|
|
|
|
did_update_status();
|
|
|
|
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
SetDataAddress(registers_[15].l);
|
|
|
|
|
|
|
|
// Push status and current program counter.
|
|
|
|
// Write order is wacky here, but I think it's correct.
|
|
|
|
registers_[15].l -= 6;
|
|
|
|
Access(captured_status_); // ns
|
|
|
|
|
|
|
|
registers_[15].l += 4;
|
|
|
|
Access(instruction_address_.low); // ns
|
|
|
|
|
|
|
|
registers_[15].l -= 2;
|
|
|
|
Access(instruction_address_.high); // nS
|
|
|
|
|
|
|
|
registers_[15].l -= 2;
|
|
|
|
|
|
|
|
// Grab new program counter.
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
|
2022-05-20 16:40:35 +00:00
|
|
|
SetDataAddress(temporary_address_.l);
|
2022-05-19 20:27:39 +00:00
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
temporary_address_.l = exception_vector_ << 2;
|
2022-05-19 20:27:39 +00:00
|
|
|
Access(program_counter_.high); // nV
|
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
temporary_address_.l += 2;
|
2022-05-19 20:27:39 +00:00
|
|
|
Access(program_counter_.low); // nv
|
|
|
|
|
|
|
|
// Populate the prefetch queue.
|
|
|
|
Prefetch(); // np
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-17 12:26:35 +00:00
|
|
|
// Inspect the prefetch queue in order to decode the next instruction,
|
|
|
|
// and segue into the fetching of operands.
|
2022-05-18 19:35:38 +00:00
|
|
|
BeginState(Decode):
|
2022-05-18 20:45:40 +00:00
|
|
|
CheckOverrun();
|
|
|
|
|
2022-05-17 12:26:35 +00:00
|
|
|
opcode_ = prefetch_.high.w;
|
|
|
|
instruction_ = decoder_.decode(opcode_);
|
2022-05-19 20:27:39 +00:00
|
|
|
instruction_address_.l = program_counter_.l - 4;
|
2022-05-17 18:08:50 +00:00
|
|
|
|
2022-05-19 22:50:43 +00:00
|
|
|
// Signal the bus handler if requested.
|
|
|
|
if constexpr (signal_will_perform) {
|
|
|
|
bus_handler_.will_perform(instruction_address_.l, opcode_);
|
|
|
|
}
|
|
|
|
|
2022-05-19 20:55:16 +00:00
|
|
|
// Check for a privilege violation.
|
|
|
|
if(instruction_.requires_supervisor() && !status_.is_supervisor) {
|
|
|
|
exception_vector_ = InstructionSet::M68k::Exception::PrivilegeViolation;
|
|
|
|
MoveToState(StandardException);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check for an unrecognised opcode.
|
|
|
|
if(instruction_.operation == InstructionSet::M68k::Operation::Undefined) {
|
|
|
|
switch(opcode_ & 0xf000) {
|
|
|
|
default:
|
|
|
|
exception_vector_ = InstructionSet::M68k::Exception::IllegalInstruction;
|
|
|
|
continue;
|
|
|
|
case 0xa000:
|
|
|
|
exception_vector_ = InstructionSet::M68k::Exception::Line1010;
|
|
|
|
continue;
|
|
|
|
case 0xf000:
|
|
|
|
exception_vector_ = InstructionSet::M68k::Exception::Line1111;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
MoveToState(StandardException);
|
|
|
|
}
|
2022-05-17 12:26:35 +00:00
|
|
|
|
2022-05-17 19:05:11 +00:00
|
|
|
// Ensure the first parameter is next fetched.
|
2022-05-17 18:08:50 +00:00
|
|
|
next_operand_ = 0;
|
2022-05-18 20:45:40 +00:00
|
|
|
|
|
|
|
// Obtain operand flags and pick a perform pattern.
|
2022-05-19 19:03:22 +00:00
|
|
|
#define CASE(x) \
|
2022-05-19 16:18:47 +00:00
|
|
|
case InstructionSet::M68k::Operation::x: \
|
2022-05-19 19:03:22 +00:00
|
|
|
operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>();
|
|
|
|
|
|
|
|
#define StdCASE(x, y) \
|
|
|
|
CASE(x) \
|
2022-05-19 16:18:47 +00:00
|
|
|
y; \
|
|
|
|
\
|
|
|
|
if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::LongWord) { \
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); \
|
|
|
|
MoveToState(FetchOperand_l); \
|
2022-05-19 14:27:51 +00:00
|
|
|
} else { \
|
2022-05-19 16:18:47 +00:00
|
|
|
if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::Byte) { \
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectByte); \
|
|
|
|
} else { \
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); \
|
|
|
|
} \
|
|
|
|
MoveToState(FetchOperand_bw); \
|
|
|
|
}
|
2022-05-19 14:27:51 +00:00
|
|
|
|
2022-05-19 19:49:42 +00:00
|
|
|
#define Duplicate(x, y) \
|
|
|
|
case InstructionSet::M68k::Operation::x: \
|
|
|
|
static_assert( \
|
|
|
|
InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>() == \
|
|
|
|
InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::y>() && \
|
|
|
|
InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == \
|
|
|
|
InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::y>() \
|
2022-05-20 11:02:02 +00:00
|
|
|
); \
|
|
|
|
[[fallthrough]];
|
2022-05-19 19:49:42 +00:00
|
|
|
|
2022-05-18 20:45:40 +00:00
|
|
|
switch(instruction_.operation) {
|
2022-05-19 19:03:22 +00:00
|
|
|
StdCASE(NBCD, {
|
2022-05-18 20:45:40 +00:00
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
} else {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
}
|
2022-05-19 16:18:47 +00:00
|
|
|
})
|
|
|
|
|
2022-05-19 20:30:08 +00:00
|
|
|
Duplicate(CLRb, NEGXb) Duplicate(NEGb, NEGXb) Duplicate(NOTb, NEGXb)
|
2022-05-19 20:27:39 +00:00
|
|
|
StdCASE(NEGXb, perform_state_ = Perform_np);
|
|
|
|
|
2022-05-19 20:30:08 +00:00
|
|
|
Duplicate(CLRw, NEGXw) Duplicate(NEGw, NEGXw) Duplicate(NOTw, NEGXw)
|
2022-05-19 20:27:39 +00:00
|
|
|
StdCASE(NEGXw, perform_state_ = Perform_np);
|
|
|
|
|
2022-05-19 20:30:08 +00:00
|
|
|
Duplicate(CLRl, NEGXl) Duplicate(NEGl, NEGXl) Duplicate(NOTl, NEGXl)
|
2022-05-19 20:27:39 +00:00
|
|
|
StdCASE(NEGXl,
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
} else {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
}
|
|
|
|
);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
StdCASE(SWAP, perform_state_ = Perform_np);
|
2022-05-19 19:19:00 +00:00
|
|
|
StdCASE(EXG, perform_state_ = Perform_np_n);
|
2022-05-19 19:03:22 +00:00
|
|
|
|
2022-05-19 19:41:02 +00:00
|
|
|
StdCASE(EXTbtow, perform_state_ = Perform_np);
|
|
|
|
StdCASE(EXTwtol, perform_state_ = Perform_np);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
StdCASE(MOVEw, perform_state_ = MOVEw);
|
2022-05-19 16:18:47 +00:00
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
StdCASE(CMPb, perform_state_ = Perform_np);
|
|
|
|
StdCASE(CMPw, perform_state_ = Perform_np);
|
|
|
|
StdCASE(CMPl, perform_state_ = Perform_np_n);
|
2022-05-19 16:18:47 +00:00
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
StdCASE(CMPAw, perform_state_ = Perform_np_n);
|
|
|
|
StdCASE(CMPAl, perform_state_ = Perform_np_n);
|
2022-05-19 16:18:47 +00:00
|
|
|
|
2022-05-19 19:49:42 +00:00
|
|
|
Duplicate(ANDb, ORb) StdCASE(ORb, perform_state_ = Perform_np);
|
|
|
|
Duplicate(ANDw, ORw) StdCASE(ORw, perform_state_ = Perform_np);
|
|
|
|
Duplicate(ANDl, ORl) StdCASE(ORl, {
|
2022-05-19 16:18:47 +00:00
|
|
|
if(instruction_.mode(1) == Mode::DataRegisterDirect) {
|
|
|
|
switch(instruction_.mode(0)) {
|
|
|
|
default:
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
break;
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
perform_state_ = Perform_np_nn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
}
|
|
|
|
});
|
2022-05-18 20:45:40 +00:00
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
StdCASE(EORb, perform_state_ = Perform_np);
|
|
|
|
StdCASE(EORw, perform_state_ = Perform_np);
|
|
|
|
StdCASE(EORl, {
|
2022-05-19 16:18:47 +00:00
|
|
|
if(instruction_.mode(1) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np_nn;
|
|
|
|
} else {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
}
|
|
|
|
})
|
2022-05-19 01:00:10 +00:00
|
|
|
|
2022-05-19 19:49:42 +00:00
|
|
|
Duplicate(SBCD, ABCD)
|
2022-05-19 19:19:00 +00:00
|
|
|
CASE(ABCD)
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
|
|
|
|
MoveToState(FetchOperand_bw);
|
|
|
|
} else {
|
2022-05-20 11:02:02 +00:00
|
|
|
select_flag_ = Microcycle::SelectByte;
|
|
|
|
MoveToState(TwoOp_Predec_bw);
|
2022-05-19 19:19:00 +00:00
|
|
|
}
|
|
|
|
|
2022-05-19 20:27:39 +00:00
|
|
|
StdCASE(CHK, perform_state_ = CHK);
|
|
|
|
|
2022-05-20 11:02:02 +00:00
|
|
|
Duplicate(SUBb, ADDb) StdCASE(ADDb, perform_state_ = Perform_np)
|
|
|
|
Duplicate(SUBw, ADDw) StdCASE(ADDw, perform_state_ = Perform_np)
|
|
|
|
Duplicate(SUBl, ADDl) StdCASE(ADDl, {
|
|
|
|
if(instruction_.mode(1) != Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
} else {
|
|
|
|
switch(instruction_.mode(0)) {
|
|
|
|
default:
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
break;
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::AddressRegisterDirect:
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
perform_state_ = Perform_np_nn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
})
|
|
|
|
|
|
|
|
Duplicate(SUBAw, ADDAw) StdCASE(ADDAw, perform_state_ = Perform_np_nn)
|
|
|
|
Duplicate(SUBAl, ADDAl) StdCASE(ADDAl, {
|
|
|
|
if(instruction_.mode(1) == Mode::AddressRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np_nn;
|
|
|
|
} else {
|
|
|
|
switch(instruction_.mode(0)) {
|
|
|
|
default:
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
break;
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::AddressRegisterDirect:
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
perform_state_ = Perform_np_nn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
})
|
|
|
|
|
|
|
|
Duplicate(SUBXb, ADDXb) StdCASE(ADDXb, {
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
} else {
|
|
|
|
select_flag_ = Microcycle::SelectByte;
|
|
|
|
MoveToState(TwoOp_Predec_bw);
|
|
|
|
}
|
|
|
|
})
|
|
|
|
Duplicate(SUBXw, ADDXw) StdCASE(ADDXw, {
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
} else {
|
|
|
|
select_flag_ = Microcycle::SelectWord;
|
|
|
|
MoveToState(TwoOp_Predec_bw);
|
|
|
|
}
|
|
|
|
})
|
|
|
|
Duplicate(SUBXl, ADDXl) StdCASE(ADDXl, {
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Perform_np_nn;
|
|
|
|
} else {
|
|
|
|
MoveToState(TwoOp_Predec_l);
|
|
|
|
}
|
|
|
|
})
|
|
|
|
|
2022-05-20 15:19:16 +00:00
|
|
|
StdCASE(Scc, {
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
perform_state_ = Scc_Dn;
|
|
|
|
} else {
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2022-05-20 15:32:06 +00:00
|
|
|
StdCASE(DBcc, perform_state_ = DBcc);
|
|
|
|
|
2022-05-20 16:04:43 +00:00
|
|
|
StdCASE(Bccb, perform_state_ = Bcc);
|
|
|
|
StdCASE(Bccw, perform_state_ = Bcc);
|
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
StdCASE(BSRb, perform_state_ = BSR);
|
|
|
|
StdCASE(BSRw, perform_state_ = BSR);
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
StdCASE(JSR, {
|
|
|
|
switch(instruction_.mode(0)) {
|
|
|
|
case Mode::AddressRegisterIndirect:
|
|
|
|
MoveToState(JSRAddressRegisterIndirect);
|
|
|
|
case Mode::AddressRegisterIndirectWithDisplacement:
|
|
|
|
MoveToState(JSRAddressRegisterIndirectWithDisplacement);
|
|
|
|
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
|
|
|
|
MoveToState(JSRAddressRegisterIndirectWithIndex8bitDisplacement);
|
|
|
|
case Mode::ProgramCounterIndirectWithDisplacement:
|
|
|
|
MoveToState(JSRProgramCounterIndirectWithDisplacement);
|
|
|
|
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
|
|
|
MoveToState(JSRProgramCounterIndirectWithIndex8bitDisplacement);
|
|
|
|
case Mode::AbsoluteShort:
|
|
|
|
MoveToState(JSRAbsoluteShort);
|
|
|
|
case Mode::AbsoluteLong:
|
|
|
|
MoveToState(JSRAbsoluteLong);
|
|
|
|
|
|
|
|
default: assert(false);
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2022-05-20 16:58:45 +00:00
|
|
|
StdCASE(BTST, {
|
|
|
|
switch(instruction_.mode(1)) {
|
|
|
|
default:
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
break;
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
perform_state_ = Perform_np_n;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
|
|
|
Duplicate(BCHG, BSET)
|
|
|
|
StdCASE(BSET, {
|
|
|
|
switch(instruction_.mode(1)) {
|
|
|
|
default:
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
break;
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
perform_state_ = BCHG_BSET_Dn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
|
|
|
StdCASE(BCLR, {
|
|
|
|
switch(instruction_.mode(1)) {
|
|
|
|
default:
|
|
|
|
perform_state_ = Perform_np;
|
|
|
|
break;
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
perform_state_ = BCLR_Dn;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2022-05-20 18:22:32 +00:00
|
|
|
StdCASE(MOVEPl, {
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
MoveToState(MOVEPtoM_l);
|
|
|
|
} else {
|
|
|
|
MoveToState(MOVEPtoR_l);
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
|
|
|
StdCASE(MOVEPw, {
|
|
|
|
if(instruction_.mode(0) == Mode::DataRegisterDirect) {
|
|
|
|
MoveToState(MOVEPtoM_w);
|
|
|
|
} else {
|
|
|
|
MoveToState(MOVEPtoR_w);
|
|
|
|
}
|
|
|
|
});
|
|
|
|
|
2022-05-20 18:29:14 +00:00
|
|
|
Duplicate(ORItoCCR, EORItoCCR); Duplicate(ANDItoCCR, EORItoCCR);
|
|
|
|
StdCASE(EORItoCCR, perform_state_ = LogicalToSR);
|
|
|
|
|
|
|
|
Duplicate(ORItoSR, EORItoSR); Duplicate(ANDItoSR, EORItoSR);
|
|
|
|
StdCASE(EORItoSR, perform_state_ = LogicalToSR);
|
|
|
|
|
2022-05-20 22:48:19 +00:00
|
|
|
StdCASE(MOVEMtoRl, perform_state_ = MOVEMtoR);
|
|
|
|
StdCASE(MOVEMtoRw, perform_state_ = MOVEMtoR);
|
|
|
|
StdCASE(MOVEMtoMl, perform_state_ = MOVEMtoM);
|
|
|
|
StdCASE(MOVEMtoMw, perform_state_ = MOVEMtoM);
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
StdCASE(TSTb, perform_state_ = Perform_np);
|
|
|
|
StdCASE(TSTw, perform_state_ = Perform_np);
|
|
|
|
StdCASE(TSTl, perform_state_ = Perform_np);
|
|
|
|
|
2022-05-18 20:45:40 +00:00
|
|
|
default:
|
|
|
|
assert(false);
|
|
|
|
}
|
|
|
|
|
2022-05-19 19:49:42 +00:00
|
|
|
#undef Duplicate
|
|
|
|
#undef StdCASE
|
2022-05-18 20:45:40 +00:00
|
|
|
#undef CASE
|
2022-05-17 12:26:35 +00:00
|
|
|
|
2022-05-19 14:47:57 +00:00
|
|
|
// MARK: - Fetch, dispatch.
|
|
|
|
|
2022-05-19 14:27:51 +00:00
|
|
|
#define MoveToNextOperand(x) \
|
2022-05-18 20:45:40 +00:00
|
|
|
++next_operand_; \
|
|
|
|
if(next_operand_ == 2) { \
|
|
|
|
state_ = perform_state_; \
|
|
|
|
continue; \
|
|
|
|
} \
|
2022-05-19 14:27:51 +00:00
|
|
|
MoveToState(x)
|
2022-05-18 20:45:40 +00:00
|
|
|
|
2022-05-19 14:47:57 +00:00
|
|
|
// Check the operand flags to determine whether the byte or word
|
|
|
|
// operand at index next_operand_ needs to be fetched, and if so
|
|
|
|
// then calculate the EA and do so.
|
|
|
|
BeginState(FetchOperand_bw):
|
2022-05-18 20:45:40 +00:00
|
|
|
// Check that this operand is meant to be fetched; if not then either:
|
|
|
|
//
|
|
|
|
// (i) this operand isn't used; or
|
|
|
|
// (ii) its address calculation will end up conflated with performance,
|
|
|
|
// so there's no generic bus-accurate approach.
|
2022-05-17 20:57:33 +00:00
|
|
|
if(!(operand_flags_ & (1 << next_operand_))) {
|
|
|
|
state_ = perform_state_;
|
2022-05-17 18:08:50 +00:00
|
|
|
continue;
|
2022-05-17 20:57:33 +00:00
|
|
|
}
|
2022-05-17 18:08:50 +00:00
|
|
|
|
2022-05-17 20:57:33 +00:00
|
|
|
// Figure out how to fetch it.
|
|
|
|
switch(instruction_.mode(next_operand_)) {
|
2022-05-17 18:08:50 +00:00
|
|
|
case Mode::AddressRegisterDirect:
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
|
|
|
|
case Mode::Quick:
|
|
|
|
operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
|
|
|
|
case Mode::AddressRegisterIndirect:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAddressRegisterIndirect_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::AddressRegisterIndirectWithPostincrement:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAddressRegisterIndirectWithPostincrement_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::AddressRegisterIndirectWithPredecrement:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAddressRegisterIndirectWithPredecrement_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::AddressRegisterIndirectWithDisplacement:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAddressRegisterIndirectWithDisplacement_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::ProgramCounterIndirectWithDisplacement:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchProgramCounterIndirectWithDisplacement_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::AbsoluteShort:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAbsoluteShort_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::AbsoluteLong:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchAbsoluteLong_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
case Mode::ImmediateData:
|
2022-05-19 14:47:57 +00:00
|
|
|
MoveToState(FetchImmediateData_bw);
|
2022-05-18 20:45:40 +00:00
|
|
|
|
|
|
|
// Should be impossible to reach.
|
2022-05-17 18:08:50 +00:00
|
|
|
default:
|
|
|
|
assert(false);
|
|
|
|
}
|
2022-05-17 18:51:49 +00:00
|
|
|
break;
|
|
|
|
|
2022-05-19 14:47:57 +00:00
|
|
|
// As above, but for .l.
|
|
|
|
BeginState(FetchOperand_l):
|
|
|
|
if(!(operand_flags_ & (1 << next_operand_))) {
|
|
|
|
state_ = perform_state_;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(instruction_.mode(next_operand_)) {
|
|
|
|
case Mode::AddressRegisterDirect:
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
|
2022-05-19 23:38:42 +00:00
|
|
|
MoveToNextOperand(FetchOperand_l);
|
2022-05-19 14:47:57 +00:00
|
|
|
|
|
|
|
case Mode::Quick:
|
|
|
|
operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
|
2022-05-19 23:38:42 +00:00
|
|
|
MoveToNextOperand(FetchOperand_l);
|
2022-05-19 14:47:57 +00:00
|
|
|
|
|
|
|
case Mode::AddressRegisterIndirect:
|
|
|
|
MoveToState(FetchAddressRegisterIndirect_l);
|
|
|
|
case Mode::AddressRegisterIndirectWithPostincrement:
|
|
|
|
MoveToState(FetchAddressRegisterIndirectWithPostincrement_l);
|
|
|
|
case Mode::AddressRegisterIndirectWithPredecrement:
|
|
|
|
MoveToState(FetchAddressRegisterIndirectWithPredecrement_l);
|
|
|
|
case Mode::AddressRegisterIndirectWithDisplacement:
|
|
|
|
MoveToState(FetchAddressRegisterIndirectWithDisplacement_l);
|
|
|
|
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
|
|
|
|
MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
|
|
|
|
case Mode::ProgramCounterIndirectWithDisplacement:
|
|
|
|
MoveToState(FetchProgramCounterIndirectWithDisplacement_l);
|
|
|
|
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
|
|
|
MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
|
|
|
|
case Mode::AbsoluteShort:
|
|
|
|
MoveToState(FetchAbsoluteShort_l);
|
|
|
|
case Mode::AbsoluteLong:
|
|
|
|
MoveToState(FetchAbsoluteLong_l);
|
|
|
|
case Mode::ImmediateData:
|
|
|
|
MoveToState(FetchImmediateData_l);
|
|
|
|
|
|
|
|
// Should be impossible to reach.
|
|
|
|
default:
|
|
|
|
assert(false);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcEffectiveAddress):
|
|
|
|
switch(instruction_.mode(next_operand_)) {
|
|
|
|
default:
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case Mode::AddressRegisterIndirect:
|
|
|
|
MoveToState(CalcAddressRegisterIndirect);
|
|
|
|
case Mode::AddressRegisterIndirectWithPostincrement:
|
|
|
|
MoveToState(CalcAddressRegisterIndirectWithPostincrement);
|
|
|
|
case Mode::AddressRegisterIndirectWithPredecrement:
|
|
|
|
MoveToState(CalcAddressRegisterIndirectWithPredecrement);
|
|
|
|
case Mode::AddressRegisterIndirectWithDisplacement:
|
|
|
|
MoveToState(CalcAddressRegisterIndirectWithDisplacement);
|
|
|
|
case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
|
|
|
|
MoveToState(CalcAddressRegisterIndirectWithIndex8bitDisplacement);
|
|
|
|
case Mode::ProgramCounterIndirectWithDisplacement:
|
|
|
|
MoveToState(CalcProgramCounterIndirectWithDisplacement);
|
|
|
|
case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
|
|
|
|
MoveToState(CalcProgramCounterIndirectWithIndex8bitDisplacement);
|
|
|
|
case Mode::AbsoluteShort:
|
|
|
|
MoveToState(CalcAbsoluteShort);
|
|
|
|
case Mode::AbsoluteLong:
|
|
|
|
MoveToState(CalcAbsoluteLong);
|
|
|
|
}
|
|
|
|
|
2022-05-19 14:47:57 +00:00
|
|
|
// MARK: - Fetch, addressing modes.
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// AddressRegisterIndirect
|
|
|
|
//
|
2022-05-19 14:47:57 +00:00
|
|
|
BeginState(FetchAddressRegisterIndirect_bw):
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
2022-05-19 16:18:47 +00:00
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
2022-05-19 14:47:57 +00:00
|
|
|
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAddressRegisterIndirect_l):
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
2022-05-19 16:18:47 +00:00
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
2022-05-19 14:47:57 +00:00
|
|
|
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
|
2022-05-19 15:23:26 +00:00
|
|
|
effective_address_[next_operand_] += 2;
|
2022-05-19 14:47:57 +00:00
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAddressRegisterIndirect):
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRAddressRegisterIndirect):
|
|
|
|
effective_address_[0] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// AddressRegisterIndirectWithPostincrement
|
|
|
|
//
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithPostincrement_bw):
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l +=
|
2022-05-20 20:23:52 +00:00
|
|
|
address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
|
2022-05-19 19:03:22 +00:00
|
|
|
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithPostincrement_l):
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l += 4;
|
|
|
|
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAddressRegisterIndirectWithPostincrement):
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l +=
|
|
|
|
address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// AddressRegisterIndirectWithPredecrement
|
|
|
|
//
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithPredecrement_bw):
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l -=
|
2022-05-20 20:23:52 +00:00
|
|
|
address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
|
2022-05-19 19:03:22 +00:00
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
IdleBus(1); // n
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithPredecrement_l):
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l -= 4;
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
IdleBus(1); // n
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAddressRegisterIndirectWithPredecrement):
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
|
|
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// AddressRegisterIndirectWithDisplacement
|
|
|
|
//
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithDisplacement_bw):
|
|
|
|
effective_address_[next_operand_] =
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l +
|
|
|
|
int16_t(prefetch_.w);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithDisplacement_l):
|
|
|
|
effective_address_[next_operand_] =
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l +
|
|
|
|
int16_t(prefetch_.w);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAddressRegisterIndirectWithDisplacement):
|
|
|
|
effective_address_[next_operand_] =
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l +
|
|
|
|
int16_t(prefetch_.w);
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRAddressRegisterIndirectWithDisplacement):
|
|
|
|
effective_address_[0] =
|
|
|
|
registers_[8 + instruction_.reg(next_operand_)].l +
|
|
|
|
int16_t(prefetch_.w);
|
|
|
|
IdleBus(1); // n
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// ProgramCounterIndirectWithDisplacement
|
|
|
|
//
|
|
|
|
BeginState(FetchProgramCounterIndirectWithDisplacement_bw):
|
|
|
|
effective_address_[next_operand_] =
|
2022-05-20 18:42:51 +00:00
|
|
|
program_counter_.l - 2 +
|
2022-05-19 19:03:22 +00:00
|
|
|
int16_t(prefetch_.w);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchProgramCounterIndirectWithDisplacement_l):
|
|
|
|
effective_address_[next_operand_] =
|
2022-05-20 18:42:51 +00:00
|
|
|
program_counter_.l - 2 +
|
2022-05-19 19:03:22 +00:00
|
|
|
int16_t(prefetch_.w);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcProgramCounterIndirectWithDisplacement):
|
|
|
|
effective_address_[next_operand_] =
|
|
|
|
program_counter_.l - 2 +
|
|
|
|
int16_t(prefetch_.w);
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRProgramCounterIndirectWithDisplacement):
|
|
|
|
effective_address_[0] =
|
|
|
|
program_counter_.l - 2 +
|
|
|
|
int16_t(prefetch_.w);
|
|
|
|
IdleBus(1); // n
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
//
|
|
|
|
// AddressRegisterIndirectWithIndex8bitDisplacement
|
|
|
|
//
|
2022-05-19 19:03:22 +00:00
|
|
|
#define d8Xn(base) \
|
|
|
|
base + \
|
|
|
|
((prefetch_.w & 0x800) ? \
|
|
|
|
registers_[prefetch_.w >> 12].l : \
|
|
|
|
int16_t(registers_[prefetch_.w >> 12].w)) + \
|
|
|
|
int8_t(prefetch_.b);
|
|
|
|
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw):
|
|
|
|
effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l):
|
|
|
|
effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement):
|
|
|
|
effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
|
|
|
|
IdleBus(1); // n
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRAddressRegisterIndirectWithIndex8bitDisplacement):
|
|
|
|
effective_address_[0] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
|
|
|
|
IdleBus(3); // n nn
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// ProgramCounterIndirectWithIndex8bitDisplacement
|
|
|
|
//
|
|
|
|
BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw):
|
2022-05-20 18:42:51 +00:00
|
|
|
effective_address_[next_operand_] = d8Xn(program_counter_.l - 2);
|
2022-05-19 19:03:22 +00:00
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l):
|
2022-05-20 20:23:52 +00:00
|
|
|
effective_address_[next_operand_] = d8Xn(program_counter_.l - 2);
|
2022-05-19 19:03:22 +00:00
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement):
|
|
|
|
effective_address_[next_operand_] = d8Xn(program_counter_.l - 2);
|
|
|
|
IdleBus(1); // n
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRProgramCounterIndirectWithIndex8bitDisplacement):
|
|
|
|
effective_address_[0] = d8Xn(program_counter_.l - 2);
|
|
|
|
IdleBus(3); // n nn
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
#undef d8Xn
|
|
|
|
|
|
|
|
//
|
|
|
|
// AbsoluteShort
|
|
|
|
//
|
|
|
|
BeginState(FetchAbsoluteShort_bw):
|
|
|
|
effective_address_[next_operand_] = int16_t(prefetch_.w);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAbsoluteShort_l):
|
|
|
|
effective_address_[next_operand_] = int16_t(prefetch_.w);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAbsoluteShort):
|
|
|
|
effective_address_[next_operand_] = int16_t(prefetch_.w);
|
|
|
|
Prefetch(); // np
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRAbsoluteShort):
|
|
|
|
effective_address_[0] = int16_t(prefetch_.w);
|
|
|
|
IdleBus(1); // n
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// AbsoluteLong
|
|
|
|
//
|
|
|
|
BeginState(FetchAbsoluteLong_bw):
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
effective_address_[next_operand_] = prefetch_.l;
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchAbsoluteLong_l):
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
effective_address_[next_operand_] = prefetch_.l;
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Access(operand_[next_operand_].high); // nR
|
|
|
|
effective_address_[next_operand_] += 2;
|
|
|
|
Access(operand_[next_operand_].low); // nr
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-20 20:23:52 +00:00
|
|
|
BeginState(CalcAbsoluteLong):
|
|
|
|
Prefetch(); // np
|
|
|
|
effective_address_[next_operand_] = prefetch_.l;
|
|
|
|
Prefetch(); // np
|
|
|
|
state_ = post_ea_state_;
|
|
|
|
break;
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
BeginState(JSRAbsoluteLong):
|
|
|
|
Prefetch(); // np
|
|
|
|
effective_address_[0] = prefetch_.l;
|
|
|
|
MoveToState(JSR_push);
|
|
|
|
|
2022-05-19 19:03:22 +00:00
|
|
|
//
|
|
|
|
// ImmediateData
|
|
|
|
//
|
|
|
|
BeginState(FetchImmediateData_bw):
|
|
|
|
operand_[next_operand_].w = prefetch_.w;
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
|
|
|
|
BeginState(FetchImmediateData_l):
|
|
|
|
Prefetch(); // np
|
|
|
|
operand_[next_operand_].l = prefetch_.l;
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
|
2022-05-19 20:55:16 +00:00
|
|
|
#undef MoveToNextOperand
|
|
|
|
|
2022-05-19 14:47:57 +00:00
|
|
|
// MARK: - Store.
|
|
|
|
|
2022-05-19 20:55:16 +00:00
|
|
|
#define MoveToNextOperand(x) \
|
|
|
|
++next_operand_; \
|
|
|
|
if(next_operand_ == 2) { \
|
|
|
|
MoveToState(Decode); \
|
|
|
|
} \
|
|
|
|
MoveToState(x)
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
// Store operand is a lot simpler: only one operand is ever stored, and its address
|
|
|
|
// is already known. So this can either skip straight back to ::Decode if the target
|
|
|
|
// is a register, otherwise a single write operation can occur.
|
2022-05-18 19:35:38 +00:00
|
|
|
BeginState(StoreOperand):
|
2022-05-19 20:55:16 +00:00
|
|
|
switch(instruction_.operand_size()) {
|
|
|
|
case InstructionSet::M68k::DataSize::LongWord:
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
MoveToState(StoreOperand_l);
|
|
|
|
|
|
|
|
case InstructionSet::M68k::DataSize::Word:
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
MoveToState(StoreOperand_bw);
|
|
|
|
|
|
|
|
case InstructionSet::M68k::DataSize::Byte:
|
|
|
|
SetupDataAccess(0, Microcycle::SelectByte);
|
|
|
|
MoveToState(StoreOperand_bw);
|
2022-05-17 20:10:20 +00:00
|
|
|
}
|
|
|
|
|
2022-05-19 20:55:16 +00:00
|
|
|
BeginState(StoreOperand_bw):
|
|
|
|
if(!(operand_flags_ & 0x4 << next_operand_)) {
|
|
|
|
MoveToNextOperand(StoreOperand_bw);
|
|
|
|
}
|
|
|
|
|
|
|
|
if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) {
|
|
|
|
registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
|
|
|
|
MoveToNextOperand(StoreOperand_bw);
|
2022-05-19 15:23:26 +00:00
|
|
|
}
|
|
|
|
|
2022-05-19 16:18:47 +00:00
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
2022-05-19 15:23:26 +00:00
|
|
|
Access(operand_[next_operand_].low); // nw
|
2022-05-19 20:55:16 +00:00
|
|
|
MoveToNextOperand(StoreOperand_bw);
|
2022-05-19 15:23:26 +00:00
|
|
|
|
|
|
|
BeginState(StoreOperand_l):
|
2022-05-19 20:55:16 +00:00
|
|
|
if(!(operand_flags_ & 0x4 << next_operand_)) {
|
|
|
|
MoveToNextOperand(StoreOperand_l);
|
|
|
|
}
|
|
|
|
|
|
|
|
if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) {
|
|
|
|
registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
|
|
|
|
MoveToNextOperand(StoreOperand_l);
|
|
|
|
}
|
|
|
|
|
2022-05-19 16:18:47 +00:00
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
2022-05-19 15:23:26 +00:00
|
|
|
Access(operand_[next_operand_].low); // nw
|
|
|
|
|
|
|
|
effective_address_[next_operand_] -= 2;
|
|
|
|
Access(operand_[next_operand_].high); // nW
|
2022-05-19 20:55:16 +00:00
|
|
|
MoveToNextOperand(StoreOperand_l);
|
2022-05-17 20:10:20 +00:00
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
//
|
2022-05-19 01:00:10 +00:00
|
|
|
// Various generic forms of perform.
|
2022-05-17 18:51:49 +00:00
|
|
|
//
|
2022-05-17 20:10:20 +00:00
|
|
|
#define MoveToWritePhase() \
|
2022-05-19 20:55:16 +00:00
|
|
|
next_operand_ = 0; \
|
2022-05-18 19:35:38 +00:00
|
|
|
if(operand_flags_ & 0x0c) MoveToState(StoreOperand) else MoveToState(Decode)
|
2022-05-17 20:10:20 +00:00
|
|
|
|
2022-05-18 19:35:38 +00:00
|
|
|
BeginState(Perform_np):
|
2022-05-17 18:51:49 +00:00
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
Prefetch(); // np
|
2022-05-18 19:35:38 +00:00
|
|
|
MoveToWritePhase();
|
2022-05-17 18:51:49 +00:00
|
|
|
|
2022-05-18 19:35:38 +00:00
|
|
|
BeginState(Perform_np_n):
|
2022-05-17 18:51:49 +00:00
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
Prefetch(); // np
|
|
|
|
IdleBus(1); // n
|
2022-05-18 19:35:38 +00:00
|
|
|
MoveToWritePhase();
|
2022-05-17 18:51:49 +00:00
|
|
|
|
2022-05-19 16:18:47 +00:00
|
|
|
BeginState(Perform_np_nn):
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
Prefetch(); // np
|
|
|
|
IdleBus(2); // nn
|
|
|
|
MoveToWritePhase();
|
|
|
|
|
2022-05-17 20:10:20 +00:00
|
|
|
#undef MoveToWritePhase
|
2022-05-17 12:26:35 +00:00
|
|
|
|
2022-05-18 19:35:38 +00:00
|
|
|
|
2022-05-19 01:00:10 +00:00
|
|
|
//
|
2022-05-20 16:04:43 +00:00
|
|
|
// Specific forms of perform...
|
2022-05-19 01:00:10 +00:00
|
|
|
//
|
|
|
|
|
|
|
|
BeginState(MOVEw):
|
|
|
|
switch(instruction_.mode(1)) {
|
|
|
|
case Mode::DataRegisterDirect:
|
|
|
|
case Mode::AddressRegisterDirect:
|
|
|
|
MoveToState(MOVEwRegisterDirect);
|
|
|
|
|
|
|
|
case Mode::AddressRegisterIndirectWithPostincrement:
|
|
|
|
MoveToState(MOVEwAddressRegisterIndirectWithPostincrement);
|
|
|
|
|
|
|
|
default: assert(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
BeginState(MOVEwRegisterDirect):
|
|
|
|
registers_[instruction_.lreg(1)].w = operand_[1].w;
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(MOVEwAddressRegisterIndirectWithPostincrement):
|
|
|
|
// TODO: nw
|
|
|
|
assert(false);
|
|
|
|
Prefetch() // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 16:04:43 +00:00
|
|
|
//
|
|
|
|
// [ABCD/SBCD/SUBX/ADDX] (An)-, (An)-
|
|
|
|
//
|
2022-05-20 11:02:02 +00:00
|
|
|
BeginState(TwoOp_Predec_bw):
|
2022-05-19 19:19:00 +00:00
|
|
|
IdleBus(1); // n
|
|
|
|
|
2022-05-20 11:02:02 +00:00
|
|
|
SetupDataAccess(Microcycle::Read, select_flag_);
|
|
|
|
|
2022-05-19 19:19:00 +00:00
|
|
|
SetDataAddress(registers_[8 + instruction_.reg(0)].l);
|
2022-05-20 20:23:52 +00:00
|
|
|
registers_[8 + instruction_.reg(0)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(0)];
|
2022-05-19 19:19:00 +00:00
|
|
|
Access(operand_[0].low); // nr
|
|
|
|
|
|
|
|
SetDataAddress(registers_[8 + instruction_.reg(1)].l);
|
2022-05-20 20:23:52 +00:00
|
|
|
registers_[8 + instruction_.reg(1)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(1)];
|
2022-05-19 19:19:00 +00:00
|
|
|
Access(operand_[1].low); // nr
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
2022-05-20 11:02:02 +00:00
|
|
|
SetupDataAccess(0, select_flag_);
|
2022-05-19 19:19:00 +00:00
|
|
|
Access(operand_[1].low); // nw
|
2022-05-20 11:02:02 +00:00
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(TwoOp_Predec_l):
|
|
|
|
IdleBus(1); // n
|
|
|
|
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
|
|
|
|
|
|
|
|
SetDataAddress(registers_[8 + instruction_.reg(0)].l);
|
|
|
|
registers_[8 + instruction_.reg(0)].l -= 2;
|
|
|
|
Access(operand_[0].low); // nr
|
|
|
|
|
|
|
|
registers_[8 + instruction_.reg(0)].l -= 2;
|
|
|
|
Access(operand_[0].high); // nR
|
|
|
|
|
|
|
|
SetDataAddress(registers_[8 + instruction_.reg(1)].l);
|
|
|
|
registers_[8 + instruction_.reg(1)].l -= 2;
|
|
|
|
Access(operand_[1].low); // nr
|
|
|
|
|
|
|
|
registers_[8 + instruction_.reg(1)].l -= 2;
|
|
|
|
Access(operand_[1].high); // nR
|
|
|
|
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
|
|
|
|
registers_[8 + instruction_.reg(1)].l += 2;
|
|
|
|
Access(operand_[1].low); // nw
|
|
|
|
|
|
|
|
Prefetch(); // np
|
2022-05-19 19:19:00 +00:00
|
|
|
|
2022-05-20 11:02:02 +00:00
|
|
|
registers_[8 + instruction_.reg(1)].l -= 2;
|
|
|
|
Access(operand_[1].high); // nW
|
2022-05-19 19:19:00 +00:00
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 15:19:16 +00:00
|
|
|
//
|
|
|
|
// CHK
|
|
|
|
//
|
2022-05-19 20:27:39 +00:00
|
|
|
BeginState(CHK):
|
|
|
|
Prefetch(); // np
|
|
|
|
InstructionSet::M68k::perform<
|
|
|
|
InstructionSet::M68k::Model::M68000,
|
|
|
|
ProcessorBase,
|
|
|
|
InstructionSet::M68k::Operation::CHK
|
|
|
|
>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
// Proper next state will have been set by the flow controller
|
|
|
|
// call-in; just allow dispatch to whatever it was.
|
|
|
|
break;
|
|
|
|
|
|
|
|
BeginState(CHK_no_trap):
|
|
|
|
IdleBus(3); // nn n
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(CHK_was_over):
|
|
|
|
IdleBus(2); // nn
|
|
|
|
instruction_address_.l = program_counter_.l - 4;
|
|
|
|
exception_vector_ = InstructionSet::M68k::Exception::CHK;
|
|
|
|
MoveToState(StandardException);
|
|
|
|
|
|
|
|
BeginState(CHK_was_under):
|
|
|
|
IdleBus(3); // n nn
|
|
|
|
instruction_address_.l = program_counter_.l - 4;
|
|
|
|
exception_vector_ = InstructionSet::M68k::Exception::CHK;
|
|
|
|
MoveToState(StandardException);
|
|
|
|
|
2022-05-20 15:19:16 +00:00
|
|
|
//
|
|
|
|
// Scc
|
|
|
|
//
|
|
|
|
BeginState(Scc_Dn):
|
|
|
|
Prefetch(); // np
|
|
|
|
InstructionSet::M68k::perform<
|
|
|
|
InstructionSet::M68k::Model::M68000,
|
|
|
|
ProcessorBase,
|
|
|
|
InstructionSet::M68k::Operation::Scc
|
|
|
|
>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
// Next state will be set by did_scc.
|
|
|
|
break;
|
|
|
|
|
|
|
|
BeginState(Scc_Dn_did_set):
|
|
|
|
IdleBus(1); // n
|
|
|
|
[[fallthrough]];
|
|
|
|
BeginState(Scc_Dn_did_not_set):
|
|
|
|
next_operand_ = 0;
|
|
|
|
MoveToState(StoreOperand);
|
|
|
|
|
2022-05-20 15:32:06 +00:00
|
|
|
//
|
|
|
|
// DBcc
|
|
|
|
//
|
|
|
|
BeginState(DBcc):
|
|
|
|
InstructionSet::M68k::perform<
|
|
|
|
InstructionSet::M68k::Model::M68000,
|
|
|
|
ProcessorBase,
|
|
|
|
InstructionSet::M68k::Operation::DBcc
|
|
|
|
>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
2022-05-20 15:37:18 +00:00
|
|
|
|
|
|
|
// Just do the write-back here.
|
|
|
|
registers_[instruction_.reg(0)].w = operand_[0].w;
|
|
|
|
|
2022-05-20 16:04:43 +00:00
|
|
|
// Next state was set by complete_dbcc.
|
2022-05-20 15:32:06 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
BeginState(DBcc_branch_taken):
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(DBcc_condition_true):
|
|
|
|
IdleBus(2); // n n
|
|
|
|
Prefetch(); // np
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(DBcc_counter_overflow):
|
|
|
|
IdleBus(1); // n
|
|
|
|
|
|
|
|
// Yacht lists an extra np here; I'm assuming it's a read from where
|
|
|
|
// the PC would have gone, had the branch been taken. So do that,
|
|
|
|
// but then reset the PC to where it would have been.
|
|
|
|
Prefetch();
|
|
|
|
|
|
|
|
program_counter_.l = instruction_address_.l + 4;
|
|
|
|
Prefetch(); // np
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 16:04:43 +00:00
|
|
|
//
|
|
|
|
// Bcc [.b and .w]
|
|
|
|
//
|
|
|
|
BeginState(Bcc):
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
// Next state was set by complete_bcc.
|
|
|
|
break;
|
|
|
|
|
|
|
|
BeginState(Bcc_branch_taken):
|
|
|
|
IdleBus(1); // n
|
|
|
|
Prefetch(); // np
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(Bcc_b_branch_not_taken):
|
|
|
|
IdleBus(2); // nn
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(Bcc_w_branch_not_taken):
|
|
|
|
IdleBus(2); // nn
|
|
|
|
Prefetch(); // np
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 16:40:35 +00:00
|
|
|
//
|
|
|
|
// BSR
|
|
|
|
//
|
|
|
|
BeginState(BSR):
|
|
|
|
IdleBus(1); // n
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
// Calculate the address of the next instruction.
|
2022-05-20 16:40:35 +00:00
|
|
|
if(instruction_.operand_size() == InstructionSet::M68k::DataSize::Word) {
|
|
|
|
temporary_address_.l = instruction_address_.l + 4;
|
|
|
|
} else {
|
|
|
|
temporary_address_.l = instruction_address_.l + 2;
|
|
|
|
}
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
// Push it to the stack.
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
SetDataAddress(registers_[15].l);
|
2022-05-20 16:40:35 +00:00
|
|
|
registers_[15].l -= 4;
|
|
|
|
Access(temporary_address_.high); // nS
|
|
|
|
registers_[15].l += 2;
|
2022-05-21 14:29:36 +00:00
|
|
|
Access(temporary_address_.low); // ns
|
2022-05-20 16:40:35 +00:00
|
|
|
registers_[15].l -= 2;
|
|
|
|
|
|
|
|
// Get the new PC.
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-21 14:29:36 +00:00
|
|
|
//
|
|
|
|
// JSR [push only; address calculation elsewhere]
|
|
|
|
//
|
|
|
|
BeginState(JSR_push):
|
|
|
|
// Grab the address of the next instruction.
|
|
|
|
temporary_address_.l = program_counter_.l - 4;
|
|
|
|
|
|
|
|
// Update the program counter and prefetch once.
|
|
|
|
program_counter_.l = effective_address_[0];
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
// Push the old PC onto the stack in upper, lower order.
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
|
|
SetDataAddress(registers_[15].l);
|
|
|
|
registers_[15].l -= 4;
|
|
|
|
Access(temporary_address_.high); // nS
|
|
|
|
registers_[15].l += 2;
|
|
|
|
Access(temporary_address_.low); // ns
|
|
|
|
registers_[15].l -= 2;
|
|
|
|
|
|
|
|
// Prefetch once more.
|
|
|
|
Prefetch();
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 16:58:45 +00:00
|
|
|
//
|
|
|
|
// BSET, BCHG, BCLR
|
|
|
|
//
|
|
|
|
BeginState(BCHG_BSET_Dn):
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
IdleBus(1 + did_bit_op_high_);
|
|
|
|
registers_[instruction_.reg(1)] = operand_[1];
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(BCLR_Dn):
|
|
|
|
InstructionSet::M68k::perform<
|
|
|
|
InstructionSet::M68k::Model::M68000,
|
|
|
|
ProcessorBase,
|
|
|
|
InstructionSet::M68k::Operation::BCLR
|
|
|
|
>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
IdleBus(2 + did_bit_op_high_);
|
|
|
|
registers_[instruction_.reg(1)] = operand_[1];
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 18:22:32 +00:00
|
|
|
//
|
|
|
|
// MOVEP
|
|
|
|
//
|
|
|
|
BeginState(MOVEPtoM_l):
|
|
|
|
temporary_address_.l = registers_[8 + instruction_.reg(1)].l + uint32_t(int16_t(prefetch_.w));
|
|
|
|
SetDataAddress(temporary_address_.l);
|
|
|
|
SetupDataAccess(0, Microcycle::SelectByte);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 24);
|
|
|
|
Access(temporary_value_.low); // nW
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 16);
|
|
|
|
Access(temporary_value_.low); // nW
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 8);
|
|
|
|
Access(temporary_value_.low); // nw
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l);
|
|
|
|
Access(temporary_value_.low); // nw
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(MOVEPtoM_w):
|
|
|
|
temporary_address_.l = registers_[8 + instruction_.reg(1)].l + uint32_t(int16_t(prefetch_.w));
|
|
|
|
SetDataAddress(temporary_address_.l);
|
|
|
|
SetupDataAccess(0, Microcycle::SelectByte);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 8);
|
|
|
|
Access(temporary_value_.low); // nW
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l);
|
|
|
|
Access(temporary_value_.low); // nw
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(MOVEPtoR_l):
|
|
|
|
temporary_address_.l = registers_[8 + instruction_.reg(0)].l + uint32_t(int16_t(prefetch_.w));
|
|
|
|
SetDataAddress(temporary_address_.l);
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
Access(temporary_value_.low); // nR
|
|
|
|
registers_[instruction_.reg(1)].l = temporary_value_.b << 24;
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
Access(temporary_value_.low); // nR
|
|
|
|
registers_[instruction_.reg(1)].w |= temporary_value_.b << 16;
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
Access(temporary_value_.low); // nr
|
|
|
|
registers_[instruction_.reg(1)].w |= temporary_value_.b << 8;
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
Access(temporary_value_.low); // nr
|
|
|
|
registers_[instruction_.reg(1)].w |= temporary_value_.b;
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
BeginState(MOVEPtoR_w):
|
|
|
|
temporary_address_.l = registers_[8 + instruction_.reg(0)].l + uint32_t(int16_t(prefetch_.w));
|
|
|
|
SetDataAddress(temporary_address_.l);
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
|
|
|
|
Access(temporary_value_.low); // nR
|
|
|
|
registers_[instruction_.reg(1)].w = temporary_value_.b << 8;
|
|
|
|
|
|
|
|
temporary_address_.l += 2;
|
|
|
|
Access(temporary_value_.low); // nr
|
|
|
|
registers_[instruction_.reg(1)].w |= temporary_value_.b;
|
|
|
|
|
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 18:29:14 +00:00
|
|
|
//
|
|
|
|
// [EORI/ORI/ANDI] #, [CCR/SR]
|
|
|
|
//
|
|
|
|
BeginState(LogicalToSR):
|
|
|
|
// Perform the operation.
|
|
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
|
|
|
|
|
|
// Recede the program counter and prefetch twice.
|
|
|
|
program_counter_.l -= 2;
|
|
|
|
Prefetch();
|
|
|
|
Prefetch();
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 22:48:19 +00:00
|
|
|
//
|
|
|
|
// MOVEM M --> R
|
|
|
|
//
|
|
|
|
BeginState(MOVEMtoR):
|
|
|
|
post_ea_state_ =
|
|
|
|
(instruction_.operation == InstructionSet::M68k::Operation::MOVEMtoRl) ?
|
|
|
|
MOVEMtoR_l_read : MOVEMtoR_w_read;
|
|
|
|
next_operand_ = 1;
|
|
|
|
register_index_ = 0;
|
|
|
|
|
|
|
|
SetDataAddress(effective_address_[1]);
|
|
|
|
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
|
|
|
|
MoveToState(CalcEffectiveAddress);
|
|
|
|
|
|
|
|
BeginState(MOVEMtoR_w_read):
|
|
|
|
// If there's nothing left to read, move on.
|
|
|
|
if(!operand_[0].w) {
|
|
|
|
MoveToState(MOVEMtoR_finish);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find the next register to read, read it and sign extend it.
|
|
|
|
while(!(operand_[0].w & 1)) {
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 00:47:54 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
}
|
|
|
|
Access(registers_[register_index_].low);
|
|
|
|
registers_[register_index_].l = uint32_t(int16_t(registers_[register_index_].w));
|
|
|
|
effective_address_[1] += 2;
|
|
|
|
|
|
|
|
// Drop the bottom bit.
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 00:47:54 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
MoveToState(MOVEMtoR_w_read);
|
|
|
|
|
|
|
|
BeginState(MOVEMtoR_l_read):
|
|
|
|
// If there's nothing left to read, move on.
|
|
|
|
if(!operand_[0].w) {
|
|
|
|
MoveToState(MOVEMtoR_finish);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find the next register to read, read it.
|
|
|
|
while(!(operand_[0].w & 1)) {
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 00:47:54 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
}
|
|
|
|
Access(registers_[register_index_].high);
|
|
|
|
effective_address_[1] += 2;
|
2022-05-21 00:47:54 +00:00
|
|
|
Access(registers_[register_index_].low);
|
|
|
|
effective_address_[1] += 2;
|
2022-05-20 22:48:19 +00:00
|
|
|
|
|
|
|
// Drop the bottom bit.
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 00:47:54 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
MoveToState(MOVEMtoR_l_read);
|
|
|
|
|
|
|
|
BeginState(MOVEMtoR_finish):
|
|
|
|
// Perform one more read, spuriously.
|
|
|
|
Access(temporary_value_.low); // nr
|
|
|
|
|
2022-05-21 01:01:23 +00:00
|
|
|
// Write the address back to the register if
|
2022-05-21 12:17:39 +00:00
|
|
|
// this was postincrement mode.
|
2022-05-21 01:01:23 +00:00
|
|
|
if(instruction_.mode(1) == Mode::AddressRegisterIndirectWithPostincrement) {
|
|
|
|
registers_[8 + instruction_.reg(1)].l = effective_address_[1];
|
|
|
|
}
|
|
|
|
|
2022-05-20 22:48:19 +00:00
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
|
|
|
//
|
|
|
|
// MOVEM R --> M
|
|
|
|
//
|
|
|
|
BeginState(MOVEMtoM):
|
|
|
|
next_operand_ = 1;
|
2022-05-21 12:17:39 +00:00
|
|
|
SetDataAddress(effective_address_[1]);
|
|
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
2022-05-20 22:48:19 +00:00
|
|
|
|
|
|
|
// Predecrement writes registers the other way around, but still reads the
|
|
|
|
// mask from LSB.
|
|
|
|
if(instruction_.mode(1) == Mode::AddressRegisterIndirectWithPredecrement) {
|
|
|
|
register_index_ = 15;
|
2022-05-21 12:17:39 +00:00
|
|
|
effective_address_[1] = registers_[8 + instruction_.reg(1)].l;
|
|
|
|
|
|
|
|
// Don't go through the usual calculate EA path because: (i) the test above
|
|
|
|
// has already told us the addressing mode, and it's trivial; and (ii) the
|
|
|
|
// predecrement isn't actually wanted.
|
|
|
|
if(instruction_.operation == InstructionSet::M68k::Operation::MOVEMtoMl) {
|
|
|
|
MoveToState(MOVEMtoM_l_write_predec);
|
|
|
|
} else {
|
|
|
|
MoveToState(MOVEMtoM_w_write_predec);
|
|
|
|
}
|
2022-05-20 22:48:19 +00:00
|
|
|
}
|
|
|
|
|
2022-05-21 12:17:39 +00:00
|
|
|
register_index_ = 0;
|
|
|
|
post_ea_state_ =
|
|
|
|
(instruction_.operation == InstructionSet::M68k::Operation::MOVEMtoMl) ?
|
|
|
|
MOVEMtoM_l_write : MOVEMtoM_w_write;
|
2022-05-20 22:48:19 +00:00
|
|
|
MoveToState(CalcEffectiveAddress);
|
|
|
|
|
|
|
|
BeginState(MOVEMtoM_w_write):
|
|
|
|
// If there's nothing left to read, move on.
|
|
|
|
if(!operand_[0].w) {
|
|
|
|
MoveToState(MOVEMtoM_finish);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find the next register to write, write it.
|
|
|
|
while(!(operand_[0].w & 1)) {
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 12:17:39 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
}
|
|
|
|
Access(registers_[register_index_].low);
|
2022-05-21 12:17:39 +00:00
|
|
|
effective_address_[1] += 2;
|
2022-05-20 22:48:19 +00:00
|
|
|
|
|
|
|
// Drop the bottom bit.
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 12:17:39 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
MoveToState(MOVEMtoM_w_write);
|
|
|
|
|
|
|
|
BeginState(MOVEMtoM_l_write):
|
|
|
|
// If there's nothing left to read, move on.
|
|
|
|
if(!operand_[0].w) {
|
|
|
|
MoveToState(MOVEMtoM_finish);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find the next register to write, write it.
|
|
|
|
while(!(operand_[0].w & 1)) {
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 12:17:39 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
Access(registers_[register_index_].high);
|
2022-05-21 12:17:39 +00:00
|
|
|
effective_address_[1] += 2;
|
2022-05-20 22:48:19 +00:00
|
|
|
Access(registers_[register_index_].low);
|
2022-05-21 12:17:39 +00:00
|
|
|
effective_address_[1] += 2;
|
2022-05-20 22:48:19 +00:00
|
|
|
|
|
|
|
// Drop the bottom bit.
|
|
|
|
operand_[0].w >>= 1;
|
2022-05-21 12:17:39 +00:00
|
|
|
++register_index_;
|
2022-05-20 22:48:19 +00:00
|
|
|
MoveToState(MOVEMtoM_l_write);
|
|
|
|
|
2022-05-21 12:17:39 +00:00
|
|
|
BeginState(MOVEMtoM_w_write_predec):
|
|
|
|
// If there's nothing left to read, move on.
|
|
|
|
if(!operand_[0].w) {
|
|
|
|
MoveToState(MOVEMtoM_finish);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find the next register to write, write it.
|
|
|
|
while(!(operand_[0].w & 1)) {
|
|
|
|
operand_[0].w >>= 1;
|
|
|
|
--register_index_;
|
|
|
|
}
|
|
|
|
effective_address_[1] -= 2;
|
|
|
|
Access(registers_[register_index_].low);
|
|
|
|
|
|
|
|
// Drop the bottom bit.
|
|
|
|
operand_[0].w >>= 1;
|
|
|
|
--register_index_;
|
|
|
|
MoveToState(MOVEMtoM_w_write_predec);
|
|
|
|
|
|
|
|
BeginState(MOVEMtoM_l_write_predec):
|
|
|
|
// If there's nothing left to read, move on.
|
|
|
|
if(!operand_[0].w) {
|
|
|
|
MoveToState(MOVEMtoM_finish);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Find the next register to write, write it.
|
|
|
|
while(!(operand_[0].w & 1)) {
|
|
|
|
operand_[0].w >>= 1;
|
|
|
|
--register_index_;
|
|
|
|
}
|
|
|
|
|
|
|
|
effective_address_[1] -= 2;
|
|
|
|
Access(registers_[register_index_].low);
|
|
|
|
effective_address_[1] -= 2;
|
|
|
|
Access(registers_[register_index_].high);
|
|
|
|
|
|
|
|
// Drop the bottom bit.
|
|
|
|
operand_[0].w >>= 1;
|
|
|
|
--register_index_;
|
|
|
|
MoveToState(MOVEMtoM_l_write_predec);
|
|
|
|
|
2022-05-20 22:48:19 +00:00
|
|
|
BeginState(MOVEMtoM_finish):
|
2022-05-21 12:17:39 +00:00
|
|
|
// Write the address back to the register if
|
|
|
|
// this was predecrement mode.
|
|
|
|
if(instruction_.mode(1) == Mode::AddressRegisterIndirectWithPredecrement) {
|
|
|
|
registers_[8 + instruction_.reg(1)].l = effective_address_[1];
|
|
|
|
}
|
|
|
|
|
2022-05-20 22:48:19 +00:00
|
|
|
Prefetch(); // np
|
|
|
|
MoveToState(Decode);
|
|
|
|
|
2022-05-20 15:19:16 +00:00
|
|
|
//
|
2022-05-18 19:35:38 +00:00
|
|
|
// Various states TODO.
|
2022-05-20 15:19:16 +00:00
|
|
|
//
|
2022-05-18 20:45:40 +00:00
|
|
|
#define TODOState(x) \
|
|
|
|
BeginState(x): [[fallthrough]];
|
|
|
|
|
2022-05-19 20:27:39 +00:00
|
|
|
TODOState(BusOrAddressErrorException);
|
2022-05-18 20:45:40 +00:00
|
|
|
|
|
|
|
#undef TODOState
|
2022-05-18 19:35:38 +00:00
|
|
|
|
2022-05-17 01:00:25 +00:00
|
|
|
default:
|
2022-05-19 14:47:57 +00:00
|
|
|
printf("Unhandled state: %d; opcode is %04x\n", state_, opcode_);
|
2022-05-17 01:00:25 +00:00
|
|
|
assert(false);
|
2022-05-16 15:59:03 +00:00
|
|
|
}}
|
|
|
|
|
2022-05-17 01:02:25 +00:00
|
|
|
#undef Prefetch
|
|
|
|
#undef ReadProgramWord
|
|
|
|
#undef ReadDataWord
|
|
|
|
#undef AccessPair
|
|
|
|
#undef CompleteAccess
|
|
|
|
#undef WaitForDTACK
|
|
|
|
#undef IdleBus
|
|
|
|
#undef PerformBusOperation
|
|
|
|
#undef MoveToState
|
2022-05-16 15:59:03 +00:00
|
|
|
#undef CheckOverrun
|
|
|
|
#undef Spend
|
|
|
|
#undef ConsiderExit
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
// MARK: - Flow Controller.
|
|
|
|
|
|
|
|
void ProcessorBase::did_update_status() {
|
|
|
|
// Shuffle the stack pointers.
|
2022-05-17 20:51:26 +00:00
|
|
|
stack_pointers_[is_supervisor_] = registers_[15];
|
|
|
|
registers_[15] = stack_pointers_[int(status_.is_supervisor)];
|
2022-05-17 18:51:49 +00:00
|
|
|
is_supervisor_ = int(status_.is_supervisor);
|
|
|
|
}
|
|
|
|
|
2022-05-19 20:27:39 +00:00
|
|
|
void ProcessorBase::did_chk(bool was_under, bool was_over) {
|
|
|
|
if(was_over) {
|
|
|
|
state_ = CHK_was_over;
|
|
|
|
} else if(was_under) {
|
|
|
|
state_ = CHK_was_under;
|
|
|
|
} else {
|
|
|
|
state_ = CHK_no_trap;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-05-20 15:19:16 +00:00
|
|
|
void ProcessorBase::did_scc(bool did_set_ff) {
|
|
|
|
state_ = did_set_ff ? Scc_Dn_did_set : Scc_Dn_did_not_set;
|
|
|
|
}
|
|
|
|
|
2022-05-20 15:32:06 +00:00
|
|
|
void ProcessorBase::complete_dbcc(bool matched_condition, bool overflowed, int16_t offset) {
|
|
|
|
// The actual DBcc rule is: branch if !matched_condition and !overflowed; but I think
|
|
|
|
// that a spurious read from the intended destination PC occurs if overflowed, so update
|
|
|
|
// the PC for any case of !matched_condition and rely on the DBcc_counter_overflow to
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// set it back.
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if(!matched_condition) {
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state_ = overflowed ? DBcc_counter_overflow : DBcc_branch_taken;
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program_counter_.l = instruction_address_.l + uint32_t(offset) + 2;
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return;
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}
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state_ = DBcc_condition_true;
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}
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2022-05-20 16:04:43 +00:00
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template <typename IntT> void ProcessorBase::complete_bcc(bool take_branch, IntT offset) {
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if(take_branch) {
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program_counter_.l = instruction_address_.l + uint32_t(offset) + 2;
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state_ = Bcc_branch_taken;
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return;
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}
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state_ =
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(instruction_.operation == InstructionSet::M68k::Operation::Bccb) ?
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Bcc_b_branch_not_taken : Bcc_w_branch_not_taken;
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}
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2022-05-20 16:40:35 +00:00
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void ProcessorBase::bsr(uint32_t offset) {
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program_counter_.l = instruction_address_.l + offset + 2;
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}
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2022-05-20 16:58:45 +00:00
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void ProcessorBase::did_bit_op(int bit_position) {
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did_bit_op_high_ = bit_position > 15;
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}
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2022-05-17 18:51:49 +00:00
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|
// MARK: - External state.
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2022-05-17 00:04:13 +00:00
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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CPU::MC68000Mk2::State Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::get_state() {
|
2022-05-17 20:51:26 +00:00
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CPU::MC68000Mk2::State state;
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|
|
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|
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|
// This isn't true, but will ensure that both stack_pointers_ have their proper values.
|
|
|
|
did_update_status();
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|
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|
|
|
|
for(int c = 0; c < 7; c++) {
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|
state.registers.data[c] = registers_[c].l;
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|
|
state.registers.address[c] = registers_[c + 8].l;
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|
}
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|
|
state.registers.data[7] = registers_[7].l;
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|
|
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|
|
state.registers.program_counter = program_counter_.l;
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|
|
state.registers.status = status_.status();
|
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|
|
state.registers.user_stack_pointer = stack_pointers_[0].l;
|
|
|
|
state.registers.supervisor_stack_pointer = stack_pointers_[1].l;
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|
|
|
|
|
|
|
return state;
|
2022-05-17 00:04:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
2022-05-17 20:51:26 +00:00
|
|
|
void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::set_state(const CPU::MC68000Mk2::State &state) {
|
|
|
|
// Copy registers and the program counter.
|
|
|
|
for(int c = 0; c < 7; c++) {
|
|
|
|
registers_[c].l = state.registers.data[c];
|
|
|
|
registers_[c + 8].l = state.registers.address[c];
|
|
|
|
}
|
|
|
|
registers_[7].l = state.registers.data[7];
|
|
|
|
program_counter_.l = state.registers.program_counter;
|
|
|
|
|
|
|
|
// Set status first in order to get the proper is-supervisor flag in place.
|
|
|
|
status_.set_status(state.registers.status);
|
|
|
|
|
|
|
|
// Update stack pointers, being careful to copy the right one.
|
|
|
|
stack_pointers_[0].l = state.registers.user_stack_pointer;
|
|
|
|
stack_pointers_[1].l = state.registers.supervisor_stack_pointer;
|
|
|
|
registers_[15] = stack_pointers_[is_supervisor_];
|
|
|
|
|
|
|
|
// Ensure the local is-supervisor flag is updated.
|
|
|
|
did_update_status();
|
2022-05-17 00:04:13 +00:00
|
|
|
}
|
|
|
|
|
2022-05-17 18:51:49 +00:00
|
|
|
|
2022-05-16 15:44:16 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* _8000Mk2Implementation_h */
|