Thomas Harte
|
2cadc706e2
|
Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started.
|
2017-05-25 21:00:33 -04:00 |
|
Thomas Harte
|
3c6f63abcc
|
Started towards running the FUSE tests. Just need to deal with the memory segments.
|
2017-05-25 19:12:59 -04:00 |
|
Thomas Harte
|
00cd7e7e9c
|
After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.
|
2017-05-25 18:20:13 -04:00 |
|
Thomas Harte
|
055c860b43
|
Sealed off RegisterState as immutable, and started trying to parse the .expected file.
|
2017-05-23 22:32:36 -04:00 |
|
Thomas Harte
|
454c8628c3
|
Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable.
|
2017-05-23 22:05:33 -04:00 |
|
Thomas Harte
|
a23a6db4d6
|
Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine.
|
2017-05-23 08:13:24 -04:00 |
|
Thomas Harte
|
6575091a78
|
Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
|
2017-05-22 21:50:34 -04:00 |
|
Thomas Harte
|
9e25d014d2
|
Made an attempt to log bus activity for comparison with FUSE results.
|
2017-05-22 19:49:38 -04:00 |
|
Thomas Harte
|
41d5dd8679
|
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
|
2017-05-22 19:24:11 -04:00 |
|
Thomas Harte
|
c3ea6dc1f5
|
Added respect for limiting to the requested number of cycles in the Z80.
|
2017-05-22 19:15:55 -04:00 |
|
Thomas Harte
|
22afa509ca
|
Got to a parsing and towards an attempt to run FUSE tests.
|
2017-05-22 19:14:46 -04:00 |
|
Thomas Harte
|
3fb3cc8269
|
Got explicit about encodings.
|
2017-05-21 22:53:06 -04:00 |
|
Thomas Harte
|
e3e461d7cb
|
Added a test class for running the FUSE tests. With nothing much in it.
|
2017-05-21 22:49:24 -04:00 |
|
Thomas Harte
|
c16fccb317
|
Fixed file names.
|
2017-05-21 22:43:07 -04:00 |
|
Thomas Harte
|
b9cffdf2bd
|
Imported the FUSE tests.
|
2017-05-21 22:42:20 -04:00 |
|
Thomas Harte
|
f2aae72cc2
|
Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
|
2017-05-21 20:43:36 -04:00 |
|
Thomas Harte
|
fe8db1873c
|
Added 16-bit ADC and SBC table entries; once again extended logging.
|
2017-05-21 20:32:06 -04:00 |
|
Thomas Harte
|
c66c715ac9
|
Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
|
2017-05-21 19:26:40 -04:00 |
|
Thomas Harte
|
5dcfd85642
|
Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
|
2017-05-21 19:15:52 -04:00 |
|
Thomas Harte
|
c70dfe1b09
|
Implemented the two variations of loading between (nn) and SP.
|
2017-05-21 13:20:28 -04:00 |
|
Thomas Harte
|
232c591655
|
Threw in a little macro documentation and a missing macro.
|
2017-05-21 13:13:21 -04:00 |
|
Thomas Harte
|
790614b544
|
Added EI and DI.
|
2017-05-21 12:53:17 -04:00 |
|
Thomas Harte
|
32c032cd97
|
Implemented a couple of easy-to-add missing base page instructions.
|
2017-05-21 10:18:43 -04:00 |
|
Thomas Harte
|
e48ee16366
|
Continued cleaning efforts, added conditional RET.
|
2017-05-21 10:13:59 -04:00 |
|
Thomas Harte
|
e92d936ce8
|
Added conditional calls.
|
2017-05-21 10:03:46 -04:00 |
|
Thomas Harte
|
4e210c5396
|
Added LD A, (nn).
|
2017-05-21 10:00:10 -04:00 |
|
Thomas Harte
|
3d3e60b1fc
|
Implemented LD (HL), r.
|
2017-05-21 09:56:41 -04:00 |
|
Thomas Harte
|
f3f0e2f1a9
|
Implemented RRA and RRCA.
|
2017-05-21 09:52:19 -04:00 |
|
Thomas Harte
|
08206eea56
|
This logging has outlived its usefulness for now.
|
2017-05-21 09:47:53 -04:00 |
|
Thomas Harte
|
78296246e8
|
Added ALU n.
|
2017-05-21 09:46:18 -04:00 |
|
Thomas Harte
|
85b5dd35b1
|
Took a shot at 8-bit arithmetic.
|
2017-05-21 09:43:17 -04:00 |
|
Thomas Harte
|
11cfaa3e3d
|
Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement.
|
2017-05-21 09:17:30 -04:00 |
|
Thomas Harte
|
103c863534
|
Through temporarily dramatically increased logging, fixed conditional JP.
|
2017-05-20 23:03:52 -04:00 |
|
Thomas Harte
|
6688f83226
|
Took a shot at LDIR.
|
2017-05-20 21:58:24 -04:00 |
|
Thomas Harte
|
01a064dd63
|
Added an empty ED page.
|
2017-05-20 17:29:30 -04:00 |
|
Thomas Harte
|
7b234078ae
|
Implemented EX DE, HL and shuffled to allow instruction pages.
|
2017-05-20 17:04:25 -04:00 |
|
Thomas Harte
|
add02a7897
|
Added LD (nn), A, and reduced double logging to single for now.
|
2017-05-19 23:13:28 -04:00 |
|
Thomas Harte
|
19167df692
|
Consolidated and filled in AND and XOR.
|
2017-05-19 23:03:34 -04:00 |
|
Thomas Harte
|
6766845e21
|
Filled in most of the loads.
|
2017-05-19 22:57:43 -04:00 |
|
Thomas Harte
|
bc3b5f3e35
|
Added 16-bit INCs and DECs. Which don't set flags, so are easy.
|
2017-05-19 22:13:36 -04:00 |
|
Thomas Harte
|
5fe23113ec
|
Moved RET to the correct place, implemented POP AF.
|
2017-05-19 22:03:12 -04:00 |
|
Thomas Harte
|
c55e1c1d17
|
Implemented POP and therefore RET; corrected timing of PUSH.
|
2017-05-19 21:59:45 -04:00 |
|
Thomas Harte
|
d910405648
|
Added enough infrastructure to be able to react to the two CP/M calls this cares about.
|
2017-05-19 21:53:39 -04:00 |
|
Thomas Harte
|
62b432c046
|
Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
|
2017-05-19 21:20:28 -04:00 |
|
Thomas Harte
|
eae1f78221
|
Implemented the main page pushes.
|
2017-05-19 19:28:38 -04:00 |
|
Thomas Harte
|
11d05fb3b8
|
Expanded a little on operations, added an implementation or two.
|
2017-05-19 19:18:35 -04:00 |
|
Thomas Harte
|
58efca835f
|
Sought to add a further opcode.
|
2017-05-18 22:53:43 -04:00 |
|
Thomas Harte
|
da6e520b91
|
Merge branch 'master' into Z80
|
2017-05-18 22:30:51 -04:00 |
|
Thomas Harte
|
a5099f69d8
|
Merge pull request #127 from TomHarte/OricShift
Maps either Mac shift key to both Oric shifts
|
2017-05-18 22:27:47 -04:00 |
|
Thomas Harte
|
9398b6c2c8
|
Unable to differentiate, decided to map a Mac shift key to both Oric shifts.
|
2017-05-18 22:25:59 -04:00 |
|