1060 Commits

Author	SHA1	Message	Date
Thomas Harte	1f9e41e9cb	Ensure TOD isn't firing from power-on.	2021-08-08 18:51:58 -04:00
Thomas Harte	98bd6fc240	Adds a further logging hint.	2021-08-06 23:16:06 -04:00
Thomas Harte	b9f78f5d33	Fix final timer B test.	2021-08-03 22:27:23 -04:00
Thomas Harte	b4ec9d70da	Adds the CNT input.	2021-08-03 22:19:41 -04:00
Thomas Harte	dd91d793d9	Correct typo.	2021-08-03 21:45:44 -04:00
Thomas Harte	8e51e8eb77	Does just a touch of 6526 TOD work.	2021-08-03 21:13:08 -04:00
Thomas Harte	6210605bc7	Transfers full TOD responsibility onto the chip-specific templates.	2021-08-03 19:10:09 -04:00
Thomas Harte	0245b040b0	Splits TOD storage by model. ... TOD storage will probably end up being a full-on class.	2021-08-03 18:50:58 -04:00
Thomas Harte	8795719c18	This counts reloads, most accurately.	2021-08-03 17:12:08 -04:00
Thomas Harte	6bbbf43341	At least attempts to chain correctly.	2021-08-03 17:03:58 -04:00
Thomas Harte	ee6039bfa5	Writes to a timer _during reload_ now have effect. ... Net: one CIA test passed.	2021-08-03 16:57:05 -04:00
Thomas Harte	ef58ce6277	Gets a bit more rigorous about the clocking stage. ... Albeit without advancing relative to the test.	2021-08-02 21:04:00 -04:00
Thomas Harte	15de5e98c4	Adds [partial] test for whether counters are linked.	2021-08-02 20:17:37 -04:00
Thomas Harte	38848ca2db	Rationalises reload logic and cuts storage. ... Failure point is now chaining, I think.	2021-08-02 20:14:01 -04:00
Thomas Harte	77c627e822	Ensure that reading the interrupt flags really clears the master bit. ... Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.	2021-08-02 07:47:08 -04:00
Thomas Harte	c640132699	Reinstates clocking.	2021-08-01 21:35:08 -04:00
Thomas Harte	57dd38aef2	Reintroduces reload-on-off, adds interrupt delay.	2021-08-01 21:09:02 -04:00
Thomas Harte	460a6cb6fe	Attempts a more literal implementation.	2021-08-01 18:14:10 -04:00
Thomas Harte	3d160ce85f	Add another potential warning.	2021-07-30 18:21:38 -04:00
Thomas Harte	759007ffc1	Attempts to route CIA interrupts.	2021-07-28 19:36:30 -04:00
Thomas Harte	37a55c3a77	Corrects 6526 interrupt control write. ... This seems to imply that the 6526 should be interrupting too.	2021-07-28 19:26:02 -04:00
Thomas Harte	bcb7bb5cce	Improves logging further. ... To investigate the new perpetual loop.	2021-07-26 17:02:30 -04:00
Thomas Harte	34d4420e8c	Correct reading of top byte of counter 2.	2021-07-25 20:41:15 -04:00
Thomas Harte	fcd6b7b0ea	Takes further aim at the conters. ... I think test cases are needed, probably.	2021-07-24 16:06:49 -04:00
Thomas Harte	ceca32ceb3	Takes a guess at one-shot mode.	2021-07-24 15:53:18 -04:00
Thomas Harte	77a8ddb95c	Edges towards working counters.	2021-07-23 22:43:47 -04:00
Thomas Harte	c733a4dbf8	Beefs up interrupt awareness.	2021-07-23 21:58:52 -04:00
Thomas Harte	d898a43dff	Implements time-of-day counters, provisionally. ... Interrupts to do.	2021-07-23 21:24:07 -04:00
Thomas Harte	6123349b79	Stubs in control registers and disables exit-on-miss. ... I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.	2021-07-22 19:28:01 -04:00
Thomas Harte	56b62a5e49	Adds a dummy interrupt control register.	2021-07-22 16:09:32 -04:00
Thomas Harte	a030d9935e	Adds port input.	2021-07-18 20:25:04 -04:00
Thomas Harte	c425dec4d5	Makes some attempt to get as far as the overlay being disabled.	2021-07-18 17:17:41 -04:00
Thomas Harte	67d53601d5	Latch and return data direction. ... Albeit with no port-handling effect yet.	2021-07-18 12:23:47 -04:00
Thomas Harte	622cca0acf	Adds sufficient address decoding to print a more helpful exit message.	2021-07-18 12:13:56 -04:00
Thomas Harte	48999c03a5	Adds concept of time, captured port handler.	2021-07-18 11:49:10 -04:00
Thomas Harte	377cc7bdcd	Start to introduce a 6526/8250.	2021-07-18 11:36:13 -04:00
Thomas Harte	a5d0976c2d	Eliminate unused #includes.	2021-07-18 11:35:57 -04:00
Thomas Harte	ae05010255	Improve indentation.	2021-07-18 11:29:26 -04:00
Thomas Harte	66cacbd0e0	Be overt about the type being supplied.	2021-07-18 11:28:18 -04:00
Thomas Harte	c8699d9770	Correct Disk II sleeping test to allow for spin-down.	2021-07-16 17:12:57 -04:00
Thomas Harte	69c0734975	WD1770: switch motor on even if spin-up is disabled.	2021-06-21 23:26:55 -04:00
Thomas Harte	1d5144b912	Correct no-interrupt signal.	2021-06-04 22:38:07 -04:00
Thomas Harte	b7a62e0121	Adds SZX support. ... Tweaking exposed Spectrum state object as relevant.	2021-04-26 20:47:28 -04:00
Thomas Harte	3348167c46	Ensures AY registers are conveyed.	2021-04-26 17:39:11 -04:00
Thomas Harte	73c8157197	Retain 6850 time tracking at all times.	2021-04-20 22:26:43 -04:00
Thomas Harte	af1dc2d3b2	Switches to correct non-value sentinel.	2021-04-20 21:56:58 -04:00
Thomas Harte	1266bbb224	Makes the TMS a sequence-point-generating JustInTimeActor.	2021-04-05 21:02:37 -04:00
Thomas Harte	8a11a5832c	Uses GI::AY38910::Utility far and wide.	2021-03-26 23:19:47 -04:00
Thomas Harte	f37f89a7d3	Merge branch 'master' into ZXSpectrum	2021-03-21 22:44:37 -04:00
Thomas Harte	58be770eaa	Factors out some boilerplate. ... When I'm confident this is correct, I can fix up the other call sites.	2021-03-21 00:14:48 -04:00