8720 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Thomas Harte	5899af0038	Starts accumulating disk data.	2021-10-07 05:11:32 -07:00
Thomas Harte	ed303310bb	Spell out slightly more; this makes debugging a touch easier.	2021-10-06 13:40:48 -07:00
Thomas Harte	33ff4f3b5c	Eliminate drive copies.	2021-10-06 13:40:28 -07:00
Thomas Harte	20bad38d42	Add drive activity lights.	2021-10-06 04:54:40 -07:00
Thomas Harte	92a07398cd	I think CHNG works the other way around.	2021-10-06 04:47:52 -07:00
Thomas Harte	ce8f782577	Corrects meaning of IBM-style RDY.	2021-10-06 04:42:44 -07:00
Thomas Harte	e961d0b4a3	Switch RDY type.	2021-10-06 04:41:09 -07:00
Thomas Harte	2253ff656a	Adds route for inserting disks.	2021-10-05 16:12:30 -07:00
Thomas Harte	18631399ad	Attempts to clock the disk controller.	2021-10-05 15:38:56 -07:00
Thomas Harte	ad4afcdcd5	Switch stepping direction. ... Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.	2021-10-05 15:23:48 -07:00
Thomas Harte	2cf5bcc5db	Clarify logic somewhat.	2021-10-05 15:20:05 -07:00
Thomas Harte	1180ad7662	Disables a couple of now-trustworthy LOGs.	2021-10-05 06:51:47 -07:00
Thomas Harte	5463cd1ae3	Attempts to support stepping and head selection.	2021-10-05 06:36:17 -07:00
Thomas Harte	647ec770ce	Implements motor latching, drive ID shift registers.	2021-10-05 05:12:01 -07:00
Thomas Harte	e47bec2e65	Switch CIA B ports over.	2021-10-05 03:38:11 -07:00
Thomas Harte	6566936be9	Be overt about the intended interface.	2021-10-04 16:45:33 -07:00
Thomas Harte	674941abdf	Starts to add a disk controller.	2021-10-04 16:45:05 -07:00
Thomas Harte	b3f0ca39ed	Adds some unused drives.	2021-10-04 08:12:13 -07:00
Thomas Harte	5ccb512883	Moves the CIAs into the Chipset class. ... This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.	2021-10-04 06:44:54 -07:00
Thomas Harte	da286d5ae8	Switch spaces to tabs.	2021-10-04 05:27:25 -07:00
Thomas Harte	73e45511dc	Add missing #include.	2021-10-04 05:26:38 -07:00
Thomas Harte	a282a51673	Remove last of the direct printf'ing.	2021-09-30 02:42:59 -04:00
Thomas Harte	b7b13e20d1	Single column blits should use both masks.	2021-09-29 22:49:35 -04:00
Thomas Harte	ad90c6b6ce	Now that this is getting close, don't stop at the first error.	2021-09-29 22:19:34 -04:00
Thomas Harte	402fa41bc0	Corrects initial error value.	2021-09-29 22:19:17 -04:00
Thomas Harte	0b9ebafc0f	Flip bit deserialisation order.	2021-09-28 22:12:13 -04:00
Thomas Harte	140e24ef15	Grab further copy flags.	2021-09-28 22:11:58 -04:00
Thomas Harte	0c998d60cb	Correct test logic for line draws that repeatedly write to the same address.	2021-09-28 21:45:55 -04:00
Thomas Harte	ffcd2ea10c	Attempts more properly to implement line mode.	2021-09-28 21:39:09 -04:00
Thomas Harte	cb460de94d	Makes bad first attempt at a Bresenham inner loop.	2021-09-27 22:06:00 -04:00
Thomas Harte	f6624bf776	Edges mildly closer to line output.	2021-09-26 19:18:12 -04:00
Thomas Harte	b4b6c4d86f	Attempts to support left and right masks.	2021-09-26 18:42:08 -04:00
Thomas Harte	759689ff31	Fix line mode flag, add busy status.	2021-09-26 18:16:00 -04:00
Thomas Harte	1dfc36f311	Flip loop, add modulo mappings.	2021-09-26 18:15:32 -04:00
Thomas Harte	1c03ff1d37	Fix bltdptl to bltbptl misstatement; remove pre-DMA writes.	2021-09-26 18:14:50 -04:00
Thomas Harte	19dd2f92bd	Implements test case. Failing at present, naturally.	2021-09-25 21:52:41 -04:00
Thomas Harte	acfaa016a0	Adds a capture of traffic leading up to the Workbench boot logo. ... Around which to construct a test case.	2021-09-25 18:10:07 -04:00
Thomas Harte	732761433a	Merge branch 'master' into HeaderOnly6502	2021-09-23 23:00:11 -04:00
Thomas Harte	9012a7f5e1	Merge branch 'master' into Amiga	2021-09-23 23:00:03 -04:00
Thomas Harte	e957b471b2	Merge pull request #989 from TomHarte/Xcode13 ... Resolves Clang 13 implicit conversion warnings.	2021-09-23 22:59:42 -04:00
Thomas Harte	e5a5faa417	Resolves Clang 13 implicit conversion warnings.	2021-09-23 22:53:41 -04:00
Thomas Harte	313dbe05e0	Switch to more consistent inlining.	2021-09-23 22:36:15 -04:00
Thomas Harte	adf7124e2c	Eliminate 6502Base.cpp.	2021-09-23 22:33:33 -04:00
Thomas Harte	c4ab2bbeed	Hard-code fetch window width. For now.	2021-09-23 22:06:13 -04:00
Thomas Harte	42ef459e20	Resolve resting values.	2021-09-23 22:05:59 -04:00
Thomas Harte	cad1a9e0f1	Correct bit test.	2021-09-23 20:42:31 -04:00
Thomas Harte	f1d514470d	Add note to future self.	2021-09-23 20:29:39 -04:00
Thomas Harte	9a7a54f22f	Take alternative guess as to meaning of 'use' bits.	2021-09-23 18:42:12 -04:00
Thomas Harte	137d1c61bd	Allow for channel enables and blitting direction.	2021-09-23 18:38:37 -04:00
Thomas Harte	adc071ed7a	Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.	2021-09-23 18:30:35 -04:00