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Author	SHA1	Message	Date
Thomas Harte	e11990e453	Make an attempt at DIVS timing.	2022-05-27 15:38:54 -04:00
Thomas Harte	165ebe8ae3	Add time calculation for MULU and MULS.	2022-05-27 15:38:14 -04:00
Thomas Harte	e746637bee	Fill in dynamic cost of shifts.	2022-05-27 15:38:08 -04:00
Thomas Harte	0e6370d467	Tweak per empirical results.	2022-05-27 15:37:40 -04:00
Thomas Harte	512cd333e5	Make an attempt at DIVS timing.	2022-05-27 14:56:04 -04:00
Thomas Harte	f599a78cad	Add time calculation for MULU and MULS.	2022-05-27 14:41:42 -04:00
Thomas Harte	7601dab464	Fill in timing calculation for DIVU.	2022-05-27 14:30:03 -04:00
Thomas Harte	a8623eab4a	Fill in dynamic cost of shifts.	2022-05-27 11:12:10 -04:00
Thomas Harte	c367ddff1b	Merge branch '68000Mk2' into InMacintosh	2022-05-27 10:34:11 -04:00
Thomas Harte	67b340fa5e	Fix interrupt request address.	2022-05-27 10:33:36 -04:00
Thomas Harte	c97245e626	Fix CalcEA timing; make MOVEfromSR a read-modify-write.	2022-05-27 10:32:28 -04:00
Thomas Harte	79e2c17f93	Fix interrupt request address.	2022-05-26 20:20:28 -04:00
Thomas Harte	5937737bb7	Merge branch '68000Mk2' into InMacintosh	2022-05-26 19:37:44 -04:00
Thomas Harte	5f030edea4	Simplify transaction.	2022-05-26 19:37:30 -04:00
Thomas Harte	88e33353a1	Fix instruction and time counting, and initial state.	2022-05-26 09:17:37 -04:00
Thomas Harte	f3c0c62c79	Switch register-setting interface.	2022-05-26 07:52:14 -04:00
Thomas Harte	866787c5d3	Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.	2022-05-25 20:22:38 -04:00
Thomas Harte	367ad8079a	Add a call to set register state with population of the prefetch.	2022-05-25 20:22:05 -04:00
Thomas Harte	64491525b4	Work further to guess at caller's intention for set_state. ... Probably I should just eliminate the initial reset, somehow.	2022-05-25 17:01:18 -04:00
Thomas Harte	68b184885f	Reapply only the status.	2022-05-25 16:54:25 -04:00
Thomas Harte	06f3c716f5	Make better effort to establish initial state.	2022-05-25 16:47:41 -04:00
Thomas Harte	22714b8c7f	Capture state at instruction end, for potential inspection.	2022-05-25 16:32:26 -04:00
Thomas Harte	80c1bedffb	Eliminate false prefetch for BSR.	2022-05-25 16:32:02 -04:00
Thomas Harte	56ad6d24ee	Fix ANDI/ORI/EORI to CCR/SR timing.	2022-05-25 16:20:26 -04:00
Thomas Harte	4ad0e04c23	Fix macro for n being an expression.	2022-05-25 16:05:45 -04:00
Thomas Harte	f9d1c554b7	Fix for the actual number of cycles in a standard reset.	2022-05-25 16:05:28 -04:00
Thomas Harte	ee58301a46	Add RaiseException macro.	2022-05-25 15:45:09 -04:00
Thomas Harte	f2a7660390	Merge branch 'master' into 68000Mk2	2022-05-25 15:40:10 -04:00
Thomas Harte	d4c7ce2d6f	Merge pull request #1035 from TomHarte/68000TestIssues ... Add details on gaps in coverage.	2022-05-25 15:39:42 -04:00
Thomas Harte	4961e39fb6	Mention DIVU/DIVS flags.	2022-05-25 15:39:00 -04:00
Thomas Harte	0bedf608c0	Add details on gaps in coverage.	2022-05-25 15:36:27 -04:00
Thomas Harte	1ab831f571	Add the option to log a list of all untested instructions.	2022-05-25 13:17:01 -04:00
Thomas Harte	b90f1a48ce	Merge branch '68000Mk2' into InMacintosh	2022-05-25 13:02:44 -04:00
Thomas Harte	72425fc2e1	Fix bus data size of MOVE.b xx, -(An).	2022-05-25 13:00:36 -04:00
Thomas Harte	a5f2dfbc0c	Initialise registers to 0 for better testability. ... TODO: is this the real initial state?	2022-05-25 11:47:42 -04:00
Thomas Harte	5db6a937cb	Have TRAP and TRAPV push the next instruction address to the stack.	2022-05-25 11:47:21 -04:00
Thomas Harte	9709b9b1b1	Standard exceptions don't raise the interrupt level.	2022-05-25 11:37:39 -04:00
Thomas Harte	2c6b9b4c9d	Switch comparative trace tests to 68000 Mk2.	2022-05-25 11:32:00 -04:00
Thomas Harte	463fbb07f9	Adapt remaining 68000 tests to use Mk2.	2022-05-25 10:55:17 -04:00
Thomas Harte	b6e473a515	Adapt remaining 68000 tests to use Mk2.	2022-05-25 10:55:03 -04:00
Thomas Harte	24f7b5806c	Merge branch '68000Mk2' into InMacintosh	2022-05-25 08:15:41 -04:00
Thomas Harte	5872e0ea4a	Resolve MOVE.l xx, -(An) write target.	2022-05-25 08:15:18 -04:00
Thomas Harte	04d2d6012a	Merge branch '68000Mk2' into InMacintosh	2022-05-24 16:08:56 -04:00
Thomas Harte	f43d27541b	Avoid attempt to establish operand flags for undefined opcodes.	2022-05-24 15:53:12 -04:00
Thomas Harte	c8d3d980ba	Avoid attempt to establish operand flags for undefined opcodes.	2022-05-24 15:52:53 -04:00
Thomas Harte	f93bf06b99	Merge branch '68000Mk2' into InMacintosh	2022-05-24 15:51:22 -04:00
Thomas Harte	0f7cb2fa5a	Attempt to honour the trace flag.	2022-05-24 15:47:47 -04:00
Thomas Harte	01e93ba916	Make an attempt at bus/address error.	2022-05-24 15:42:50 -04:00
Thomas Harte	780954f27b	Add TRAP, TRAPV.	2022-05-24 15:14:46 -04:00
Thomas Harte	19d69bdbb5	Add TRAP, TRAPV.	2022-05-24 15:14:20 -04:00