Thomas Harte
7163b1132c
Takes a run at CMPI.
...
Also factors out a couple of mode things, clarifies on where things from the
prefetch are assembled to, and switches to ordering implemented instructions
alphabetically.
2019-03-24 23:05:57 -04:00
Thomas Harte
3ccec1c996
Implements MOVE to SR, fleshing out the final bits of storage for the status word.
2019-03-24 18:20:54 -04:00
Thomas Harte
43532c8455
Starts to make incursions into MOVE[A].l.
2019-03-23 21:03:52 -04:00
Thomas Harte
ed7060a105
Made an initial stab at completing MOVEA.w.
...
I think I'm probably peeking into the prefetch queue incorrectly.
2019-03-22 21:43:51 -04:00
Thomas Harte
c9c16968bb
Implements MOVEA as distinct from MOVE.
...
At least as far as MOVE is implemented, that is.
2019-03-22 19:25:53 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
eeb161ec51
Converts the prefetch queue into a 32-bit quantity.
2019-03-19 21:33:52 -04:00
Thomas Harte
21cb7307d0
Adds MOVE #, Dn
and MOVEA An, An
.
...
As well as the scheduling for `(d16,PC), Dd` and `MOVE (d8,As,Xn), Dd` other than the .ls.
2019-03-19 11:53:37 -04:00
Thomas Harte
412a1eb7ee
Takes an initial run at (An)+, -(An), (d16,An) and (d8,An,Xn) addressing modes.
...
With only MOVEs from those to a data register implemented so far.
2019-03-18 22:51:32 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
53b3d9cf9d
Implements a few more MOVE variants, plus MOVEA.
2019-03-17 14:34:16 -04:00
Thomas Harte
937b3ca81d
Attempts properly to honour the bus-op and microcycle contract.
2019-03-16 22:36:09 -04:00
Thomas Harte
d0c5cf0d2d
Starts attempting to kill the need to prepare all bus step sequences in advance.
2019-03-16 21:47:46 -04:00
Thomas Harte
4cbf2bef82
By way of a friend, clears a bunch of transient stuff out of 68000Storage.hpp.
...
As, even if not in the programmer's eye, this does affect recompilation times.
2019-03-16 19:41:07 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
bb04981280
I'm still dithering on address management, but this seeks fully to implement ABCD and SUBD bus programs.
2019-03-13 21:08:13 -04:00
Thomas Harte
57898ed6dd
This is where my thinking now resides. Two levels of indirection, and consolidated collections.
2019-03-12 22:46:31 -04:00
Thomas Harte
33b53e7605
Settles upon disassembly as the route in, and begins work in that direction.
2019-03-11 22:47:58 -04:00
Thomas Harte
98aa597510
A theoretical 68000 could now perform its /RESET. That's all though.
2019-03-10 17:42:13 -04:00
Thomas Harte
de56d48b2f
Embraces a more communicative 68000 bus.
2019-03-10 17:27:34 -04:00
Thomas Harte
b9b52b7c8b
Begins some very early sketching out of a 68000.
2019-03-09 00:00:23 -05:00