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11,632 Commits 8 Branches 121 Tags 496 MiB
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117 Commits

Author SHA1 Message Date
Thomas Harte
fbc273f114 Add invented model for tests. 2024-03-10 21:45:56 -04:00
Thomas Harte
a4cf86268e Provide full access to stored registers. 2024-03-09 15:11:04 -05:00
Thomas Harte
d059e7c5d8 Disallow copying. 2024-03-09 15:10:55 -05:00
Thomas Harte
fdef8901ab Double down on uint32_t. 2024-03-08 14:13:34 -05:00
Thomas Harte
ca1c3dc005 Add extra comments. 
To persuade myself in the future.
 2024-03-08 11:36:17 -05:00
Thomas Harte
fa8fcd2218 Take another swing at popcount. 2024-03-07 14:28:31 -05:00
Thomas Harte
2a36d0fcbc Adjust user-mode test. 2024-03-07 14:00:38 -05:00
Thomas Harte
0e92885ed5 Fix ad hoc popcount; ARM does carry 'backwards'. 2024-03-07 13:27:41 -05:00
Thomas Harte
f5225b69e5 Add note to self. 2024-03-07 11:48:44 -05:00
Thomas Harte
15ee84b2eb Fix MUL ambiguity. 2024-03-07 11:45:39 -05:00
Thomas Harte
a0f0f73bde Fix MOV as unconditional branch. 2024-03-07 10:31:26 -05:00
Thomas Harte
108a056f1c Execution now runs into a prefetch abort loop. 2024-03-06 15:05:24 -05:00
Thomas Harte
fe467be124 Further stick to existing type. 2024-03-05 10:56:09 -05:00
Thomas Harte
ba5f142515 Take further stab at TEQ PC, etc. 2024-03-05 10:55:44 -05:00
Thomas Harte
ed586e80bc Don't write to the PC with logical operations. 2024-03-05 09:32:35 -05:00
Thomas Harte
871c5467d7 Avoid sign change. 2024-03-05 09:31:42 -05:00
Thomas Harte
1b7c3644f4 Eliinate meaningless 'const'. 2024-03-04 14:09:27 -05:00
Thomas Harte
0cdca12e06 Resolve type mismatches. 2024-03-04 13:53:46 -05:00
Thomas Harte
61d4c69e45 Fix template parameter reference. 2024-03-04 13:25:40 -05:00
Thomas Harte
79865e295b Avoid ambiguous template parameter; use standard type. 2024-03-04 12:20:40 -05:00
Thomas Harte
230e9c6327 Obscure active. 2024-03-03 21:43:30 -05:00
Thomas Harte
11c4d2f09e Add further exposition. 2024-03-03 21:38:27 -05:00
Thomas Harte
f2db1b4aae Merge branch 'TiedDown' into PositiveExpression 2024-03-03 21:31:26 -05:00
Thomas Harte
b42a6e447d Tie down more corners. 2024-03-03 21:29:53 -05:00
Thomas Harte
8a83d71560 Fix condition. 2024-03-03 14:40:05 -05:00
Thomas Harte
9fd7d5c10f Switch test and meaning. 2024-03-03 14:34:21 -05:00
Thomas Harte
4e7963ee81 Clarify PC semantics; remove faulty underscore. 2024-03-03 14:11:02 -05:00
Thomas Harte
99f0233b76 Fix immediate offset and data processing operation. 2024-03-02 23:27:37 -05:00
Thomas Harte
62da0dee7f Unify reads. 2024-03-02 23:15:17 -05:00
Thomas Harte
1663d3d9d1 Introduce disaster of an attempted test run. 2024-03-02 22:40:12 -05:00
Thomas Harte
37499d493a Fix model name. 2024-03-02 21:47:09 -05:00
Thomas Harte
e6f77a9b80 Add logical right-shift tests. 2024-03-01 18:06:54 -05:00
Thomas Harte
42ba6d1281 Relocate execution code appropriately. 2024-03-01 15:02:47 -05:00
Thomas Harte
5759798ad7 Deal with downward write order. 2024-02-29 14:34:20 -05:00
Thomas Harte
fd2c5b6679 Make a quick first attempt at memory accesses. 2024-02-29 10:18:09 -05:00
Thomas Harte
93b4008f81 Localise flags, detect improper carry write. 2024-02-28 21:28:19 -05:00
Thomas Harte
904462b881 Regularise data transfers. 2024-02-28 21:23:57 -05:00
Thomas Harte
3b320bcdef Update coprocessor interface. 2024-02-28 14:43:31 -05:00
Thomas Harte
3368bdb99f Document exceptions, partly for my future self. 2024-02-28 14:34:31 -05:00
Thomas Harte
4d400c3cb7 Add easy exceptions. 2024-02-28 14:25:12 -05:00
Thomas Harte
474f9da3c2 Add banked registers. 2024-02-28 14:09:05 -05:00
Thomas Harte
c49b26701f Relocate and clarify barrel shifts. 
With a view to independent testing.
 2024-02-28 13:53:13 -05:00
Thomas Harte
9b42d35d56 Update interface. 2024-02-28 11:42:33 -05:00
Thomas Harte
645152a1fd Implement branch. 2024-02-28 11:33:28 -05:00
Thomas Harte
487ade56ed Add basic multiply. 2024-02-28 11:27:27 -05:00
Thomas Harte
60d1b36e9a Implement registers side. 2024-02-28 10:25:14 -05:00
Thomas Harte
5a48c15e46 Add scheduler side of PC writeback. 2024-02-28 10:15:23 -05:00
Thomas Harte
d6bf1808f9 Take a swing at PC-as-input. 2024-02-28 09:33:05 -05:00
Thomas Harte
b676153d21 State intention to merge status with other registers. 2024-02-27 15:36:34 -05:00
Thomas Harte
a3339cf882 Fix indentation. 2024-02-27 15:30:51 -05:00
Thomas Harte
4255283e33 Deal with conditionality up front. 2024-02-26 21:36:23 -05:00
Thomas Harte
16e827bb2c Add basic arithmetics. 2024-02-26 21:27:58 -05:00
Thomas Harte
580f402bb6 Muddle further towards data processing. 2024-02-26 14:50:45 -05:00
Thomas Harte
030dda34f0 Start poking at implementation. 2024-02-26 14:30:26 -05:00
Thomas Harte
481b6d0e69 Sketch out some status flags. 2024-02-25 22:01:51 -05:00
Thomas Harte
a88d41bf00 List the flags. 2024-02-25 15:21:54 -05:00
Thomas Harte
73d2acca12 Moderately improve comments. 2024-02-22 11:20:22 -05:00
Thomas Harte
d205e538e1 Accept the C++ I'm in; clarify and simplify interface. 2024-02-22 10:16:54 -05:00
Thomas Harte
6577f68efc Complete instruction set; consolidate mapper. 2024-02-21 15:32:27 -05:00
Thomas Harte
e986ae2878 Add coprocessor data operations and register transfers. 2024-02-21 15:25:57 -05:00
Thomas Harte
b2696450d5 Bring forwards single data transfers. 2024-02-21 14:51:51 -05:00
Thomas Harte
2bbaf73aa2 Delete was is now duplicated. 2024-02-21 14:18:41 -05:00
Thomas Harte
0fe2c1406b Start mutating towards a form that owns the switch. 2024-02-21 14:17:01 -05:00
Thomas Harte
954d920b9e Extend what's held in the operation enum. 2024-02-20 14:14:18 -05:00
Thomas Harte
57b45076c5 Start dealing with per-instruction fields. 2024-02-17 22:13:51 -05:00
Thomas Harte
9a74ab6a8e Switch to actual mnenomics, temporarily(?) shrink table. 2024-02-17 15:41:57 -05:00
Thomas Harte
bd0a15c054 Start working on ARM2 decoding. 2024-02-16 21:36:07 -05:00