Thomas Harte
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64491525b4
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Work further to guess at caller's intention for set_state.
Probably I should just eliminate the initial reset, somehow.
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2022-05-25 17:01:18 -04:00 |
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Thomas Harte
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68b184885f
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Reapply only the status.
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2022-05-25 16:54:25 -04:00 |
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Thomas Harte
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06f3c716f5
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Make better effort to establish initial state.
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2022-05-25 16:47:41 -04:00 |
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Thomas Harte
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22714b8c7f
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Capture state at instruction end, for potential inspection.
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2022-05-25 16:32:26 -04:00 |
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Thomas Harte
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f9d1c554b7
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Fix for the actual number of cycles in a standard reset.
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2022-05-25 16:05:28 -04:00 |
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Thomas Harte
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f2a7660390
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Merge branch 'master' into 68000Mk2
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2022-05-25 15:40:10 -04:00 |
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Thomas Harte
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4961e39fb6
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Mention DIVU/DIVS flags.
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2022-05-25 15:39:00 -04:00 |
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Thomas Harte
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0bedf608c0
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Add details on gaps in coverage.
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2022-05-25 15:36:27 -04:00 |
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Thomas Harte
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1ab831f571
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Add the option to log a list of all untested instructions.
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2022-05-25 13:17:01 -04:00 |
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Thomas Harte
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2c6b9b4c9d
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Switch comparative trace tests to 68000 Mk2.
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2022-05-25 11:32:00 -04:00 |
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Thomas Harte
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463fbb07f9
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Adapt remaining 68000 tests to use Mk2.
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2022-05-25 10:55:17 -04:00 |
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Thomas Harte
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4b07c41df9
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Ensure alignment of storage.
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2022-05-24 11:29:28 -04:00 |
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Thomas Harte
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a87f6a28c9
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Fix LINK A7.
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2022-05-23 10:43:17 -04:00 |
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Thomas Harte
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98325325b1
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Fix UNLINK A7.
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2022-05-23 10:27:44 -04:00 |
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Thomas Harte
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26bf66e3f8
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Fix shifts and rolls.
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2022-05-23 10:09:46 -04:00 |
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Thomas Harte
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c6b3281274
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Attempt the shifts and rolls.
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2022-05-23 09:29:19 -04:00 |
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Thomas Harte
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1e8adc2bd9
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Fix MOVEP to R.
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2022-05-23 09:00:37 -04:00 |
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Thomas Harte
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c73021cf3c
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Implement MOVE.
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2022-05-23 08:46:06 -04:00 |
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Federico Berti
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1a26d4e409
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Update nbcd_pea.json
Add missing bracket
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2022-05-23 12:14:00 +01:00 |
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Thomas Harte
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269263eecf
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Implement RTE, RTS, RTR.
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2022-05-22 21:16:38 -04:00 |
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Thomas Harte
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4e21cdfc63
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Enable NEGX/CLR tests.
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2022-05-22 20:55:21 -04:00 |
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Thomas Harte
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faef5633f8
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Ensure MOVE from SR has an effective address to write to.
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2022-05-22 20:52:00 -04:00 |
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Thomas Harte
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7d1f1a3175
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Implement MOVE [to/from] [CCR/SR].
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2022-05-22 19:45:22 -04:00 |
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Thomas Harte
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4e34727195
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Fully implement TAS.
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2022-05-22 16:14:03 -04:00 |
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Thomas Harte
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1dd6ed6ae3
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Implement TAS Dn, with detour for other TASes.
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2022-05-22 16:08:30 -04:00 |
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Thomas Harte
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cb4d6710df
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Switch to a more direct indication of progress.
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2022-05-22 11:27:58 -04:00 |
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Thomas Harte
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284f23c6ea
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Implement JMP.
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2022-05-22 07:16:38 -04:00 |
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Thomas Harte
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4b35899a12
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Bcc: properly establish offset.
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2022-05-21 20:59:34 -04:00 |
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Thomas Harte
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94288d5a94
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Excludes DBcc from standard operand fetch.
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2022-05-21 19:53:28 -04:00 |
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Thomas Harte
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c869eb1eec
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Correct omission: wasn't testing the final PC.
Plenty of new errors incoming.
|
2022-05-21 15:56:27 -04:00 |
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Thomas Harte
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176c8355cb
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The tests in chk.json now pass.
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2022-05-21 14:32:58 -04:00 |
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Thomas Harte
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e46a3c4046
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Implement JSR.
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2022-05-21 10:29:36 -04:00 |
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Thomas Harte
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256da43fe5
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Fix MOVEM other than postinc and predec.
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2022-05-20 20:47:54 -04:00 |
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Thomas Harte
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a818650027
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Add a faulty attempt at MOVEM.
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2022-05-20 18:48:19 -04:00 |
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Thomas Harte
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c7c12f9638
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After a quick check, eori_andi_ori also now passes.
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2022-05-20 14:47:11 -04:00 |
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Thomas Harte
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ee942c5c17
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Fix PC-relative fetches.
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2022-05-20 14:42:51 -04:00 |
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Thomas Harte
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d157819c49
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Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch.
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
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2022-05-20 14:29:14 -04:00 |
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Thomas Harte
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2d91fb5441
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Implement MOVEP.
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2022-05-20 14:22:32 -04:00 |
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Thomas Harte
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81431a5453
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Attempt BTST, BCHG, BCLR and BSET.
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2022-05-20 12:58:45 -04:00 |
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Thomas Harte
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6d7ec07216
|
Uncover another three already-working test files.
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2022-05-20 12:44:57 -04:00 |
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Thomas Harte
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b4978d1452
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Implement BSR, adding one more test file to the working set.
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2022-05-20 12:40:35 -04:00 |
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Thomas Harte
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45e9648b8c
|
Implement Bcc.
|
2022-05-20 12:04:43 -04:00 |
|
Thomas Harte
|
ce32957d9d
|
Shuffle two more into the working column.
|
2022-05-20 11:53:12 -04:00 |
|
Thomas Harte
|
452dd3ccfd
|
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
|
2022-05-20 11:20:23 -04:00 |
|
Thomas Harte
|
e5c1621382
|
Add missing fallthrough , patterns for all ADDs and SUBs.
|
2022-05-20 07:02:02 -04:00 |
|
Thomas Harte
|
af3518dc1f
|
Implement various ADD, SUB patterns.
|
2022-05-19 20:50:37 -04:00 |
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Thomas Harte
|
6cfc0e80d9
|
Don't test the unrecognised instruction exception.
|
2022-05-19 19:45:38 -04:00 |
|
Thomas Harte
|
334e3ec529
|
Add privilege and instruction error exceptions; permit two operands to be stored.
|
2022-05-19 16:55:16 -04:00 |
|
Thomas Harte
|
84c165459f
|
ext.json now passes.
|
2022-05-19 16:32:40 -04:00 |
|
Thomas Harte
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22b63fe1f8
|
Add EXT, and notes to self.
|
2022-05-19 15:41:02 -04:00 |
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