98 Commits

Author	SHA1	Message	Date
Thomas Harte	a282a51673	Remove last of the direct printf'ing.	2021-09-30 02:42:59 -04:00
Thomas Harte	b7b13e20d1	Single column blits should use both masks.	2021-09-29 22:49:35 -04:00
Thomas Harte	402fa41bc0	Corrects initial error value.	2021-09-29 22:19:17 -04:00
Thomas Harte	0b9ebafc0f	Flip bit deserialisation order.	2021-09-28 22:12:13 -04:00
Thomas Harte	140e24ef15	Grab further copy flags.	2021-09-28 22:11:58 -04:00
Thomas Harte	ffcd2ea10c	Attempts more properly to implement line mode.	2021-09-28 21:39:09 -04:00
Thomas Harte	cb460de94d	Makes bad first attempt at a Bresenham inner loop.	2021-09-27 22:06:00 -04:00
Thomas Harte	f6624bf776	Edges mildly closer to line output.	2021-09-26 19:18:12 -04:00
Thomas Harte	b4b6c4d86f	Attempts to support left and right masks.	2021-09-26 18:42:08 -04:00
Thomas Harte	759689ff31	Fix line mode flag, add busy status.	2021-09-26 18:16:00 -04:00
Thomas Harte	c4ab2bbeed	Hard-code fetch window width. For now.	2021-09-23 22:06:13 -04:00
Thomas Harte	42ef459e20	Resolve resting values.	2021-09-23 22:05:59 -04:00
Thomas Harte	cad1a9e0f1	Correct bit test.	2021-09-23 20:42:31 -04:00
Thomas Harte	f1d514470d	Add note to future self.	2021-09-23 20:29:39 -04:00
Thomas Harte	9a7a54f22f	Take alternative guess as to meaning of 'use' bits.	2021-09-23 18:42:12 -04:00
Thomas Harte	137d1c61bd	Allow for channel enables and blitting direction.	2021-09-23 18:38:37 -04:00
Thomas Harte	adc071ed7a	Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.	2021-09-23 18:30:35 -04:00
Thomas Harte	e06f470044	Ensure no implicit conversion from int to IntT.	2021-09-23 18:30:04 -04:00
Thomas Harte	ab69fe56c9	Take a first shot at magical instant blitting.	2021-09-23 18:13:51 -04:00
Thomas Harte	60bad22a91	Correct fetch window.	2021-09-23 18:13:24 -04:00
Thomas Harte	7092429f7c	Added some notes to self on line mode.	2021-09-20 23:08:26 -04:00
Thomas Harte	fa800bb809	Introduces code for minterm application.	2021-09-20 19:13:23 -04:00
Thomas Harte	e15f1103a0	Takes a shot at low resolution shifting.	2021-09-20 19:00:52 -04:00
Thomas Harte	a4263b5a8c	Ties bitplane collection to line position. ... Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.	2021-09-19 21:55:45 -04:00
Thomas Harte	245b7baa61	Moves the Copper into its own file.	2021-09-16 21:17:23 -04:00
Thomas Harte	0eeaaa150a	Correct Copper start address.	2021-09-16 21:01:37 -04:00
Thomas Harte	692d87f446	Attempts to restrict blitter slot allocation.	2021-09-16 19:56:28 -04:00
Thomas Harte	6572efe2a7	Clarifies word addressing.	2021-09-16 08:24:52 -04:00
Thomas Harte	8aac2bd029	Stubs in serial port status.	2021-09-14 21:53:07 -04:00
Thomas Harte	add11db369	Factors out DMADevice, which is now a parent of Blitter.	2021-09-14 20:51:32 -04:00
Thomas Harte	fd70f7ad43	Attempts to make pixel content observeable.	2021-09-08 20:57:26 -04:00
Thomas Harte	6e034c9b7f	At least manages to place a pixel region on screen. ... Albeit that I've suddenly realised that I've failed properly to think about high-res versus low-res.	2021-08-11 20:31:37 -04:00
Thomas Harte	52e375a985	Move towards playfield decoding.	2021-08-11 18:47:35 -04:00
Thomas Harte	10a5e7313f	Makes a buggy first attempt at bitplane data collection.	2021-08-10 21:28:48 -04:00
Thomas Harte	ec9cb21fae	Starts towards bitplane collection.	2021-08-10 19:01:41 -04:00
Thomas Harte	fdd02ad6a6	Neaten, slightly.	2021-08-10 09:20:34 -04:00
Thomas Harte	76e9fcc94a	Obey blitter DMA-enable mask.	2021-08-10 09:19:15 -04:00
Thomas Harte	e412927415	Logs a bit more from the Blitter, gives it access to slots.	2021-08-10 07:17:01 -04:00
Thomas Harte	dda154c7c6	Adds nonsense disk reads, which seems to lead to bitplane and blitter requests. ... Progress, at last!	2021-08-09 20:31:14 -04:00
Thomas Harte	9215535bee	Adds a container for the disk controller. ... Thereby appears to prove that my Amiga is getting as far as attempting to load from floppy.	2021-08-09 17:35:09 -04:00
Thomas Harte	1502c4530e	Takes a further step towards real timing.	2021-08-08 21:52:28 -04:00
Thomas Harte	c1df4d1c0b	Mirroring is correct.	2021-08-08 20:20:12 -04:00
Thomas Harte	7f2610c4fc	Disambiguates serial control logs.	2021-08-07 16:57:30 -04:00
Thomas Harte	db3c158215	Further increases logging.	2021-08-05 20:07:14 -04:00
Thomas Harte	25e2bd307a	Sets VPA for CIA accesses; logs a little more.	2021-08-05 20:06:48 -04:00
Thomas Harte	1bae4973bc	Post the serial control write onwards.	2021-07-30 18:24:27 -04:00
Thomas Harte	3d9f86c584	Begins keyboard sketches and notes.	2021-07-30 18:23:15 -04:00
Thomas Harte	3514e537ca	Minor logging tweaks.	2021-07-30 18:22:59 -04:00
Thomas Harte	b78090ec76	Fixes IOPortsAndTimers classification.	2021-07-28 19:39:42 -04:00
Thomas Harte	759007ffc1	Attempts to route CIA interrupts.	2021-07-28 19:36:30 -04:00