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Author	SHA1	Message	Date
Thomas Harte	15f6c51062	Added the most trivial implementation of the ZX81 wait line.	2017-06-21 21:28:14 -04:00
Thomas Harte	5e21c706f3	Merge pull request #132 from TomHarte/MachineCycles ... Subdivides the Z80's machine cycles	2017-06-21 21:19:48 -04:00
Thomas Harte	e1355d4b62	Restored proper video output.	2017-06-21 21:18:09 -04:00
Thomas Harte	7eeac3b586	Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation.	2017-06-21 21:11:00 -04:00
Thomas Harte	4bf13610ce	Reinstated interrupts by moving the refresh test back into the refresh cycle.	2017-06-21 21:03:39 -04:00
Thomas Harte	0e0ce379b4	Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.	2017-06-21 20:38:08 -04:00
Thomas Harte	36e8a11505	Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.	2017-06-21 20:32:08 -04:00
Thomas Harte	45f442ea63	Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.	2017-06-21 19:08:48 -04:00
Thomas Harte	db743c90d8	Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.	2017-06-21 18:58:44 -04:00
Thomas Harte	10cc94f581	Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.	2017-06-21 18:47:00 -04:00
Thomas Harte	108da64562	Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.	2017-06-20 22:25:00 -04:00
Thomas Harte	f85b46286e	Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.	2017-06-20 22:20:58 -04:00
Thomas Harte	184b371649	Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.	2017-06-20 21:48:50 -04:00
Thomas Harte	b0375bb037	Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.	2017-06-20 21:32:23 -04:00
Thomas Harte	48942848e7	Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.	2017-06-20 21:15:56 -04:00
Thomas Harte	27ac342928	Corrected conditional call timing, and its test.	2017-06-20 20:57:23 -04:00
Thomas Harte	25aba16ef8	Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.	2017-06-19 22:20:23 -04:00
Thomas Harte	a0d0f383c8	Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.	2017-06-19 22:07:36 -04:00
Thomas Harte	6752f165db	Added failing tests for both kinds of CALL.	2017-06-19 22:03:29 -04:00
Thomas Harte	e05076b258	Added tests for everything except CALL. All passing.	2017-06-19 22:00:04 -04:00
Thomas Harte	fadbfdf801	Added DJNZ test.	2017-06-19 21:31:56 -04:00
Thomas Harte	cb277b8d1e	Added JP and JR tests.	2017-06-19 21:27:23 -04:00
Thomas Harte	234f14dbbe	Tests were at fault; all passing now.	2017-06-19 21:14:40 -04:00
Thomas Harte	99ede3a9ef	BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).	2017-06-19 21:04:14 -04:00
Thomas Harte	378233f53d	Extended to BITs and SETs, accruing three new failures.	2017-06-19 21:01:30 -04:00
Thomas Harte	f903408980	Caught up on comments.	2017-06-19 20:53:22 -04:00
Thomas Harte	cc8f316941	Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).	2017-06-19 20:51:28 -04:00
Thomas Harte	b684254908	Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.	2017-06-19 20:33:34 -04:00
Thomas Harte	351d90ca55	Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.	2017-06-19 20:04:55 -04:00
Thomas Harte	23177df26a	Added various tests of the basic ALU ops.	2017-06-19 19:53:26 -04:00
Thomas Harte	ba15371948	Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.	2017-06-19 19:47:00 -04:00
Thomas Harte	73dbaebbc1	Fixed timing of EX (SP), HL/IX.	2017-06-19 19:25:53 -04:00
Thomas Harte	8d60734737	Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.	2017-06-19 19:17:54 -04:00
Thomas Harte	002098d496	The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.	2017-06-19 07:45:41 -04:00
Thomas Harte	e3244eb68e	Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes.	2017-06-19 07:39:46 -04:00
Thomas Harte	85c6fb1430	Explained refresh cycles to the all-RAM Z80.	2017-06-19 07:36:11 -04:00
Thomas Harte	54e4643396	Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.	2017-06-19 07:34:23 -04:00
Thomas Harte	85c5c4405a	Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.	2017-06-19 07:30:01 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	cb140aa06e	Managed to navigate back to building.	2017-06-18 21:00:44 -04:00
Thomas Harte	6a769d3953	Finally dipped below the 20 error threshold that the compiler tops out at.	2017-06-18 20:34:46 -04:00
Thomas Harte	3be8ffd826	Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors.	2017-06-18 20:31:12 -04:00
Thomas Harte	bb910e14a4	Dealt with the CB page.	2017-06-18 18:01:33 -04:00
Thomas Harte	69ebbe019a	Completed ED page conversion. Rolling onwards...	2017-06-18 17:56:48 -04:00
Thomas Harte	0d39672d32	Fixing typos here and there, persuaded the first half of the ED table to compile.	2017-06-18 17:48:54 -04:00
Thomas Harte	0d1231980a	Advanced to getting specific warnings in the ed-page table. So that's progress.	2017-06-18 17:25:15 -04:00
Thomas Harte	82a015892b	Started adapting to the newly-segmented world.	2017-06-18 17:18:01 -04:00
Thomas Harte	194b7f60c5	Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.	2017-06-18 17:08:50 -04:00
Thomas Harte	ebc7356db5	Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.	2017-06-18 12:21:27 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00