Thomas Harte
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a8645f80bf
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Introduces 'non-exclusive' emulator-space keyboards.
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
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2018-10-24 21:59:30 -04:00 |
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Thomas Harte
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c07f9fed99
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Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
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2018-10-21 18:42:49 -04:00 |
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Thomas Harte
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616777517d
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Makes the failing test more communicative, in the hope of more easily debugging errors.
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2018-10-21 14:35:44 -04:00 |
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Thomas Harte
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b3f1677da5
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Introduces new failing test for rational continuous interrupt prediction.
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2018-10-21 13:59:14 -04:00 |
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Thomas Harte
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725b364bbc
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Improves testing; now tests for time to the first interrupt.
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2018-10-20 18:25:55 -04:00 |
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Thomas Harte
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acdc84e08c
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Improves test slightly, and fixes line interrupt reload value setting.
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2018-10-09 22:14:35 -04:00 |
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Thomas Harte
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c128ddb549
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Introduces a first unit test for line interrupts and corrects backup behaviour.
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2018-10-09 21:49:21 -04:00 |
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Thomas Harte
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fc84ae611e
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Resolves various instances of spaces in place of tabs.
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2018-09-09 20:33:56 -04:00 |
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Thomas Harte
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ddf45a0010
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Ensures NMI and RST reset D on 65C02s.
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2018-08-14 19:49:14 -04:00 |
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Thomas Harte
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261fb3d4f8
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Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
This gets Klaus Dorman's test to pass.
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2018-08-10 22:42:35 -04:00 |
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Thomas Harte
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b63e0cff72
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Improves has-completed test.
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2018-08-10 22:27:01 -04:00 |
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Thomas Harte
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5d6e479338
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Implements RMB and SMB, and fixes SBC (zero).
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2018-08-10 22:13:51 -04:00 |
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Thomas Harte
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90094529a5
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Implements TSB and TRB, and adds the extra BIT instructions.
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2018-08-10 22:04:45 -04:00 |
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Thomas Harte
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aed4c0539e
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Implements STZ.
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2018-08-10 21:17:02 -04:00 |
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Thomas Harte
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95164b79c9
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Attempted implementation of (zp) addressing mode.
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2018-08-09 21:51:14 -04:00 |
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Thomas Harte
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bb680b40d8
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Implements the 65C02's JMPs.
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2018-08-08 22:26:57 -04:00 |
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Thomas Harte
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e3f6da6994
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Implements the 65C02 NOPs.
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2018-08-08 20:00:14 -04:00 |
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Thomas Harte
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32338bea4d
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Implements BRA.
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2018-08-06 22:37:30 -04:00 |
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Thomas Harte
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1a44ef0469
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Introduces Klaus Dorman's 65C02 tests. All failing.
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2018-08-06 21:48:43 -04:00 |
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Thomas Harte
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ebce9a2e51
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Fixes test target.
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2018-08-06 21:15:13 -04:00 |
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Thomas Harte
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abca38a548
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Makes an initial removal of PCMPatchedTrack. Farewell, old friend.
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2018-07-01 22:49:57 -04:00 |
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Thomas Harte
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853261364e
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Generalised CRC generation and created specific subclasses for the CCITT CRC16 and CRC32.
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2018-05-23 22:21:57 -04:00 |
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Thomas Harte
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0b771ce61a
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Removes all instances of the copyright symbol.
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2018-05-13 15:19:52 -04:00 |
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Thomas Harte
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05e31d7594
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Mutates testComplicatedTrackSeek into an actual test.
Which frustratingly passes.
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2018-05-01 19:52:12 -04:00 |
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Thomas Harte
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f4097290c2
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Made various corrections following a quick for-loop constness audit.
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2018-04-30 22:23:57 -04:00 |
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Thomas Harte
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b32538f3c8
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Adds an additional test.
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2018-04-30 22:05:44 -04:00 |
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Thomas Harte
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e7618bb32e
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Corrects types (/chickens out).
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2018-04-30 22:04:05 -04:00 |
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Thomas Harte
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e599e65087
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Switches to use of the TargetList typedef wherever possible.
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2018-04-14 19:46:38 -04:00 |
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Thomas Harte
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389979923e
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Performs update to and satisfaction of Xcode 9.3's preferred warnings.
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2018-03-30 10:25:01 -04:00 |
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Thomas Harte
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f0f9d5a6af
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Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
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2018-03-08 20:30:22 -05:00 |
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Thomas Harte
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fdef914137
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Corrects test target regression.
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2018-03-06 18:32:21 -05:00 |
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Thomas Harte
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66faed4008
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Gives MachineForTargets complete responsibility for initial machine state.
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2018-01-25 18:28:19 -05:00 |
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Thomas Harte
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21efb32b6f
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Integrates the static and nascent dynamic analyser namespaces.
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2018-01-24 21:48:44 -05:00 |
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Thomas Harte
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ed564cb810
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Implements the main four cartridge banking schemes.
Slightly proof of concept for now.
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2018-01-04 22:18:18 -05:00 |
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Thomas Harte
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c8367a017f
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Cleans up test and makes attempt to factor in cartridge type popularity.
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2018-01-01 21:21:05 -05:00 |
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Thomas Harte
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344a12566b
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Tweaks a couple of expected cartridge types.
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2018-01-01 20:14:56 -05:00 |
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Thomas Harte
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c07113ea95
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Ensures no illegal accesses while testing MSX ROM type detection.
Specifically: the static analyser doesn't even correctly identify everything that is an MSX ROM yet, let alone then properly determine type.
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2018-01-01 17:38:26 -05:00 |
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Thomas Harte
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bc2879c412
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Corrects the MSX ROM unit test.
I.e. the test is correct now, for those SHAs I could find. The static analyser is still wrong just slightly less than half the time.
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2018-01-01 17:35:13 -05:00 |
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Thomas Harte
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db25b4554b
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Introduces failing tests of the MSX static analyser.
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2018-01-01 16:38:26 -05:00 |
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Thomas Harte
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05b95ea2e0
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Corrects Xcode tests.
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2018-01-01 16:04:13 -05:00 |
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Thomas Harte
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6e1d69581c
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Eliminates a variety of end-of-line spaces.
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2017-11-07 22:54:22 -05:00 |
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Thomas Harte
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f95515ae81
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Eliminates a large number of instance of end-of-line tabs.
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2017-11-07 22:51:06 -05:00 |
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Thomas Harte
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064f1dfdbc
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Removes usages of deprecated initialiser.
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2017-10-05 18:10:47 -04:00 |
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Thomas Harte
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ff24e1de31
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Corrects 6522 bridge per has-a-not-is-a template switch.
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2017-09-04 21:56:21 -04:00 |
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Thomas Harte
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7af3de010e
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Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
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2017-08-23 22:25:31 -04:00 |
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Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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761afad118
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Corrected timestamp return, and its testing by the 6502 timing tests.
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2017-07-27 21:19:16 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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9257a3f6d7
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Added test for 16-bit arithmetic, and fixed implementation.
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2017-07-26 19:04:52 -04:00 |
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Thomas Harte
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728143247d
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Added a test for RLD and RRD. Which already passes.
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2017-07-26 18:56:35 -04:00 |
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Thomas Harte
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6ec4e4e3d7
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Merge branch 'master' into Memptr
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2017-07-25 23:01:34 -04:00 |
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Thomas Harte
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37ccb9d3b6
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Fixed 6502 timing tests.
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2017-07-25 23:00:39 -04:00 |
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Thomas Harte
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3c254360ba
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Completed fixture of the 6502 BCD test.
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2017-07-25 22:55:45 -04:00 |
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Thomas Harte
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3ca51bedc6
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Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
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2017-07-25 22:48:44 -04:00 |
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Thomas Harte
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36076b7ea5
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Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
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2017-07-25 22:38:26 -04:00 |
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Thomas Harte
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df4732be2e
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Corrected test.
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2017-07-24 22:33:49 -04:00 |
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Thomas Harte
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9435c1e12a
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The 1540 is now a ClockReceiver.
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2017-07-24 22:32:41 -04:00 |
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Thomas Harte
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2912d7055b
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The 6532 is now a ClockReceiver.
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2017-07-24 21:57:24 -04:00 |
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Thomas Harte
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13f7aa4063
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The TIA is now a ClockReceiver.
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2017-07-24 21:48:34 -04:00 |
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Thomas Harte
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b3ae920746
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Converted the DPLL and disk controller classes to be ClockReceivers.
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2017-07-24 21:04:47 -04:00 |
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Thomas Harte
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e6578defcd
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It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
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2017-07-23 22:22:50 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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b0c2325adc
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Corrected run call, and accepted that jam handling is gone forever.
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2017-07-22 22:21:26 -04:00 |
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Thomas Harte
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4ea835e50b
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Added test for EX (SP), rp, which passes.
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2017-07-22 17:17:32 -04:00 |
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Thomas Harte
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6437c43147
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Added CPI and CPD tests: at last two that pass without requiring implementation changes!
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2017-07-22 12:38:18 -04:00 |
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Thomas Harte
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5928a24803
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Transcribed missing tests as TODOs.
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2017-07-22 11:44:17 -04:00 |
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Thomas Harte
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20a6bcc676
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Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
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2017-07-22 11:39:13 -04:00 |
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Thomas Harte
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eaf313b0f6
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Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
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2017-07-22 11:20:21 -04:00 |
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Thomas Harte
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d51b66c204
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Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
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2017-07-21 23:01:35 -04:00 |
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Thomas Harte
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660f0e4c40
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Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
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2017-07-21 22:52:25 -04:00 |
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Thomas Harte
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7b5f93510b
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Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
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2017-07-16 20:55:57 -04:00 |
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Thomas Harte
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8ddd686049
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Removed redundant variable.
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2017-07-16 19:04:03 -04:00 |
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Thomas Harte
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2fb0aea990
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Updated the C1540 test vessel to the new world.
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2017-07-16 17:00:39 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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Thomas Harte
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27ac342928
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Corrected conditional call timing, and its test.
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2017-06-20 20:57:23 -04:00 |
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Thomas Harte
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6752f165db
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Added failing tests for both kinds of CALL.
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2017-06-19 22:03:29 -04:00 |
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Thomas Harte
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e05076b258
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Added tests for everything except CALL. All passing.
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2017-06-19 22:00:04 -04:00 |
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Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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b684254908
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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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2017-06-19 20:33:34 -04:00 |
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Thomas Harte
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351d90ca55
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Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
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2017-06-19 20:04:55 -04:00 |
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Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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0f18768091
|
Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
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2017-06-17 18:19:25 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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