Thomas Harte
cfafbfd141
Fix interrupt acknowledge cycle: signals and data size.
2022-06-04 21:23:57 -04:00
Thomas Harte
659e4f6987
Include fixed cost of rolls. Which includes providing slightly more information to did_shift.
2022-06-01 20:30:51 -04:00
Thomas Harte
80c1bedffb
Eliminate false prefetch for BSR.
2022-05-25 16:32:02 -04:00
Thomas Harte
a5f2dfbc0c
Initialise registers to 0 for better testability.
...
TODO: is this the real initial state?
2022-05-25 11:47:42 -04:00
Thomas Harte
0f7cb2fa5a
Attempt to honour the trace flag.
2022-05-24 15:47:47 -04:00
Thomas Harte
01e93ba916
Make an attempt at bus/address error.
2022-05-24 15:42:50 -04:00
Thomas Harte
780954f27b
Add TRAP, TRAPV.
2022-05-24 15:14:46 -04:00
Thomas Harte
a7e8aef9d3
Add MOVEA, be slightly more careful about next_operand_.
2022-05-24 11:30:09 -04:00
Thomas Harte
3349bcaaed
Attempt interrupt support.
2022-05-24 10:53:59 -04:00
Thomas Harte
b037c76da6
Add public interface for everything except HALT and BUS REQ/etc.
...
... neither of which are used by machines I currently implement.
2022-05-23 20:55:01 -04:00
Thomas Harte
9cac4ca317
Add MOVE to/from USP.
2022-05-23 20:42:41 -04:00
Thomas Harte
e0a279344c
Codify the existence of special cases, implement NOP and RESET.
2022-05-23 15:09:46 -04:00
Thomas Harte
e2f4db3e45
Shuffle more of the flow controller methods into their proper place.
2022-05-23 12:06:14 -04:00
Thomas Harte
363cd97154
Resolve double definition of did_shift.
2022-05-23 10:07:24 -04:00
Thomas Harte
1b3acf9cd8
Eliminate assumption.
2022-05-23 08:18:37 -04:00
Thomas Harte
4e34727195
Fully implement TAS.
2022-05-22 16:14:03 -04:00
Thomas Harte
1dd6ed6ae3
Implement TAS Dn, with detour for other TASes.
2022-05-22 16:08:30 -04:00
Thomas Harte
3b68b9a83b
Implement PEA.
2022-05-22 11:27:38 -04:00
Thomas Harte
3c1c4f89e9
Add MULU/S functionality, though not timing.
2022-05-22 08:02:32 -04:00
Thomas Harte
4a6512f5d5
Reduce dispatch boilerplate.
2022-05-22 07:39:16 -04:00
Thomas Harte
f97d2a0eb9
Add DIVU/DIVS, at least as far as getting the correct numeric result.
2022-05-21 15:56:09 -04:00
Thomas Harte
a818650027
Add a faulty attempt at MOVEM.
2022-05-20 18:48:19 -04:00
Thomas Harte
9d79e64f5c
Add a mere calculate effective address pathway.
...
Plus a lot of waffle to try to justify the further code duplication.
2022-05-20 16:23:52 -04:00
Thomas Harte
2d91fb5441
Implement MOVEP.
2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453
Attempt BTST, BCHG, BCLR and BSET.
2022-05-20 12:58:45 -04:00
Thomas Harte
b4978d1452
Implement BSR, adding one more test file to the working set.
2022-05-20 12:40:35 -04:00
Thomas Harte
45e9648b8c
Implement Bcc.
2022-05-20 12:04:43 -04:00
Thomas Harte
860cc63e21
Attempt DBcc.
2022-05-20 11:32:06 -04:00
Thomas Harte
452dd3ccfd
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382
Add missing fallthrough, patterns for all ADDs and SUBs.
2022-05-20 07:02:02 -04:00
Thomas Harte
6c2eee0e44
Implement CHK, and therefore the standard exception pattern.
2022-05-19 16:27:39 -04:00
Thomas Harte
0471decfc8
Implement the complete set of fetch addressing modes.
...
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
2022-05-19 15:03:22 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
bef12f3d65
Move ExecutionState into Implementation.hpp; use goto to avoid some double switches.
...
Re: the latter, yuck. Yuck yuck yuck. But it does mean I can stop going back and forth on how to structure conditionality on effective address generation segueing into fetches without doubling up on tests.
2022-05-18 15:35:38 -04:00
Thomas Harte
aa9e7eb7a2
Codify MOVE's status somewhat, avoid reading write-only operands.
2022-05-17 16:57:33 -04:00
Thomas Harte
4a40581deb
Completes performance of NBCD D0.
2022-05-17 16:10:20 -04:00
Thomas Harte
84071ac6d0
Implement reset logic, advance as far as actually performing an NBCD on D0 (but not writing it back).
2022-05-17 14:51:49 -04:00
Thomas Harte
1a27eea46c
Establish general pattern for selecting a performance phase and obtaining operands.
2022-05-17 14:08:50 -04:00
Thomas Harte
d0b6451f02
Step gingerly on to fetching operands.
2022-05-17 08:26:35 -04:00
Thomas Harte
3db2de7478
Works 68000 mk2 into the comparative tests.
...
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
345f7c3c62
Fill in just enough to attempt the reset exception, assuming DTACK rather than VPA or BERR.
2022-05-16 16:57:40 -04:00
Thomas Harte
6f6e466c08
Make a first sketch of the coroutine-esque structure I'm going to experiment with here.
2022-05-16 11:59:03 -04:00
Thomas Harte
b0518040b5
Plants the seek of a 68000 mark 2.
2022-05-16 11:44:16 -04:00
