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11,575 Commits 8 Branches 121 Tags 496 MiB
a5a653d684
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11575 Commits

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Author SHA1 Message Date
Thomas Harte
a5a653d684 Factor vsync state into IO reads. 2024-04-09 21:49:00 -04:00
Thomas Harte
6123350895 Improve state guesswork. 2024-04-09 21:24:08 -04:00
Thomas Harte
ec73c00c3b Silence the routine stuff of interrupt masks. 2024-04-09 20:57:57 -04:00
Thomas Harte
dd24f5f4f3 Don't latch video addresses until almost the last minute. 2024-04-09 20:56:10 -04:00
Thomas Harte
82a2e802ea
Life's too short; just do it in HTML. 2024-04-08 23:11:22 -04:00
Thomas Harte
3b75eeb70a Try two divs. 2024-04-08 22:46:45 -04:00
Thomas Harte
ee4575b70f Attempt a div. 2024-04-08 22:45:41 -04:00
Thomas Harte
46a4ec1cb1 Reshuffle images. 2024-04-08 22:42:49 -04:00
Thomas Harte
8ab77a3260 Attempt to even out columns. 2024-04-08 22:39:14 -04:00
Thomas Harte
b875e349c1 Mention the Archimedes. 2024-04-08 22:34:08 -04:00
Thomas Harte
169298af42 Plumb through disk insertion. 
Surprisingly: some things now load.
 2024-04-08 21:15:40 -04:00
Thomas Harte
5e502df48b Forward motor and drive selection. 2024-04-07 22:29:00 -04:00
Thomas Harte
4f58664f97 Catch interrupt enables. 2024-04-07 22:08:12 -04:00
Thomas Harte
ffd298218c Tie off initial values; fix FIQ usage. 2024-04-07 21:58:16 -04:00
Thomas Harte
d2b077c573 Start wiring in a floppy controller. 2024-04-07 21:22:35 -04:00
Thomas Harte
547dc29a60 Remove done TODOs. 2024-04-07 15:53:42 -04:00
Thomas Harte
69aeca5c0e Aggregate mouse deltas where possible. 2024-04-06 21:24:21 -04:00
Thomas Harte
ed7cd4b277 Fix 8bpp output, all-modes cursor. 2024-04-06 20:58:44 -04:00
Thomas Harte
7bf831e1a6 Add missing 'override'. 2024-04-06 13:51:33 -04:00
Thomas Harte
0092cb8c36 Route enough to be able to mess around. 2024-04-06 13:44:05 -04:00
Thomas Harte
543b1c644a Wire mouse events to the relevant class. 2024-04-06 13:32:59 -04:00
Thomas Harte
cfaea7a90c Add cursor within 4bpp pixel area. 2024-04-05 22:43:10 -04:00
Thomas Harte
b821645644 Capture cursor palette, switch horizontal field. 2024-04-05 22:01:01 -04:00
Thomas Harte
2865190499 Resolve video addressing issues. 2024-04-05 21:56:31 -04:00
Thomas Harte
3f40e409c5 Reduce debugging heft. 2024-04-04 22:16:11 -04:00
Thomas Harte
002e235d90 Force RGB mode. 2024-04-04 22:02:47 -04:00
Thomas Harte
7d8a364658 Reimplement LDM and STM. 2024-04-04 21:59:18 -04:00
Thomas Harte
41c471ca52 Add a force-user-aware accessor. 2024-04-04 20:17:44 -04:00
Thomas Harte
dd127f64fe Simplify range. 2024-04-03 07:23:14 -04:00
Thomas Harte
b19dcfd6dc Take another run at shifts. 2024-04-02 21:57:46 -04:00
Thomas Harte
55369464ad Add a by-eye crop. A better answer will come. 2024-04-01 22:10:05 -04:00
Thomas Harte
609c117267 Switch to English RISC OS. 2024-04-01 21:44:42 -04:00
Thomas Harte
3b62a2fe7a Restrict video buffer to first 512kb. 2024-04-01 21:39:10 -04:00
Thomas Harte
7c9715f00c Change mind about carry behaviour. 2024-04-01 21:38:44 -04:00
Thomas Harte
7de92a9457 Slightly clean up shift code. 2024-04-01 21:24:49 -04:00
Thomas Harte
0866caf934 Flaws remain, but acknowledge that pixel rate is double. 2024-04-01 10:48:20 -04:00
Thomas Harte
914b88d115 Fix non-debug build. 2024-03-31 19:17:55 -04:00
Thomas Harte
cc122a7a68 Add an SWI count, to aid in logging. 2024-03-31 18:18:26 -04:00
Thomas Harte
31979649c6 As it continues to swell, factor out the junk. 2024-03-31 18:15:48 -04:00
Thomas Harte
335d13d06d Mildly improve logging, define a few more ROMs. 2024-03-30 21:49:21 -04:00
Thomas Harte
ec785f3a8a Add URL as comment. 2024-03-30 20:54:17 -04:00
Thomas Harte
1f83a5425e Complete list of all currently-failing SWIs. 
... a lot of which are probably failing correctly, i.e. they're appropriately signalling.
 2024-03-30 20:48:47 -04:00
Thomas Harte
4882d6d0f2 Start adding SWI detail. 2024-03-30 15:16:48 -04:00
Thomas Harte
722743659b Add missing space. 2024-03-29 21:52:57 -04:00
Thomas Harte
6e64a79b52 Log failed SWIs. 2024-03-29 21:31:33 -04:00
Thomas Harte
8a6bf84cff Keyboard: log more, ignore unrecognised commands. 2024-03-29 20:54:07 -04:00
Thomas Harte
a0fdd8f4eb Resolve magic constant. 2024-03-28 22:15:27 -04:00
Thomas Harte
bda1783624 Make new guess at non-byte IOC reads. 2024-03-28 22:10:49 -04:00
Thomas Harte
2a14557478 Be more disciplined about errant accesses. 2024-03-28 21:31:07 -04:00
Thomas Harte
0ddbc67b1f Switch to default CMOS RAM obtained from RISC OS itself. 2024-03-28 21:23:49 -04:00