Thomas Harte
23c47e21de
Proceeds the ColecoVision to booting.
2018-02-24 18:14:38 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
b034d4e6f8
Refactors the Z80 to separate out interface and implementation.
...
Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
2017-09-01 20:50:24 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
Thomas Harte
95d360251d
Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
2017-08-24 21:32:33 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
e1aded0d95
Allows Z80 users to opt out of support for the bus request line. Which both now do.
2017-08-21 20:43:12 -04:00
Thomas Harte
6315c22b80
Removed repeated checking of bus_request_line_. It's now checked only after each outward perform_machine_cycle.
2017-08-20 12:39:45 -04:00
Thomas Harte
039811ce6a
Switched the Z80 to being something a machine has, not something a machine is.
2017-08-02 22:09:59 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
8848ebbd4f
Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
2017-07-27 21:10:14 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
60e374dca3
Merge branch 'master' into Memptr
2017-07-27 07:54:25 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
81a3899381
Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
2017-07-26 19:42:00 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
966b5e6372
Adapted the Z80's perform_machine_cycle to return Cycles.
2017-07-25 22:25:44 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
Thomas Harte
ec3aa06caf
Removed dangling reference.
2017-07-23 22:16:00 -04:00
Thomas Harte
ba088e5545
Adapted the Z80 into a clock receiver, which also vends Cycles rather than a raw int within its PartialMachineCycle struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first.
2017-07-23 22:15:04 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
540a03f75c
Exposed the memptr register.
2017-07-21 22:31:42 -04:00
Thomas Harte
9b72c445a7
Fixed indexing type.
2017-07-21 21:19:46 -04:00
Thomas Harte
aec4fd066b
I think I've definitively decided against this model of timing.
2017-06-22 21:32:14 -04:00
Thomas Harte
95a6b0f85c
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-22 21:09:26 -04:00
Thomas Harte
b7c978e078
Added getters for most of the input lines, and attempted to round out the ZX81's wait logic.
2017-06-22 20:11:19 -04:00
Thomas Harte
f0398a6db8
Added wait state hooks to the interrupt programs, and added an is_wait query on PartialMachineCycle.
2017-06-22 20:07:47 -04:00
Thomas Harte
7eeac3b586
Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation.
2017-06-21 21:11:00 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
2017-06-21 20:32:08 -04:00
Thomas Harte
45f442ea63
Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.
2017-06-21 19:08:48 -04:00
Thomas Harte
db743c90d8
Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.
2017-06-21 18:58:44 -04:00
Thomas Harte
10cc94f581
Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.
2017-06-21 18:47:00 -04:00
Thomas Harte
108da64562
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
2017-06-20 22:25:00 -04:00
Thomas Harte
f85b46286e
Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.
2017-06-20 22:20:58 -04:00
Thomas Harte
184b371649
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
2017-06-20 21:48:50 -04:00
Thomas Harte
b0375bb037
Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.
2017-06-20 21:32:23 -04:00
Thomas Harte
48942848e7
Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.
2017-06-20 21:15:56 -04:00
Thomas Harte
27ac342928
Corrected conditional call timing, and its test.
2017-06-20 20:57:23 -04:00
Thomas Harte
25aba16ef8
Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.
2017-06-19 22:20:23 -04:00
Thomas Harte
a0d0f383c8
Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.
2017-06-19 22:07:36 -04:00
Thomas Harte
cc8f316941
Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).
2017-06-19 20:51:28 -04:00
Thomas Harte
b684254908
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
2017-06-19 20:33:34 -04:00
Thomas Harte
ba15371948
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
2017-06-19 19:47:00 -04:00
