Thomas Harte
245e27c893
Solidifies belief that the shift register bit is cleared on read/write.
2019-07-08 16:45:15 -04:00
Thomas Harte
28de629c08
Fixes the 6522 sufficiently to fix keyboard input.
2019-07-08 15:29:34 -04:00
Thomas Harte
210bcaa56d
Introduces an initial shift unit test, and makes it pass.
2019-07-07 22:13:36 -04:00
Thomas Harte
191a7a9386
Reintroduces an empty second drive.
...
This prevents the uninitialised disk error. Which is a clue.
2019-07-02 16:59:00 -04:00
Thomas Harte
b9c2c42bc0
Switches drives to using floats for time counting.
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Hopefully to eliminate a lot of unnecessary `Time` work; inaccuracies should still be within tolerable range.
2019-07-02 15:43:03 -04:00
Thomas Harte
6c588a1510
Makes some further random swings at tracking the startup procedure.
2019-06-28 13:03:47 -04:00
Thomas Harte
00c32e4b59
Further miscellaneous changes to debug logging. All temporary.
2019-06-18 10:34:31 -04:00
Thomas Harte
877b46d2c1
Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'.
2019-06-15 16:08:54 -04:00
Thomas Harte
cc7226ae9f
Starts trying to get a bit more rigorous about collected meanings.
2019-06-13 22:48:10 -04:00
Thomas Harte
bde975a3b9
Possibly mights the tiniest bit of headway with 'the IWM'.
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I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
2019-06-13 22:38:09 -04:00
Thomas Harte
f6f9024631
Corrects Macintosh aspect ratio (and framing).
2019-06-13 18:41:38 -04:00
Thomas Harte
535747e3f2
Restores single-line logging format.
2019-06-13 13:35:03 -04:00
Thomas Harte
d6150645c0
By hook or by crook, mouse input now works.
2019-06-12 22:19:25 -04:00
Thomas Harte
ccd2cb44a2
Fills in enough of the SCC to allow completion of the Macintosh side of that relationship.
2019-06-12 17:51:50 -04:00
Thomas Harte
ad8b68c998
Switches to a proper form of zero-upon-read data.
...
Not that it's necessarily correct.
2019-06-11 19:53:51 -04:00
Thomas Harte
3c075e9542
Switches drives 0 and 1.
2019-06-10 14:58:39 -04:00
Thomas Harte
9230969f43
Corrects enough of the 6522 and Keyboard to get an initial command seemingly working.
2019-06-10 09:28:27 -04:00
Thomas Harte
0e16c67805
Improves shift register connection, towards having the keyboard function properly.
...
It now seems not to receive a command terminator, but is at least getting a command.
2019-06-08 23:04:55 -04:00
Thomas Harte
697e094a4e
Sketches out the absolute basics of an SCC interface.
2019-06-08 18:47:11 -04:00
Thomas Harte
50d37798a2
Eradicates magic constants.
2019-06-06 21:37:43 -04:00
Thomas Harte
e9d0676e75
Fiddles further with the tachometer.
2019-06-06 21:36:19 -04:00
Thomas Harte
7591906777
Numerous IWM fixes: the machine now seems to be trying to measure the tachometer.
2019-06-06 18:32:11 -04:00
Thomas Harte
a413ae11cb
Makes some sort of first attempt at having the IWM read.
2019-06-04 22:13:00 -04:00
Thomas Harte
b8a1553368
Adds putative support for PlusToo-style BIN files.
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Albeit a bit of a guess, since it's not intended to be an emulator file format.
2019-06-04 21:41:09 -04:00
Thomas Harte
8557558bd8
Mildly improves investigatory reporting.
2019-06-03 21:51:45 -04:00
Thomas Harte
abe55fe950
Adds Timer 1 toggling of PB7.
2019-06-03 15:39:20 -04:00
Thomas Harte
da2b190288
Stores expected bit length.
2019-06-01 19:08:29 -04:00
Thomas Harte
48d837c636
Attempts to respond more sensibly to various queries.
...
Including adding a 1-second delay on motor off.
2019-06-01 18:43:47 -04:00
Thomas Harte
723137c0d4
With some time additions to the 6522, starts wiring in Macintosh audio.
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The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
2019-06-01 14:39:40 -04:00
Thomas Harte
4197c6f149
Attempts to make some further semantic sense of the various IWM controls.
2019-05-30 22:17:49 -04:00
Thomas Harte
4632be4fe5
Wires up the final IWM signal, SEL, preparatory to an implementation.
2019-05-30 12:08:00 -04:00
Thomas Harte
8293b18278
Adds a TODO on what I think might be an incorrect implementation?
2019-05-08 15:06:40 -04:00
Thomas Harte
2ba0364850
Adds the shift register interrupt.
2019-05-08 15:02:07 -04:00
Thomas Harte
2e7bc0b98a
Attempts the shift register.
2019-05-08 14:54:40 -04:00
Thomas Harte
8278809383
Attempts to get more rigorous on communicating outward control line changes.
2019-05-08 13:33:22 -04:00
Thomas Harte
4367459cf2
Takes a first go at handshake and pulse modes.
2019-05-08 12:48:29 -04:00
Thomas Harte
254132b83d
Eliminates 6522Base in pursuit of working handshake modes.
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Specifically: this means that the places from which the BusHandler may be called are more numerous.
2019-05-08 12:35:17 -04:00
Thomas Harte
7e6d4f5a3e
Adds emulation of the real-time clock.
2019-05-08 00:12:19 -04:00
Thomas Harte
ce099a297a
Eliminates RAM writes in ROM area.
...
I no longer think that logic is correct.
2019-05-07 17:16:22 -04:00
Thomas Harte
96facc103a
Adds an IWM shim and corrects graphics output.
...
... now that there is some.
2019-05-05 21:55:34 -04:00
Thomas Harte
62a1d69cee
Implements proper AY IO output behaviour.
2019-03-05 20:20:26 -05:00
Thomas Harte
d97348dd38
Eliminates dangling uses of printf.
2019-03-02 18:07:05 -05:00
Thomas Harte
7030abca97
Corrects PAL colours for the Vic-20.
2019-02-25 19:28:52 -05:00
Thomas Harte
e5addb27ec
Corrects log output.
2019-02-18 20:49:01 -05:00
Thomas Harte
2ef6d4327c
Resolves further build warnings.
2019-01-13 20:37:50 -05:00
Thomas Harte
248a8efd2f
Corrects declared pixel clock GCD.
2019-01-06 16:32:13 -05:00
Thomas Harte
601961deeb
Wires through set_display_type.
2018-11-29 20:44:21 -08:00
Thomas Harte
64465f97b6
Starts towards reintroducing the proper mechanisms for selecting a display type at runtime.
2018-11-28 17:53:33 -08:00
Thomas Harte
5618288459
Reduces visible area, producing a tighter crop.
2018-11-25 22:32:12 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
770d7e90e9
Removes stale sampling functions.
2018-11-22 22:47:29 -05:00
Thomas Harte
b9aca39eb0
Reintroduces Vic-20 output.
...
Resolving errors in shader generation while I'm here.
2018-11-22 22:43:42 -05:00
Thomas Harte
c5d9bf2c12
Optimises slightly for black borders.
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Specifically to help to debug proper display of unused lines in the new scan target.
2018-11-17 18:23:42 -05:00
Thomas Harte
15b1176841
Ensures no border output if space is not allocated.
2018-11-14 22:32:33 -05:00
Thomas Harte
9dff13cbbf
Re-establishes output from the machines with 9918s and derivatives.
2018-11-14 22:25:19 -05:00
Thomas Harte
6d277fecd5
Makes ScanTarget a little more communicative and orthogonal.
2018-11-10 19:52:57 -05:00
Thomas Harte
f6562de325
Possibly adds enough for the Electron and ZX80 to start outputting dummy lines.
...
Let's see!
2018-11-03 23:40:39 -04:00
Thomas Harte
b40211d2c0
Starts to bend 'CRTMachine' to a world farther from owning the GPU relationship.
2018-11-03 21:54:25 -04:00
Thomas Harte
da4d883321
Adds first, incomplete attempts to talk to a ScanTarget from the CRT.
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Does away with the hassle of `unsigned` while I'm here; that was a schoolboy error.
2018-11-03 19:58:44 -04:00
Thomas Harte
f65d80b7d1
Ensures offset and flags are initialised to 0.
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This prevents a potential crash at startup.
2018-10-29 22:09:32 -04:00
Thomas Harte
8652d8b23d
(Mostly) randomises the 9918 start position.
2018-10-26 21:02:56 -04:00
Thomas Harte
e02aa885d8
Testing against the ColecoVision suggests this is probably always 7.
2018-10-26 20:59:12 -04:00
Thomas Harte
bb09762029
Introduces extra delays to VRAM access.
2018-10-26 20:19:08 -04:00
Thomas Harte
05a5c7120e
Shunts CRAM dots into their proper place.
2018-10-26 20:06:51 -04:00
Thomas Harte
521d603902
Adds a first attempt at CRAM dot output. With a TODO.
2018-10-26 19:26:46 -04:00
Thomas Harte
916710353a
Makes it explicit that I want the reference.
2018-10-25 23:18:34 -04:00
Thomas Harte
53b00dea3f
Adds missing include.
2018-10-25 23:12:41 -04:00
Thomas Harte
0587b9f257
Edges to within millimetres of CRAM dots.
...
... but all the way up to bedtime.
2018-10-25 23:12:03 -04:00
Thomas Harte
5accd8cf08
Fixes broken implementation of 9918 multicolour mode.
2018-10-24 22:40:38 -04:00
Thomas Harte
a8645f80bf
Introduces 'non-exclusive' emulator-space keyboards.
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i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
2018-10-24 21:59:30 -04:00
Thomas Harte
d61c3a9442
Fixes sprite list termination in 224- and 240-line modes.
2018-10-24 19:53:46 -04:00
Thomas Harte
2cdeaa2575
Moves misplaced bracket.
2018-10-23 22:37:19 -04:00
Thomas Harte
286783e880
Accepts GCC's suggestion of extra clarity brackets.
2018-10-23 22:36:23 -04:00
Thomas Harte
00e7958a97
Separates request for an SMS2 VDP from current graphics mode.
...
Thereby fixes various minor segments of Codemasters games.
2018-10-23 22:19:45 -04:00
Thomas Harte
2f995eb622
Adjusts vertical timing for display height.
2018-10-23 21:20:44 -04:00
Thomas Harte
90fbad0f1c
Implements SMS2-style addressing if in a 224 or 240-line mode.
...
This isn't quite accurate, but it'll do for development.
2018-10-23 20:30:08 -04:00
Thomas Harte
2cbd28478d
Allows the sprite terminator to be specified.
2018-10-23 20:01:47 -04:00
Thomas Harte
7855145ebd
Slightly adjusts pixel output time.
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i.e. respective to reading; sprite collision times now seem correct.
2018-10-22 19:58:33 -04:00
Thomas Harte
883680731a
Uses explicit state to determine whether a pixel target has been requested.
2018-10-21 21:18:41 -04:00
Thomas Harte
c07f9fed99
Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
2018-10-21 18:42:49 -04:00
Thomas Harte
16f08eb654
Slightly tweaks Master System timing numbers.
2018-10-21 13:58:34 -04:00
Thomas Harte
30b99f0049
Fixes a couple of interrupt prediction errors.
2018-10-20 18:25:28 -04:00
Thomas Harte
b61de65b43
Restores proper phase with the CPU.
2018-10-19 23:18:16 -04:00
Thomas Harte
0822c96ce0
Implements the proper row counter values for > 192 row modes.
2018-10-19 22:37:56 -04:00
Thomas Harte
f9a6c00493
Makes first attempt to support PAL timings.
2018-10-19 21:36:13 -04:00
Thomas Harte
4cd65eab5c
Seeks to avoid bad macro expansion.
2018-10-18 22:36:25 -04:00
Thomas Harte
9bc09046c0
Attempts to ensure that sprites can go off the top of the screen.
2018-10-18 21:48:57 -04:00
Thomas Harte
512f085891
Ensures proper left clipping of sprites.
2018-10-18 21:14:16 -04:00
Thomas Harte
da00c832f5
Corrects colour fetching for multicolour text mode.
2018-10-18 20:38:00 -04:00
Thomas Harte
8ff265c3a1
Corrects multicolour text mode.
2018-10-18 20:25:42 -04:00
Thomas Harte
1fc88c4eff
Corrects off-by-one error in line fetching coroutines.
2018-10-16 21:36:31 -04:00
Thomas Harte
58ca74c68a
Resolves right-side TMS sprite droppages.
2018-10-16 21:25:08 -04:00
Thomas Harte
b4f871a2ef
Corrects first line sprite row selection.
2018-10-16 21:16:29 -04:00
Thomas Harte
0f7bf6d6c6
Resolves attempt to output graphics on the line one before the display.
2018-10-16 21:02:31 -04:00
Thomas Harte
5dfe7d8596
Corrects most of TMS sprite drawing.
2018-10-16 20:49:04 -04:00
Thomas Harte
231009b901
Makes faulty attempt to reintroduce TMS-mode sprites.
2018-10-16 20:00:06 -04:00
Thomas Harte
1c5f939aea
Reintroduces tiles and some element of sprites in regular TMS mode.
2018-10-14 21:52:13 -04:00
Thomas Harte
c1e6406fc9
Corrects sprite accumulation.
2018-10-14 19:56:09 -04:00
Thomas Harte
d66979c68f
Switched to a very large number of buffers, and resolved stupid attempt to reassign a reference.
2018-10-14 18:19:11 -04:00
Thomas Harte
6c09abc6cb
Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer.
...
Specifically because closer inspection of the TMS modes shows it isn't quite valid to model output of one line as having fully completed prior to fetching of the next. So some sort of extra buffer is required. At which point it is most natural to continue with the logic that each fetch routine is oriented around the fetching process for a single line, and each output routine has the same view, suggesting separate read/write addresses.
Something is wrong though, as video data is being output too rapidly (I think) and with occasional sync issues (again: subject to investigation).
2018-10-14 16:23:45 -04:00
