Thomas Harte
c7c12f9638
After a quick check, eori_andi_ori also now passes.
2022-05-20 14:47:11 -04:00
Thomas Harte
ee942c5c17
Fix PC-relative fetches.
2022-05-20 14:42:51 -04:00
Thomas Harte
d157819c49
Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch.
...
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
2022-05-20 14:29:14 -04:00
Thomas Harte
2d91fb5441
Implement MOVEP.
2022-05-20 14:22:32 -04:00
Thomas Harte
81431a5453
Attempt BTST, BCHG, BCLR and BSET.
2022-05-20 12:58:45 -04:00
Thomas Harte
6d7ec07216
Uncover another three already-working test files.
2022-05-20 12:44:57 -04:00
Thomas Harte
b4978d1452
Implement BSR, adding one more test file to the working set.
2022-05-20 12:40:35 -04:00
Thomas Harte
cb77519af8
Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.
2022-05-20 12:40:09 -04:00
Thomas Harte
45e9648b8c
Implement Bcc.
2022-05-20 12:04:43 -04:00
Thomas Harte
ce32957d9d
Shuffle two more into the working column.
2022-05-20 11:53:12 -04:00
Thomas Harte
ba8592ceae
At least on the 68000, Scc is read-modify-write.
2022-05-20 11:43:26 -04:00
Thomas Harte
4327af3760
DBcc: add write-back.
2022-05-20 11:37:18 -04:00
Thomas Harte
860cc63e21
Attempt DBcc.
2022-05-20 11:32:06 -04:00
Thomas Harte
452dd3ccfd
Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
2022-05-20 11:20:23 -04:00
Thomas Harte
e5c1621382
Add missing fallthrough, patterns for all ADDs and SUBs.
2022-05-20 07:02:02 -04:00
Thomas Harte
af3518dc1f
Implement various ADD, SUB patterns.
2022-05-19 20:50:37 -04:00
Thomas Harte
6cfc0e80d9
Don't test the unrecognised instruction exception.
2022-05-19 19:45:38 -04:00
Thomas Harte
1ee9c585ca
Fix segue into second operand.
2022-05-19 19:38:42 -04:00
Thomas Harte
efe5a5ac26
Signal will_perform even for invalid instructions.
2022-05-19 18:50:43 -04:00
Thomas Harte
334e3ec529
Add privilege and instruction error exceptions; permit two operands to be stored.
2022-05-19 16:55:16 -04:00
Thomas Harte
84c165459f
ext.json now passes.
2022-05-19 16:32:40 -04:00
Thomas Harte
282c4121d6
CLR also follows the NEGX/NEG/NOT pattern.
2022-05-19 16:30:08 -04:00
Thomas Harte
6c2eee0e44
Implement CHK, and therefore the standard exception pattern.
2022-05-19 16:27:39 -04:00
Thomas Harte
eeb6a088b8
Add a tag to avoid duplication.
2022-05-19 15:49:42 -04:00
Thomas Harte
22b63fe1f8
Add EXT, and notes to self.
2022-05-19 15:41:02 -04:00
Thomas Harte
7ef526e2d3
Fix destination decrement.
2022-05-19 15:22:59 -04:00
Thomas Harte
ce7f94559b
Add EXG, ABCD, SBCD.
2022-05-19 15:19:00 -04:00
Thomas Harte
0471decfc8
Implement the complete set of fetch addressing modes.
...
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
2022-05-19 15:03:22 -04:00
Thomas Harte
e4c0a89889
Just use the four-bit register number directly.
2022-05-19 15:01:09 -04:00
Thomas Harte
084d6ca11d
Simplify address handling; add perform patterns for CMP, AND, OR, EOR.
2022-05-19 12:18:47 -04:00
Thomas Harte
274902c3c1
Add to-memory write-back. Am going to reconsider usage of temporary_address_ as noted.
2022-05-19 11:23:26 -04:00
Thomas Harte
f46e7c65c5
Add AddressRegisterIndirect fetches.
2022-05-19 10:47:57 -04:00
Thomas Harte
c6c6213460
Bifurcate the fetch-operand flow.
...
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
2022-05-19 10:27:51 -04:00
Thomas Harte
29f6b02c04
Factor out register setup/testing, generalising the DIVU/DIVS flag check.
2022-05-18 21:13:34 -04:00
Thomas Harte
1bf7c0ae5f
Attempt better to avoid entering a second instruction.
2022-05-18 21:00:34 -04:00
Thomas Harte
1b87626b82
Move some way towards MOVE.
2022-05-18 21:00:10 -04:00
Thomas Harte
44ae084794
Avoid the repeated .fill; reduces debug-build executor test time to 1.5s.
...
i.e. eliminates about 95% of costs.
2022-05-18 17:10:23 -04:00
Thomas Harte
13a1809101
Avoid memset.
2022-05-18 17:00:35 -04:00
Thomas Harte
c35200fbd0
Shuffle mildly, primarily to avoid repeated 16mb allocations.
2022-05-18 16:59:37 -04:00
Thomas Harte
da9fb216b1
Remove setup_operation in favour of doing the equivalent inline.
...
... as it'll probably allow me a route to `goto` straight out of there, too. At least, if I can find a sufficiently neat macro formulation.
2022-05-18 16:45:40 -04:00
Thomas Harte
bef12f3d65
Move ExecutionState into Implementation.hpp; use goto to avoid some double switches.
...
Re: the latter, yuck. Yuck yuck yuck. But it does mean I can stop going back and forth on how to structure conditionality on effective address generation segueing into fetches without doubling up on tests.
2022-05-18 15:35:38 -04:00
Thomas Harte
aa9e7eb7a2
Codify MOVE's status somewhat, avoid reading write-only operands.
2022-05-17 16:57:33 -04:00
Thomas Harte
f3d3e588fd
Add enough of state to [sort-of] pass the first test.
...
i.e. until the processor overruns, as it is permitted to do, and can't handle the second instruction.
2022-05-17 16:51:26 -04:00
Thomas Harte
4a40581deb
Completes performance of NBCD D0.
2022-05-17 16:10:20 -04:00
Thomas Harte
eed2672db5
Add documentation, honour signal_will_perform.
2022-05-17 15:05:11 -04:00
Thomas Harte
84071ac6d0
Implement reset logic, advance as far as actually performing an NBCD on D0 (but not writing it back).
2022-05-17 14:51:49 -04:00
Thomas Harte
1a27eea46c
Establish general pattern for selecting a performance phase and obtaining operands.
2022-05-17 14:08:50 -04:00
Thomas Harte
d0b6451f02
Step gingerly on to fetching operands.
2022-05-17 08:26:35 -04:00
Thomas Harte
2147c5a5f2
Fill in missing #undefs.
2022-05-16 21:02:25 -04:00
Thomas Harte
c7aa4d8b6d
Fix state transitions.
...
Confirmed that the 68000 mk 2 now appears correctly to perform a reset.
2022-05-16 21:00:25 -04:00
