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Author	SHA1	Message	Date
Thomas Harte	c8ede400eb	Fix RTE.	2022-05-22 21:17:28 -04:00
Thomas Harte	269263eecf	Implement RTE, RTS, RTR.	2022-05-22 21:16:38 -04:00
Thomas Harte	4e21cdfc63	Enable NEGX/CLR tests.	2022-05-22 20:55:21 -04:00
Thomas Harte	faef5633f8	Ensure MOVE from SR has an effective address to write to.	2022-05-22 20:52:00 -04:00
Thomas Harte	7d1f1a3175	Implement MOVE [to/from] [CCR/SR].	2022-05-22 19:45:22 -04:00
Thomas Harte	4e34727195	Fully implement TAS.	2022-05-22 16:14:03 -04:00
Thomas Harte	1dd6ed6ae3	Implement TAS Dn, with detour for other TASes.	2022-05-22 16:08:30 -04:00
Thomas Harte	cb4d6710df	Switch to a more direct indication of progress.	2022-05-22 11:27:58 -04:00
Thomas Harte	3b68b9a83b	Implement PEA.	2022-05-22 11:27:38 -04:00
Thomas Harte	4279ce87ea	Implement LEA.	2022-05-22 08:29:12 -04:00
Thomas Harte	3c1c4f89e9	Add MULU/S functionality, though not timing.	2022-05-22 08:02:32 -04:00
Thomas Harte	4a6512f5d5	Reduce dispatch boilerplate.	2022-05-22 07:39:16 -04:00
Thomas Harte	284f23c6ea	Implement JMP.	2022-05-22 07:16:38 -04:00
Thomas Harte	11a9a5c126	Use common macros for the two forms of Perform.	2022-05-22 07:08:14 -04:00
Thomas Harte	4993801741	Add missing prefetch to BSET, BCHG, BCLR.	2022-05-21 21:05:05 -04:00
Thomas Harte	4b35899a12	Bcc: properly establish offset.	2022-05-21 20:59:34 -04:00
Thomas Harte	1304e930eb	DBcc is two-operand.	2022-05-21 20:06:03 -04:00
Thomas Harte	94288d5a94	Excludes DBcc from standard operand fetch.	2022-05-21 19:53:28 -04:00
Thomas Harte	3811ab1b82	Fix the two 8bit-with-displacement effective address Calc steps.	2022-05-21 16:20:01 -04:00
Thomas Harte	c869eb1eec	Correct omission: wasn't testing the final PC. ... Plenty of new errors incoming.	2022-05-21 15:56:27 -04:00
Thomas Harte	f97d2a0eb9	Add DIVU/DIVS, at least as far as getting the correct numeric result.	2022-05-21 15:56:09 -04:00
Thomas Harte	176c8355cb	The tests in chk.json now pass.	2022-05-21 14:32:58 -04:00
Thomas Harte	2258434326	Ensure proper return addresses are calculated for JSR.	2022-05-21 14:28:44 -04:00
Thomas Harte	e46a3c4046	Implement JSR.	2022-05-21 10:29:36 -04:00
Thomas Harte	0e4cfde657	Fix MOVEM predec.	2022-05-21 08:17:39 -04:00
Thomas Harte	4bd9c36922	Fix postincrement mode.	2022-05-20 21:01:23 -04:00
Thomas Harte	256da43fe5	Fix MOVEM other than postinc and predec.	2022-05-20 20:47:54 -04:00
Thomas Harte	6a442e0136	MOVEM has an immediate first operand.	2022-05-20 20:34:51 -04:00
Thomas Harte	a818650027	Add a faulty attempt at MOVEM.	2022-05-20 18:48:19 -04:00
Thomas Harte	9d79e64f5c	Add a mere calculate effective address pathway. ... Plus a lot of waffle to try to justify the further code duplication.	2022-05-20 16:23:52 -04:00
Thomas Harte	c7c12f9638	After a quick check, eori_andi_ori also now passes.	2022-05-20 14:47:11 -04:00
Thomas Harte	ee942c5c17	Fix PC-relative fetches.	2022-05-20 14:42:51 -04:00
Thomas Harte	d157819c49	Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch. ... (which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)	2022-05-20 14:29:14 -04:00
Thomas Harte	2d91fb5441	Implement MOVEP.	2022-05-20 14:22:32 -04:00
Thomas Harte	81431a5453	Attempt BTST, BCHG, BCLR and BSET.	2022-05-20 12:58:45 -04:00
Thomas Harte	6d7ec07216	Uncover another three already-working test files.	2022-05-20 12:44:57 -04:00
Thomas Harte	b4978d1452	Implement BSR, adding one more test file to the working set.	2022-05-20 12:40:35 -04:00
Thomas Harte	cb77519af8	Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.	2022-05-20 12:40:09 -04:00
Thomas Harte	45e9648b8c	Implement Bcc.	2022-05-20 12:04:43 -04:00
Thomas Harte	ce32957d9d	Shuffle two more into the working column.	2022-05-20 11:53:12 -04:00
Thomas Harte	ba8592ceae	At least on the 68000, Scc is read-modify-write.	2022-05-20 11:43:26 -04:00
Thomas Harte	4327af3760	DBcc: add write-back.	2022-05-20 11:37:18 -04:00
Thomas Harte	860cc63e21	Attempt DBcc.	2022-05-20 11:32:06 -04:00
Thomas Harte	452dd3ccfd	Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.	2022-05-20 11:20:23 -04:00
Thomas Harte	e5c1621382	Add missing fallthrough, patterns for all ADDs and SUBs.	2022-05-20 07:02:02 -04:00
Thomas Harte	af3518dc1f	Implement various ADD, SUB patterns.	2022-05-19 20:50:37 -04:00
Thomas Harte	6cfc0e80d9	Don't test the unrecognised instruction exception.	2022-05-19 19:45:38 -04:00
Thomas Harte	1ee9c585ca	Fix segue into second operand.	2022-05-19 19:38:42 -04:00
Thomas Harte	efe5a5ac26	Signal will_perform even for invalid instructions.	2022-05-19 18:50:43 -04:00
Thomas Harte	334e3ec529	Add privilege and instruction error exceptions; permit two operands to be stored.	2022-05-19 16:55:16 -04:00