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877 Commits

Author SHA1 Message Date
Thomas Harte
a3e0024980 Chopped time accumulation out of the default Tape process because it's proving to be sufficiently expensive for a TZX as not to be worthwhile. Introduced a cheaper position capturing/restoring method. 2017-07-21 18:55:03 -04:00
Thomas Harte
44e5a03cf2 Removed just-don't-power-the-tape approach to pausing and playing, in favour of being fully communicative. 2017-07-19 19:21:27 -04:00
Thomas Harte
b3861ff755 Reduced copying of Pulses. 2017-07-16 19:49:31 -04:00
Thomas Harte
1d3ae31755 Abstracted the concept of an Acorn shifter away from being a PLLParser. The Acorn tape parser now skips using that class and uses the shifter. The actual Electron also uses the shifter. So the two are completely aligned. Net result: the Electron should successfully load exactly when static analysis was successful. 2017-07-16 19:24:01 -04:00
Thomas Harte
f931cd582d Switched to use of std::vector in those few remaining places where I was still using a unique_ptr to a native type and newing for myself. So, some of my earliest bits of code. 2017-07-16 13:54:07 -04:00
Thomas Harte
481487f084 Oh yuck, it looks like I've repeated this same test in two different places. Must figure out where to factor it out to. But in the meantime, the emulated Electron has just loaded its first CSW. 2017-07-13 22:39:30 -04:00
Thomas Harte
ac59dd8b1d Added enough typing to issue a load command. No thoughts as to running yet though. 2017-07-09 22:07:12 -04:00
Thomas Harte
353c854734 Removed a TODO that is no longer appropriate. 2017-07-09 22:06:50 -04:00
Thomas Harte
3e5c209039 Added basic Typer support for the ZX80 and '81. 2017-07-09 22:00:34 -04:00
Thomas Harte
ed28260aaf Hardens the ZX80/81 video routines to ensure they never try to push data into the future and don't double-count time when pixels would ostensibly run into sync. You could previously see the CRT being handed negative run lengths if sync interrupted pixels or if a run of more than 320 pixels (my arbitrary buffer size) occurred, with corresponding poor behaviour given my use of unsigned numbers. 2017-07-09 19:33:05 -04:00
Thomas Harte
87658e83c1 Moved line counter reset logic; I think this is actually correct. 2017-07-09 00:05:30 -04:00
Thomas Harte
4509c3ce34 By observation, it appears that disabling vsync occurs on any port output whatsoever, as long as NMI isn't blocking it. 2017-07-08 21:01:52 -04:00
Thomas Harte
30e93979d2 Removed data work if sync is enabled; in that case no data is output. 2017-07-08 21:01:07 -04:00
Thomas Harte
d6b87053bf Introduced an explicit record of whether a video byte is latched. It's definitely incorrect to treat the latching of 0 as equivalent to no latching, as the byte that will eventually become video is not strongly implied. 2017-07-08 20:40:19 -04:00
Thomas Harte
22389a5d2d Merge branch 'master' into HiRes 2017-07-08 20:38:25 -04:00
Thomas Harte
54efcb7e2f Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults. 2017-07-08 19:31:20 -04:00
Thomas Harte
e2575d6de4 Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly. 2017-07-08 19:21:12 -04:00
Thomas Harte
46fff8e8a2 Ensured bit 8 is uniquely from the latched video byte, not an OR of that with the refresh address. 2017-07-06 22:48:48 -04:00
Thomas Harte
a3684545b5 Added a block on the tape motor for a short period after each time the ROM routine is intercepted for a substituted byte read. To reduce the collision between fast tape and real tape loading. 2017-07-06 22:33:54 -04:00
Thomas Harte
b842c5b8bb Merge branch 'master' into ZX81FastLoading 2017-07-06 22:03:24 -04:00
Thomas Harte
0c037627fc Typer fixes: the recipient no longer releases the caller, and a duplicate call to strlen and piece of arithmetic is corrected. 2017-07-06 21:38:56 -04:00
Thomas Harte
a72a2e0a1a Ensured tape doesn't proceed of its own volition when in fast-loading mode. 2017-06-23 20:21:37 -04:00
Thomas Harte
50375fb373 Ensured tape position is unaffected if the attempt at loading quickly fails. 2017-06-23 20:18:19 -04:00
Thomas Harte
cb105fdeb4 Took a first stab at high-res support. 2017-06-22 22:48:17 -04:00
Thomas Harte
acfd4dde36 Reduced port writes which can adjust programmatic sync, and prevented anything while NMI generation is active. Moved line counter increment from triggered by interrupt acknowledge to triggered by horizontal sync. In both cases, cribbing from my own earlier work. Initial results suggest that sync issues are resolved in third-party software. 2017-06-22 22:44:06 -04:00
Thomas Harte
644ef13acd Connected up the fast-tape GUI option for the ZX80 and '81. 2017-06-22 20:20:31 -04:00
Thomas Harte
b7c978e078 Added getters for most of the input lines, and attempted to round out the ZX81's wait logic. 2017-06-22 20:11:19 -04:00
Thomas Harte
52d9ddf9e5 Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue. 2017-06-21 22:13:24 -04:00
Thomas Harte
a6810fc3ef Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards. 2017-06-21 21:44:42 -04:00
Thomas Harte
15f6c51062 Added the most trivial implementation of the ZX81 wait line. 2017-06-21 21:28:14 -04:00
Thomas Harte
e1355d4b62 Restored proper video output. 2017-06-21 21:18:09 -04:00
Thomas Harte
4bf13610ce Reinstated interrupts by moving the refresh test back into the refresh cycle. 2017-06-21 21:03:39 -04:00
Thomas Harte
0e0ce379b4 Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle. 2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505 Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line. 2017-06-21 20:32:08 -04:00
Thomas Harte
e1a2580b2a Renamed BusOperation to MachineCycle::Operation. 2017-06-17 21:53:45 -04:00
Thomas Harte
08a542a324 Reenabled the fast-loading hack. 2017-06-15 18:30:12 -04:00
Thomas Harte
9b3d05e05f Simplified decoding logic. 2017-06-14 22:24:44 -04:00
Thomas Harte
d8e3103a2b Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it. 2017-06-13 21:48:17 -04:00
Thomas Harte
76a64d13a0 Made a first attempt at ZX81 emulation. 2017-06-13 21:25:55 -04:00
Thomas Harte
1e975859c2 Started splitting ZX80 and ZX81 paths. Also the '80 fires its horizontal sync a little earlier than the '81, so pulled that back a little. 2017-06-13 20:09:09 -04:00
Thomas Harte
4c5261bfa0 Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now. 2017-06-12 22:28:30 -04:00
Thomas Harte
8b09b4180b This now at least remembers whether it is meant to be a ZX81 and has storage for a horizontal counter. 2017-06-12 21:33:16 -04:00
Thomas Harte
b9dbb6bcf8 Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate. 2017-06-12 18:55:04 -04:00
Thomas Harte
302c2e94de Corrected lingering hard-coded mask. So titles for memory configurations above 1kb now load. 2017-06-11 21:27:46 -04:00
Thomas Harte
06fe07932a While tidying up, killed an unused instance variable. 2017-06-11 21:21:26 -04:00
Thomas Harte
6913c7a018 This also can just use rom_mask_. 2017-06-11 19:29:20 -04:00
Thomas Harte
6b602c74b7 Made an attempt to support memory maps other than the unexpanded default of 1kb. 2017-06-11 19:29:02 -04:00
Thomas Harte
e40d553045 Bumped the tape parser up into the machine to ensure a maintained state. Temporarily disabled normally-timed tape playback. 2017-06-11 18:31:43 -04:00
Thomas Harte
e5b30cdfbb Attempted to ensure appropriate resumption of processing after quick-reading a tape byte. 2017-06-11 17:28:47 -04:00
Thomas Harte
ba5f34f827 Narrowed view to the centre 80% of a frame. 2017-06-11 17:24:32 -04:00
Thomas Harte
84d2feb2e6 Cleaned up and implemented fast-tape hack. I've decided it'd be better to test some other software, potentially to give multiple issues to think about, rather than sitting around with just the one. 2017-06-11 16:42:49 -04:00
Thomas Harte
d910a4fd38 Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207. 
Also: lots of printfs have grown temporarily as I try to figure out what I'm doing so wrong as to break loading.
 2017-06-11 13:32:20 -04:00
Thomas Harte
5626d35bc4 Tried flipping the bit meaning; decided at least to leave it in full-byte form. 2017-06-06 18:38:05 -04:00
Thomas Harte
63e0802f4e Ensured tape input appears on the returned value. 2017-06-06 18:16:27 -04:00
Thomas Harte
e3ee9604a5 Added comments. 2017-06-06 18:01:33 -04:00
Thomas Harte
8c66e1d99d Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data. 2017-06-06 17:53:23 -04:00
Thomas Harte
ca9e8aecd6 Made a seemingly unsuccessful attempt to add tape input. 2017-06-06 10:13:32 -04:00
Thomas Harte
cc4cb45e9d Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court. 2017-06-06 09:25:18 -04:00
Thomas Harte
ebbf6e6133 Surprisingly, I think this may actually be the correct output: stopped throwing away the I part of the refresh register and flipped black and white. 2017-06-06 09:03:09 -04:00
Thomas Harte
cba07dec7e Doubled up to display all eight pixels. To confirm that they are the wrong pixels. 2017-06-06 08:59:00 -04:00
Thomas Harte
6f7037b2b1 Made an initial stab at outputting half the correct pixels. 2017-06-06 08:55:07 -04:00
Thomas Harte
ef4b2f963d Probably more-or-less corrected. But this is all a bit too interdependent. 2017-06-05 23:52:56 -04:00
Thomas Harte
97f3ff03b6 Restored white background and attempted to correct output timing deficiencies. Incomplete success. 2017-06-05 23:50:04 -04:00
Thomas Harte
2fbc7a2869 Made a very basic attempt at getting something that at least demarcates proper graphics output. 2017-06-05 23:32:49 -04:00
Thomas Harte
4983718df7 Got to outputting something to the CRT. Should be just proper syncs and a paper background. It's not synchronising properly, so something is amiss in my timing. 2017-06-05 10:47:42 -04:00
Thomas Harte
23ca00fd9a Added memory fuzzing as a way to verify state being written by the Z80. Eventually discovered the HALT problem as fixed in the last commit, so have stripped away the caveman stuff again. 2017-06-05 10:36:07 -04:00
Thomas Harte
893f61b490 Attempted specifically to reproduce the 1kb ZX80 memory map in the hope of getting compact lines and in case mirroring is why I'm getting completely empty video reads. Still no action. 2017-06-05 09:38:49 -04:00
Thomas Harte
7e3a46c33e [Re]discovered that sync may also be a product of the interrupt cycle. So started looking into that. 2017-06-04 21:54:55 -04:00
Thomas Harte
73654d51dd Wired up actually to run. 2017-06-04 18:37:13 -04:00
Thomas Harte
096551ab3e Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see. 2017-06-04 18:32:23 -04:00
Thomas Harte
c485c460f7 Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world. 2017-06-04 18:08:35 -04:00
Thomas Harte
d2637123c4 Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software. 2017-06-04 17:55:19 -04:00
Thomas Harte
2562306802 Merge branch 'master' into Z80 2017-05-16 21:05:00 -04:00
Thomas Harte
2ee8a7056e Corrected TIA no longer to assume phase is an automatic quarter askew. 2017-05-16 20:43:28 -04:00
Thomas Harte
a5075d9eb5 Formalised the reasoning behind the colour phase fix-up and made it an opt-in per-caller value. Only the Oric currently needs to opt in. 2017-05-16 20:31:39 -04:00
Thomas Harte
eb8a2de5d6 Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80. 2017-05-15 07:38:59 -04:00
Thomas Harte
0808e9b6fb Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair. 2017-05-14 22:08:15 -04:00
Thomas Harte
8e35e913bb Formally withdrew the 'load automatically' option for the Vic, having removed that option elsewhere. 2017-05-14 16:59:24 -04:00
Thomas Harte
5d91a2600d Permitted ROM-style PRGs that are not a power-of-two in size, and added extra safety checks on loading data from a tape. 2017-05-08 22:15:35 -04:00
Thomas Harte
cb66c7e2dc Performed some minor tidying. 2017-05-08 21:05:35 -04:00
Thomas Harte
61f8f2f18c Switched to a more straightforward way of exiting from tape data loading. 2017-05-08 20:58:55 -04:00
Thomas Harte
7b43ae0a92 Implemented a catch for loading the data portion of files. 2017-05-07 22:22:59 -04:00
Thomas Harte
2807e3134f Implemented speedy header finding. So that's half of it. 2017-05-07 20:32:48 -04:00
Thomas Harte
0771363f3b Removed one piece of unnecessary logging. 2017-05-06 22:22:03 -04:00
Thomas Harte
2edf73908c Temporarily disabled the existing fast loading implementation in pursuit of another, and started trying to correct the lack of connection between the userport VIA and the tape drive. 2017-05-06 22:00:12 -04:00
Thomas Harte
ed6b135015 Made final switch to permit high-sampling rate Atari audio. 2017-04-15 21:18:00 -04:00
Thomas Harte
f95015c7f6 Pulled out the divisor for audio. 2017-04-03 21:16:39 -04:00
Thomas Harte
814c0ada13 Fixed action counts for border motion. 2017-03-26 18:33:05 -04:00
Thomas Harte
dfc468f220 Locked down all initial state. 2017-03-26 15:47:04 -04:00
Thomas Harte
e01f3f06c8 Completed curly bracket movement. 2017-03-26 14:34:47 -04:00
Thomas Harte
3229502fa1 Standardised curly bracket placement across the Atari. 2017-03-23 21:59:16 -04:00
Thomas Harte
a26b87f348 Fixed: mistake was failure to count ready cycles. 2017-03-20 20:44:03 -04:00
Thomas Harte
4c3cc42c91 This gives a very noisy version of the real audio. 2017-03-20 20:38:29 -04:00
Thomas Harte
f3f4e1a541 Made a first, hacky, attempt at audio. 2017-03-20 19:35:51 -04:00
Thomas Harte
4722f6b5c4 Fixed sprite disappearance: test should be applied predecrement, not post — it relates to the address being used this access, not the next one. 2017-03-19 18:58:35 -04:00
Thomas Harte
7d8d1c7828 Fixed 'random' number generator. 2017-03-19 18:54:35 -04:00
Thomas Harte
4bb70e7d31 Resetting the mask upon low byte write appears to resolve some issues. 2017-03-19 18:49:37 -04:00
Thomas Harte
321030bb44 Added a slightly faulty but seemingly 'close' version of masking. 2017-03-19 18:28:06 -04:00
Thomas Harte
6c161b1150 This gives something that might be the correct background. 2017-03-19 17:49:48 -04:00
Thomas Harte
d5c37c8619 Shushed a little, so as to be able to see a reasonable amount of output during my lifetime. 2017-03-19 17:38:54 -04:00
Thomas Harte
7c66c36d3f Attempted at least to manage appropriate data storage. 2017-03-19 17:31:08 -04:00
Thomas Harte
031a68000a Added a class to contain the Pitfall 2 pager and a skeleton of initial work. 2017-03-18 22:08:47 -04:00
Thomas Harte
c3d82f88a5 Tidied up and commented on the Activision stack implementation. 2017-03-18 21:01:58 -04:00
Thomas Harte
c033bad0b9 Here's MNetwork! 2017-03-18 20:51:49 -04:00
Thomas Harte
c31d85f820 Re-emplaced the MegaBoy. Also cut detritus from the main Atari header. 2017-03-18 19:02:34 -04:00
Thomas Harte
217fbf257e CBS RAM Plus returns. 2017-03-18 18:56:20 -04:00
Thomas Harte
0b611a14b9 Tigervision paging returns. 2017-03-18 18:50:13 -04:00
Thomas Harte
df6861c9dc Parker Bros paging is back. 2017-03-18 18:21:01 -04:00
Thomas Harte
a4cd12394e Reinstated the Activision stack pager. 2017-03-18 18:03:48 -04:00
Thomas Harte
e0bca1e37b Reinstated the 16 and 32 kb Atari pagers, and ensured the 6532 always starts in a valid state. 2017-03-18 17:34:34 -04:00
Thomas Harte
55ce851bb2 Fixed types of the 8k cartridges, ensured the 6502 starts without an IRQ request history. 2017-03-18 17:04:01 -04:00
Thomas Harte
e8d34f2eb4 Having farmed out the bus, the Atari itself no longer is/owns a 6502. 2017-03-18 16:34:41 -04:00
Thomas Harte
bb3daaa99b Sought to reintroduce the Atari 8k paging scheme, at the same time deciding to do away with the copy and paste of holding on to ROM data. 2017-03-18 15:04:01 -04:00
Thomas Harte
36b58d03b7 Formalised read bus value guarantee from the 6502, fixed missing clock signal wiring on the Atari cartridge class, reintroduced CommaVid support. 2017-03-18 14:46:46 -04:00
Thomas Harte
7958459db9 In theory unpaged cartridges should now work. Time to debug. 2017-03-18 14:01:04 -04:00
Thomas Harte
14a76af0d3 Started trying to float out bus control to cartridges. 2017-03-17 20:28:07 -04:00
Thomas Harte
afbd9fd41b Fixed declared line length. 2017-03-14 21:33:38 -04:00
Thomas Harte
7302703039 Implemented the Activision stack paging scheme. 2017-03-14 20:24:05 -04:00
Thomas Harte
97a8a96593 Rejigged how the memory map is handled and implemented MNetwork support. 2017-03-14 20:07:54 -04:00
Thomas Harte
3b29276228 Implemented the MegaBoy paging scheme. 2017-03-14 17:40:01 -04:00
Thomas Harte
b3632a4e86 Institutes CBS RAM Plus emulation. 2017-03-14 17:25:10 -04:00
Thomas Harte
f0d944847b Fixed setting of the second 1kb. 2017-03-11 18:16:29 -05:00
Thomas Harte
add14fb43a Made an attempt to implement Tigervision paging. 2017-03-11 17:44:35 -05:00
Thomas Harte
33bda2d40c Switched to image inspection for RAM guesses rather than disassembly. Which fixes the other Parker Bros titles. 2017-03-11 13:04:23 -05:00
Thomas Harte
2b5e3a600e Made a first attempt at implementing the Parker Bros pager within the emulation. 2017-03-11 12:43:12 -05:00
Thomas Harte
9c72ce5bd2 Ensured a settling delay is permitted before an NTSC/PAL decision is made. To avoid false switches just due to startup. 2017-03-06 19:37:35 -05:00
Thomas Harte
79784a8e57 Followed tip: missiles are locked to the position after four output pixels, not four input pixels. 2017-03-04 22:23:50 -05:00
Thomas Harte
4751615623 Fixed NTSC colour cycle count, and hence the 2600's reported line lengths and phase offset. 2017-03-04 17:31:39 -05:00
Thomas Harte
d3257c345a Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place. 2017-03-04 17:00:28 -05:00
Thomas Harte
837cccdf83 Switched to deferred updates for the 6532. 2017-03-04 14:58:28 -05:00
Thomas Harte
93d1573481 Added a fix for certain homebrews. 2017-03-01 07:59:25 -05:00
Thomas Harte
893a5dd007 Added an artificial low pass filter, attempting to capture post-digital effects. 2017-02-28 21:29:55 -05:00
Thomas Harte
06dd98b23c Pulled the reset time for horizontal blank extend up to position 224. 2017-02-28 20:28:54 -05:00
Thomas Harte
184c8ae707 Extended to emulate the CommaVid. 2017-02-27 20:50:59 -05:00
Thomas Harte
9d7985c1e1 Added Super Chip emulation. 2017-02-26 17:47:29 -05:00
Thomas Harte
e6a84fd26b Attempted a hardware-correct implementation of missile-to-player latching. This completes the last of the **knowing** inaccuracies. The rest are as-of-yet unwitting. 2017-02-26 15:12:31 -05:00
Thomas Harte
440467ea3e Started communicating which copy is being requested. 2017-02-26 13:39:25 -05:00
Thomas Harte
98376de9ad Started returning 'no effect' for pot ports, rather than doing nothing. Still very much TODO though. 2017-02-25 22:58:58 -05:00
Thomas Harte
e61e355251 Moved to the maximum possibly required queue length of 4. Though the emulated 2600 should never need more than 2 slots as per the current calling pattern, it's not a contractual guarantee. 2017-02-25 17:25:10 -05:00
Thomas Harte
c898c8a99e Ensured the missiles and ball don't attempt to enqueue. Because I don't think they're supposed to. 2017-02-25 17:13:22 -05:00
Thomas Harte
8c9062857c Added a single-slot queue for player objects to defer drawing, thereby deferring pixel lookup. Which I think is correct. Though more slots might be needed. 2017-02-25 17:10:24 -05:00
Thomas Harte
77ed4ddc05 Slightly simplified ready line release logic. 2017-02-23 21:08:32 -05:00
Thomas Harte
82f392fada This should be the other way around. I want whichever is later. 2017-02-22 21:54:49 -05:00
Thomas Harte
8291a63d5f Fixed loss of audio when switching to PAL. 2017-02-22 21:15:37 -05:00
Thomas Harte
6120dae61a While I'm using the hacky approach to player/missile synchronisation, I need to seed adder. 2017-02-22 07:39:11 -05:00
Thomas Harte
4f5f191cd6 Fixed: will no longer attempt to output pixels from before the pixel part of a line on which sync was disabled abruptly. 2017-02-22 07:33:36 -05:00
Thomas Harte
21abf4e9fc Enshrined a terminology switch, albeit without any flow change behind it. 2017-02-22 07:29:48 -05:00
Thomas Harte
144d6b70d9 Minor cleaning. 2017-02-22 07:14:30 -05:00
Thomas Harte
b769f22ca0 Switched back to the collision_buffer_ being part of the TIA object, added one more assert. 2017-02-21 22:26:20 -05:00
Thomas Harte
7019d396d0 Threw in some asserts, discovering a bug in missile positioning. 2017-02-21 22:04:27 -05:00