Thomas Harte
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d83dd17738
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[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.
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2017-05-29 11:40:56 -04:00 |
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Thomas Harte
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c322410783
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Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
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2017-05-29 10:52:54 -04:00 |
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Thomas Harte
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b67331e018
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Fixing the OUT repetition group reduces the code to one failing test.
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2017-05-29 10:48:53 -04:00 |
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Thomas Harte
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a47b339668
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Made an attempt at OUT[I/D]R. 10 failures remaining. None of which, I guess, are due to unimplemented operations.
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2017-05-29 10:28:04 -04:00 |
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Thomas Harte
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ad56a9215c
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Implemented IN[I/D]x. 18 failures remaining.
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2017-05-29 10:12:33 -04:00 |
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Thomas Harte
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c56a5344b9
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Implemented CP[I/D]x.
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2017-05-29 08:54:00 -04:00 |
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Thomas Harte
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1f62cbe21a
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Reduced LD[I/D}{R} repetition.
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2017-05-29 08:24:10 -04:00 |
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Thomas Harte
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47845f8c19
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Tried to complete the LD[I/D]{R} group. 32 issues remain.
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2017-05-28 23:55:54 -04:00 |
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Thomas Harte
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409c82ce73
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Implemented RLD and RRD. 34 failures remaining.
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2017-05-28 16:46:27 -04:00 |
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Thomas Harte
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dc3f5b6211
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Fixed flag setting for LD A, I and LD A, R, and corrected typo affecting LD DE, (nn).
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2017-05-28 16:32:10 -04:00 |
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Thomas Harte
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fb02b77e63
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Implemented RETI/RETN. 40 warnings remaining.
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2017-05-28 16:07:25 -04:00 |
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Thomas Harte
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f974d54c7a
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Implemented IM. 48 failures remain.
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2017-05-28 15:55:21 -04:00 |
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Thomas Harte
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68978c6e25
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Implemented NEG and filled in the load/store and copy parts of the ED page that roll directly off the tongue. 53 issues outstanding.
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2017-05-28 15:47:48 -04:00 |
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Thomas Harte
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5a4d448cc1
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Corrected logical flags; now down to 68 failures, all of them on the ED page.
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2017-05-28 15:09:58 -04:00 |
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Thomas Harte
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743eac8c55
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Implemented EXX to complete the base page. 83 failures.
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2017-05-28 14:55:14 -04:00 |
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Thomas Harte
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6b66c8f304
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Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.
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2017-05-28 14:50:51 -04:00 |
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Thomas Harte
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c976fbfcd5
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Implemented the base-page IN and OUT instructions, bringing FUSE test failures down to 91.
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2017-05-28 14:20:05 -04:00 |
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Thomas Harte
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ed3e38ac31
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Performed some quick tidying.
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2017-05-28 00:12:42 -04:00 |
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Thomas Harte
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76f03900d2
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Implemented EX HL, (SP) so as, allowing for indexed pages, to bring issues below the psychological 100 barrier. To 99.
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2017-05-28 00:02:14 -04:00 |
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Thomas Harte
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9759a04c7d
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Timing fixes: the fetch-decode-execute pattern is now per-page, since that on [DD/FD]CB not only doesn't increment R but doesn't take four cycles, so is probably a normal read cycle. Adjusted timing all around.
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2017-05-27 23:54:06 -04:00 |
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Thomas Harte
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0d2d04e17b
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Seeking proper [F/D]DCB emulation: the offset comes before the final byte of opcode, and adding seems to overlap with the opcode fetch, which does not increment R. Also needs to duplicate the result to visible registers.
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2017-05-27 21:06:56 -04:00 |
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Thomas Harte
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98423c6e41
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Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
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2017-05-27 16:19:15 -04:00 |
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Thomas Harte
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33c3fa21e3
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Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
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2017-05-27 15:54:24 -04:00 |
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Thomas Harte
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2141d52794
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Corrected typo. Now at 696 failures.
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2017-05-27 15:41:26 -04:00 |
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Thomas Harte
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16b8021401
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Made a stab at the CB pages.
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2017-05-27 15:39:22 -04:00 |
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Thomas Harte
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151b09b5ca
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Fixed various other obvious cases for indexing.
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2017-05-26 23:37:17 -04:00 |
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Thomas Harte
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9bc2b48d9b
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Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
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2017-05-26 23:23:33 -04:00 |
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Thomas Harte
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ab8a98f1df
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Implemented RST.
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2017-05-26 07:29:19 -04:00 |
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Thomas Harte
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efe354a7b1
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Fixed half carry after logical operation.s
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2017-05-25 22:55:04 -04:00 |
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Thomas Harte
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d50d3fc837
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Implemented CPL, SCF and CCF.
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2017-05-25 22:51:08 -04:00 |
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Thomas Harte
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83ee92af1a
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Made DAA work sufficiently well for the FUSE test.
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2017-05-25 22:41:05 -04:00 |
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Thomas Harte
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ea0ad9fd87
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Took a shot at DAA, seemingly not to Fuse's liking though.
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2017-05-25 22:17:48 -04:00 |
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Thomas Harte
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ff3c60c0e1
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Implemented the conditional JRs.
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2017-05-25 21:51:30 -04:00 |
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Thomas Harte
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399703a471
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Implemented JR.
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2017-05-25 21:48:28 -04:00 |
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Thomas Harte
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82017c4aea
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Implemented DJNZ.
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2017-05-25 21:44:24 -04:00 |
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Thomas Harte
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bdf07c3dc9
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Implemented EX AF, AF'.
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2017-05-25 21:26:32 -04:00 |
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Thomas Harte
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598be24644
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Fixed overflow for 8-bit decrementing.
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2017-05-25 21:23:38 -04:00 |
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Thomas Harte
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c668ff9472
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Added incrementing of the refresh register.
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2017-05-25 21:01:52 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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c3ea6dc1f5
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Added respect for limiting to the requested number of cycles in the Z80.
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2017-05-22 19:15:55 -04:00 |
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Thomas Harte
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22afa509ca
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Got to a parsing and towards an attempt to run FUSE tests.
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2017-05-22 19:14:46 -04:00 |
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Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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c66c715ac9
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Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
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2017-05-21 19:26:40 -04:00 |
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Thomas Harte
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5dcfd85642
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Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
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2017-05-21 19:15:52 -04:00 |
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Thomas Harte
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c70dfe1b09
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Implemented the two variations of loading between (nn) and SP.
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2017-05-21 13:20:28 -04:00 |
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Thomas Harte
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232c591655
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Threw in a little macro documentation and a missing macro.
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2017-05-21 13:13:21 -04:00 |
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Thomas Harte
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790614b544
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Added EI and DI.
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2017-05-21 12:53:17 -04:00 |
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