Thomas Harte
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a282a51673
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Remove last of the direct printf'ing.
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2021-09-30 02:42:59 -04:00 |
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Thomas Harte
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b7b13e20d1
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Single column blits should use both masks.
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2021-09-29 22:49:35 -04:00 |
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Thomas Harte
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402fa41bc0
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Corrects initial error value.
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2021-09-29 22:19:17 -04:00 |
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Thomas Harte
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0b9ebafc0f
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Flip bit deserialisation order.
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2021-09-28 22:12:13 -04:00 |
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Thomas Harte
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140e24ef15
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Grab further copy flags.
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2021-09-28 22:11:58 -04:00 |
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Thomas Harte
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ffcd2ea10c
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Attempts more properly to implement line mode.
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2021-09-28 21:39:09 -04:00 |
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Thomas Harte
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cb460de94d
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Makes bad first attempt at a Bresenham inner loop.
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2021-09-27 22:06:00 -04:00 |
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Thomas Harte
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f6624bf776
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Edges mildly closer to line output.
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2021-09-26 19:18:12 -04:00 |
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Thomas Harte
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b4b6c4d86f
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Attempts to support left and right masks.
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2021-09-26 18:42:08 -04:00 |
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Thomas Harte
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759689ff31
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Fix line mode flag, add busy status.
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2021-09-26 18:16:00 -04:00 |
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Thomas Harte
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c4ab2bbeed
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Hard-code fetch window width. For now.
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2021-09-23 22:06:13 -04:00 |
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Thomas Harte
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42ef459e20
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Resolve resting values.
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2021-09-23 22:05:59 -04:00 |
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Thomas Harte
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cad1a9e0f1
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Correct bit test.
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2021-09-23 20:42:31 -04:00 |
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Thomas Harte
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f1d514470d
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Add note to future self.
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2021-09-23 20:29:39 -04:00 |
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Thomas Harte
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9a7a54f22f
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Take alternative guess as to meaning of 'use' bits.
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2021-09-23 18:42:12 -04:00 |
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Thomas Harte
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137d1c61bd
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Allow for channel enables and blitting direction.
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2021-09-23 18:38:37 -04:00 |
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Thomas Harte
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adc071ed7a
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Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.
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2021-09-23 18:30:35 -04:00 |
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Thomas Harte
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e06f470044
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Ensure no implicit conversion from int to IntT.
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2021-09-23 18:30:04 -04:00 |
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Thomas Harte
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ab69fe56c9
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Take a first shot at magical instant blitting.
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2021-09-23 18:13:51 -04:00 |
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Thomas Harte
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60bad22a91
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Correct fetch window.
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2021-09-23 18:13:24 -04:00 |
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Thomas Harte
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7092429f7c
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Added some notes to self on line mode.
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2021-09-20 23:08:26 -04:00 |
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Thomas Harte
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fa800bb809
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Introduces code for minterm application.
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2021-09-20 19:13:23 -04:00 |
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Thomas Harte
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e15f1103a0
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Takes a shot at low resolution shifting.
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2021-09-20 19:00:52 -04:00 |
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Thomas Harte
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a4263b5a8c
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Ties bitplane collection to line position.
Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.
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2021-09-19 21:55:45 -04:00 |
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Thomas Harte
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245b7baa61
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Moves the Copper into its own file.
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2021-09-16 21:17:23 -04:00 |
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Thomas Harte
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0eeaaa150a
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Correct Copper start address.
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2021-09-16 21:01:37 -04:00 |
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Thomas Harte
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692d87f446
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Attempts to restrict blitter slot allocation.
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2021-09-16 19:56:28 -04:00 |
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Thomas Harte
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6572efe2a7
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Clarifies word addressing.
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2021-09-16 08:24:52 -04:00 |
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Thomas Harte
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8aac2bd029
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Stubs in serial port status.
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2021-09-14 21:53:07 -04:00 |
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Thomas Harte
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add11db369
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Factors out DMADevice, which is now a parent of Blitter.
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2021-09-14 20:51:32 -04:00 |
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Thomas Harte
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fd70f7ad43
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Attempts to make pixel content observeable.
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2021-09-08 20:57:26 -04:00 |
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Thomas Harte
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6e034c9b7f
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At least manages to place a pixel region on screen.
Albeit that I've suddenly realised that I've failed properly to think about high-res versus low-res.
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2021-08-11 20:31:37 -04:00 |
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Thomas Harte
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52e375a985
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Move towards playfield decoding.
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2021-08-11 18:47:35 -04:00 |
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Thomas Harte
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10a5e7313f
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Makes a buggy first attempt at bitplane data collection.
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2021-08-10 21:28:48 -04:00 |
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Thomas Harte
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ec9cb21fae
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Starts towards bitplane collection.
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2021-08-10 19:01:41 -04:00 |
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Thomas Harte
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fdd02ad6a6
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Neaten, slightly.
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2021-08-10 09:20:34 -04:00 |
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Thomas Harte
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76e9fcc94a
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Obey blitter DMA-enable mask.
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2021-08-10 09:19:15 -04:00 |
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Thomas Harte
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e412927415
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Logs a bit more from the Blitter, gives it access to slots.
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2021-08-10 07:17:01 -04:00 |
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Thomas Harte
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dda154c7c6
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Adds nonsense disk reads, which seems to lead to bitplane and blitter requests.
Progress, at last!
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2021-08-09 20:31:14 -04:00 |
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Thomas Harte
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9215535bee
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Adds a container for the disk controller.
Thereby appears to prove that my Amiga is getting as far as attempting to load from floppy.
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2021-08-09 17:35:09 -04:00 |
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Thomas Harte
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1502c4530e
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Takes a further step towards real timing.
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2021-08-08 21:52:28 -04:00 |
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Thomas Harte
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c1df4d1c0b
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Mirroring is correct.
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2021-08-08 20:20:12 -04:00 |
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Thomas Harte
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7f2610c4fc
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Disambiguates serial control logs.
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2021-08-07 16:57:30 -04:00 |
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Thomas Harte
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db3c158215
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Further increases logging.
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2021-08-05 20:07:14 -04:00 |
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Thomas Harte
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25e2bd307a
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Sets VPA for CIA accesses; logs a little more.
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2021-08-05 20:06:48 -04:00 |
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Thomas Harte
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1bae4973bc
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Post the serial control write onwards.
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2021-07-30 18:24:27 -04:00 |
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Thomas Harte
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3d9f86c584
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Begins keyboard sketches and notes.
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2021-07-30 18:23:15 -04:00 |
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Thomas Harte
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3514e537ca
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Minor logging tweaks.
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2021-07-30 18:22:59 -04:00 |
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Thomas Harte
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b78090ec76
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Fixes IOPortsAndTimers classification.
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2021-07-28 19:39:42 -04:00 |
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Thomas Harte
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759007ffc1
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Attempts to route CIA interrupts.
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2021-07-28 19:36:30 -04:00 |
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