2594 Commits

Author	SHA1	Message	Date
Thomas Harte	e961d0b4a3	Switch RDY type.	2021-10-06 04:41:09 -07:00
Thomas Harte	2253ff656a	Adds route for inserting disks.	2021-10-05 16:12:30 -07:00
Thomas Harte	18631399ad	Attempts to clock the disk controller.	2021-10-05 15:38:56 -07:00
Thomas Harte	ad4afcdcd5	Switch stepping direction. ... Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.	2021-10-05 15:23:48 -07:00
Thomas Harte	2cf5bcc5db	Clarify logic somewhat.	2021-10-05 15:20:05 -07:00
Thomas Harte	1180ad7662	Disables a couple of now-trustworthy LOGs.	2021-10-05 06:51:47 -07:00
Thomas Harte	5463cd1ae3	Attempts to support stepping and head selection.	2021-10-05 06:36:17 -07:00
Thomas Harte	647ec770ce	Implements motor latching, drive ID shift registers.	2021-10-05 05:12:01 -07:00
Thomas Harte	e47bec2e65	Switch CIA B ports over.	2021-10-05 03:38:11 -07:00
Thomas Harte	674941abdf	Starts to add a disk controller.	2021-10-04 16:45:05 -07:00
Thomas Harte	b3f0ca39ed	Adds some unused drives.	2021-10-04 08:12:13 -07:00
Thomas Harte	5ccb512883	Moves the CIAs into the Chipset class. ... This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.	2021-10-04 06:44:54 -07:00
Thomas Harte	da286d5ae8	Switch spaces to tabs.	2021-10-04 05:27:25 -07:00
Thomas Harte	a282a51673	Remove last of the direct printf'ing.	2021-09-30 02:42:59 -04:00
Thomas Harte	b7b13e20d1	Single column blits should use both masks.	2021-09-29 22:49:35 -04:00
Thomas Harte	402fa41bc0	Corrects initial error value.	2021-09-29 22:19:17 -04:00
Thomas Harte	0b9ebafc0f	Flip bit deserialisation order.	2021-09-28 22:12:13 -04:00
Thomas Harte	140e24ef15	Grab further copy flags.	2021-09-28 22:11:58 -04:00
Thomas Harte	ffcd2ea10c	Attempts more properly to implement line mode.	2021-09-28 21:39:09 -04:00
Thomas Harte	cb460de94d	Makes bad first attempt at a Bresenham inner loop.	2021-09-27 22:06:00 -04:00
Thomas Harte	f6624bf776	Edges mildly closer to line output.	2021-09-26 19:18:12 -04:00
Thomas Harte	b4b6c4d86f	Attempts to support left and right masks.	2021-09-26 18:42:08 -04:00
Thomas Harte	759689ff31	Fix line mode flag, add busy status.	2021-09-26 18:16:00 -04:00
Thomas Harte	9012a7f5e1	Merge branch 'master' into Amiga	2021-09-23 23:00:03 -04:00
Thomas Harte	e5a5faa417	Resolves Clang 13 implicit conversion warnings.	2021-09-23 22:53:41 -04:00
Thomas Harte	c4ab2bbeed	Hard-code fetch window width. For now.	2021-09-23 22:06:13 -04:00
Thomas Harte	42ef459e20	Resolve resting values.	2021-09-23 22:05:59 -04:00
Thomas Harte	cad1a9e0f1	Correct bit test.	2021-09-23 20:42:31 -04:00
Thomas Harte	f1d514470d	Add note to future self.	2021-09-23 20:29:39 -04:00
Thomas Harte	9a7a54f22f	Take alternative guess as to meaning of 'use' bits.	2021-09-23 18:42:12 -04:00
Thomas Harte	137d1c61bd	Allow for channel enables and blitting direction.	2021-09-23 18:38:37 -04:00
Thomas Harte	adc071ed7a	Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.	2021-09-23 18:30:35 -04:00
Thomas Harte	e06f470044	Ensure no implicit conversion from int to IntT.	2021-09-23 18:30:04 -04:00
Thomas Harte	ab69fe56c9	Take a first shot at magical instant blitting.	2021-09-23 18:13:51 -04:00
Thomas Harte	60bad22a91	Correct fetch window.	2021-09-23 18:13:24 -04:00
Thomas Harte	7092429f7c	Added some notes to self on line mode.	2021-09-20 23:08:26 -04:00
Thomas Harte	fa800bb809	Introduces code for minterm application.	2021-09-20 19:13:23 -04:00
Thomas Harte	e15f1103a0	Takes a shot at low resolution shifting.	2021-09-20 19:00:52 -04:00
Thomas Harte	a4263b5a8c	Ties bitplane collection to line position. ... Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.	2021-09-19 21:55:45 -04:00
Thomas Harte	245b7baa61	Moves the Copper into its own file.	2021-09-16 21:17:23 -04:00
Thomas Harte	0eeaaa150a	Correct Copper start address.	2021-09-16 21:01:37 -04:00
Thomas Harte	692d87f446	Attempts to restrict blitter slot allocation.	2021-09-16 19:56:28 -04:00
Thomas Harte	6572efe2a7	Clarifies word addressing.	2021-09-16 08:24:52 -04:00
Thomas Harte	8aac2bd029	Stubs in serial port status.	2021-09-14 21:53:07 -04:00
Thomas Harte	add11db369	Factors out DMADevice, which is now a parent of Blitter.	2021-09-14 20:51:32 -04:00
Thomas Harte	e47eab1d40	Merge branch 'master' into Amiga	2021-09-14 20:27:59 -04:00
Thomas Harte	fa71ae3174	Add apology.	2021-09-14 20:23:36 -04:00
Thomas Harte	dfcd1508c9	Establishes valid initial BRAM.	2021-09-10 19:56:20 -04:00
Thomas Harte	7e5fc4444a	Default to ROM01.	2021-09-09 22:09:09 -04:00
Thomas Harte	d8e42c4379	Tweak guess at initial state.	2021-09-09 22:06:36 -04:00