Thomas Harte
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ff3c60c0e1
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Implemented the conditional JRs.
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2017-05-25 21:51:30 -04:00 |
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Thomas Harte
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399703a471
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Implemented JR.
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2017-05-25 21:48:28 -04:00 |
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Thomas Harte
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82017c4aea
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Implemented DJNZ.
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2017-05-25 21:44:24 -04:00 |
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Thomas Harte
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bdf07c3dc9
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Implemented EX AF, AF'.
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2017-05-25 21:26:32 -04:00 |
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Thomas Harte
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598be24644
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Fixed overflow for 8-bit decrementing.
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2017-05-25 21:23:38 -04:00 |
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Thomas Harte
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e4e71a1e5f
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Switched back to descriptive failures, but put a cap on them.
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2017-05-25 21:08:24 -04:00 |
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Thomas Harte
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fba5af280e
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Shortened failure message, at least for now.
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2017-05-25 21:05:47 -04:00 |
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Thomas Harte
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c668ff9472
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Added incrementing of the refresh register.
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2017-05-25 21:01:52 -04:00 |
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Thomas Harte
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2cadc706e2
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Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started.
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2017-05-25 21:00:33 -04:00 |
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Thomas Harte
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3c6f63abcc
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Started towards running the FUSE tests. Just need to deal with the memory segments.
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2017-05-25 19:12:59 -04:00 |
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Thomas Harte
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00cd7e7e9c
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After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.
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2017-05-25 18:20:13 -04:00 |
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Thomas Harte
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055c860b43
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Sealed off RegisterState as immutable, and started trying to parse the .expected file.
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2017-05-23 22:32:36 -04:00 |
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Thomas Harte
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454c8628c3
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Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable.
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2017-05-23 22:05:33 -04:00 |
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Thomas Harte
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a23a6db4d6
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Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine.
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2017-05-23 08:13:24 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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c3ea6dc1f5
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Added respect for limiting to the requested number of cycles in the Z80.
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2017-05-22 19:15:55 -04:00 |
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Thomas Harte
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22afa509ca
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Got to a parsing and towards an attempt to run FUSE tests.
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2017-05-22 19:14:46 -04:00 |
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Thomas Harte
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3fb3cc8269
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Got explicit about encodings.
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2017-05-21 22:53:06 -04:00 |
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Thomas Harte
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e3e461d7cb
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Added a test class for running the FUSE tests. With nothing much in it.
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2017-05-21 22:49:24 -04:00 |
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Thomas Harte
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c16fccb317
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Fixed file names.
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2017-05-21 22:43:07 -04:00 |
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Thomas Harte
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b9cffdf2bd
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Imported the FUSE tests.
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2017-05-21 22:42:20 -04:00 |
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Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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c66c715ac9
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Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
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2017-05-21 19:26:40 -04:00 |
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Thomas Harte
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5dcfd85642
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Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
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2017-05-21 19:15:52 -04:00 |
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Thomas Harte
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c70dfe1b09
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Implemented the two variations of loading between (nn) and SP.
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2017-05-21 13:20:28 -04:00 |
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Thomas Harte
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232c591655
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Threw in a little macro documentation and a missing macro.
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2017-05-21 13:13:21 -04:00 |
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Thomas Harte
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790614b544
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Added EI and DI.
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2017-05-21 12:53:17 -04:00 |
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Thomas Harte
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32c032cd97
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Implemented a couple of easy-to-add missing base page instructions.
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2017-05-21 10:18:43 -04:00 |
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Thomas Harte
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e48ee16366
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Continued cleaning efforts, added conditional RET.
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2017-05-21 10:13:59 -04:00 |
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Thomas Harte
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e92d936ce8
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Added conditional calls.
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2017-05-21 10:03:46 -04:00 |
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Thomas Harte
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4e210c5396
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Added LD A, (nn).
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2017-05-21 10:00:10 -04:00 |
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Thomas Harte
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3d3e60b1fc
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Implemented LD (HL), r.
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2017-05-21 09:56:41 -04:00 |
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Thomas Harte
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f3f0e2f1a9
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Implemented RRA and RRCA.
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2017-05-21 09:52:19 -04:00 |
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Thomas Harte
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08206eea56
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This logging has outlived its usefulness for now.
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2017-05-21 09:47:53 -04:00 |
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Thomas Harte
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78296246e8
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Added ALU n.
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2017-05-21 09:46:18 -04:00 |
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Thomas Harte
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85b5dd35b1
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Took a shot at 8-bit arithmetic.
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2017-05-21 09:43:17 -04:00 |
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Thomas Harte
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11cfaa3e3d
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Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement.
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2017-05-21 09:17:30 -04:00 |
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Thomas Harte
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103c863534
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Through temporarily dramatically increased logging, fixed conditional JP.
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2017-05-20 23:03:52 -04:00 |
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Thomas Harte
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6688f83226
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Took a shot at LDIR.
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2017-05-20 21:58:24 -04:00 |
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Thomas Harte
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01a064dd63
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Added an empty ED page.
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2017-05-20 17:29:30 -04:00 |
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Thomas Harte
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7b234078ae
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Implemented EX DE, HL and shuffled to allow instruction pages.
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2017-05-20 17:04:25 -04:00 |
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Thomas Harte
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add02a7897
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Added LD (nn), A, and reduced double logging to single for now.
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2017-05-19 23:13:28 -04:00 |
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Thomas Harte
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19167df692
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Consolidated and filled in AND and XOR.
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2017-05-19 23:03:34 -04:00 |
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Thomas Harte
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6766845e21
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Filled in most of the loads.
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2017-05-19 22:57:43 -04:00 |
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Thomas Harte
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bc3b5f3e35
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Added 16-bit INCs and DECs. Which don't set flags, so are easy.
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2017-05-19 22:13:36 -04:00 |
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Thomas Harte
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5fe23113ec
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Moved RET to the correct place, implemented POP AF.
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2017-05-19 22:03:12 -04:00 |
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Thomas Harte
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c55e1c1d17
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Implemented POP and therefore RET; corrected timing of PUSH.
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2017-05-19 21:59:45 -04:00 |
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