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2016-10-20

2016-11-03

2016-11-08

2016-12-06

2016-12-31

2017-01-01

2017-01-27

2017-01-30

2017-03-26

2017-03-26.2

2017-05-14

2017-05-16

2017-07-15

2017-07-30

2017-08-16

2017-08-27

2017-10-24

2017-11-03

2017-11-22

2017-11-23

2018-01-13

2018-01-15

2018-01-18

2018-02-21

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2018-03-04

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2018-03-23

2018-04-07

2018-04-13

2018-05-15

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2018-06-03

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2018-08-26

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2019-03-02

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2019-03-10

2019-07-27

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2019-11-05

2019-11-17

2019-12-25

2019-12-26

2020-01-01

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2020-03-07

2020-03-10

2020-03-21

2020-05-10

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2020-07-27

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2020-09-16

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2020-11-29

2020-12-09

2021-02-02

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2021-03-25

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2021-04-16.2

2021-04-19

2021-04-21

2021-05-05

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untagged-83a648386d4da3db578a

Mono Color

• 985fbf59c2 Merge pull request #169 from TomHarte/Z80HasA Thomas Harte 2017-08-02 22:42:49 -04:00
• 2f2071be8a These should actually both be in the public header, as the types are used in an exposed method. Thomas Harte 2017-08-02 22:18:30 -04:00
• 6d510e4e70 Made it no longer public knowledge that any sort of Typer is involved in being a ZX80/81. Thomas Harte 2017-08-02 22:17:22 -04:00
• 8e0736fbe6 Reinstated typing ability, albeit with an ugly inline insertion. But I think I can defer dealing with typers to another pull request. The whole issue of keyboard mapping probably needs reappraisal. Thomas Harte 2017-08-02 22:16:09 -04:00
• 681d1e2f8d Breaking its typer for now, adapted the ZX80/81 to having a Z80, not being one. Thomas Harte 2017-08-02 22:12:59 -04:00
• 42e70ef993 Adjusted slightly as per Z80 change, and to pull everything internally declared into the Amstrad CPC namespace. Thomas Harte 2017-08-02 22:11:03 -04:00
• 039811ce6a Switched the Z80 to being something a machine has, not something a machine is. Thomas Harte 2017-08-02 22:09:59 -04:00
• a54ccd1969 Merge pull request #168 from TomHarte/CPC Thomas Harte 2017-08-02 20:50:02 -04:00
• 707821ca55 Added the normal readme to explain what's omitted here. Thomas Harte 2017-08-02 20:45:14 -04:00
• d3bf8fa53b Upped the documentation. Thomas Harte 2017-08-02 20:37:26 -04:00
• f5e2dd410e Constrained output to the centre 90%. Thomas Harte 2017-08-02 19:55:44 -04:00
• 3ca9c38777 Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc. Thomas Harte 2017-08-02 19:45:58 -04:00
• 2d2cefb0b0 Adjusted factoring to introduce support for block 10. Thomas Harte 2017-08-02 14:36:47 -04:00
• 2fd071e45d Made an honest attempt at outputting turbo speed data block data. The CPC now at least starts to load. Thomas Harte 2017-08-02 14:24:34 -04:00
• d7a5c3f49a Added support for the ID 20 block and fixed a minor error in my skip-the-contents version of block 11: length is three bytes long, not two. This gives me enough structure properly to get to the end of my current test CDT, albeit without making any of the noises. Thomas Harte 2017-08-02 14:12:34 -04:00
• 819761f9fb Fixed another uninitialised pointer. Thomas Harte 2017-08-02 13:56:35 -04:00
• e50adf1cc8 Were my TZX support up to it, this would likely be sufficient for tape emulation. Thomas Harte 2017-08-02 13:50:14 -04:00
• dcab10f53e Ensured the AY's async queue doesn't just fill and fill. Thomas Harte 2017-08-02 07:38:35 -04:00
• 633d8965e2 Removed accidental logging commit. Thomas Harte 2017-08-02 07:38:14 -04:00
• f602f9b6ec Adds an attempt to clock the AY. Thomas Harte 2017-08-02 07:21:33 -04:00
• f7e66dea61 Added a compound divide and convert. Thomas Harte 2017-08-02 07:21:21 -04:00
• bda9441620 Made an attempt to clock the AY. Thomas Harte 2017-08-02 07:20:59 -04:00
• 4d5d5041df Attempted to ensure a clean startup. Thomas Harte 2017-08-01 22:18:42 -04:00
• 587eb3a67c Factored interrupt counting out of the CRTCBusHandler. Thomas Harte 2017-08-01 22:15:39 -04:00
• 6ca07f1e28 I guess it might end up living somewhere else, but introduced a header with the compiler-specific stuff to allow me to force things inline. Thomas Harte 2017-08-01 22:04:58 -04:00
• 8d39a20088 Added proper output of mode 3, were anything ever to try to use it. Thomas Harte 2017-08-01 21:51:41 -04:00
• 4b6370eb86 Realised my colour error: mapping the ROM numbers as though they were the hardware numbers. Having fixed that, spotted that I was deserialising R and B the wrong way around and dividing by too much. Colours now appear to be correct. Thomas Harte 2017-08-01 21:47:52 -04:00
• c6e340a8a2 Wired up the vsync signal. Pen 15 no longer flashes like crazy. Still can't figure out why the palette is so askew; was looking for perhaps some sort of detection of a green screen rather than a colour one, but there's no obvious input for that. Thomas Harte 2017-08-01 21:21:59 -04:00
• 31c7153301 Corrected bit to colour mapping for modes 0 and 1. The total palette is still way off but there's consistency between modes now. Thomas Harte 2017-08-01 20:52:42 -04:00
• 7e04d00cc1 Fixed key values, causing the new set of keys to work, decreased quantity of output and ensured that pixels appear in modes 0 and 2. Thomas Harte 2017-08-01 20:39:10 -04:00
• 9d43784c65 Significantly increased quantity of keys forwarded. Thomas Harte 2017-08-01 20:37:55 -04:00
• eca9586a0f Fixed: input value is no longer overwritten by 0xff. The '0' key now works. Thomas Harte 2017-08-01 20:19:02 -04:00
• 0267bc237f Added the ability to set a port input, and relaxed bus state testing. I think my on-demand bus reactions here are inappropriate, so more work to do here probably. Thomas Harte 2017-08-01 18:04:51 -04:00
• 2e4577f741 Made a game attempt at implementing a (sticky) keyboard. No effect yet. Thomas Harte 2017-08-01 17:52:05 -04:00
• f5b278d683 Added enough stuff to put the emulated Amstrad CPC in a state of knowing whether its '0' key is pressed. Thomas Harte 2017-08-01 17:31:56 -04:00
• e6854ff8db Corrected typo: the input to an AY is BDIR, not BCDIR. Thomas Harte 2017-08-01 17:06:57 -04:00
• 3b292273c7 Fixed: BC2 is always implicitly set. The machine is now periodically checking the AY's register 14 (i.e. the first input port), so probably there's enough here now to implement keyboard input. Thomas Harte 2017-08-01 17:05:11 -04:00
• cb732e5d5f Made an attempt to wire in an [unclocked] AY, in an endeavour to get to keyboard reading. Thomas Harte 2017-08-01 17:01:58 -04:00
• 2d4e202be3 Completed dangling comment. Thomas Harte 2017-08-01 17:01:36 -04:00
• 64da8e17d1 Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended. Thomas Harte 2017-08-01 17:01:20 -04:00
• 08ad35efd9 It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC. Thomas Harte 2017-08-01 16:34:13 -04:00
• 58b98267fc Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first. Thomas Harte 2017-08-01 16:15:19 -04:00
• ace71280a0 Removed implementation file; this is only ever going to be a template. Thomas Harte 2017-08-01 16:00:17 -04:00
• a27946102a Took a shot at the interrupt counter. Attempts at keyboard reading now recur so it'll probably do for now. I think that next puts me into the realm of needing to implement the 8255. Thomas Harte 2017-08-01 15:49:16 -04:00
• 1d99c116e7 Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it. Thomas Harte 2017-08-01 15:29:37 -04:00
• ee27e16fb1 Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely. Thomas Harte 2017-08-01 15:19:25 -04:00
• 6ac7132799 Had a quick go at properly outputting Mode 1, adding wiring to communicate palette and mode changes to the CRTC bus handler. Colours are off but it's sufficient for now. Thomas Harte 2017-08-01 15:16:13 -04:00
• ca42abab70 Doubled up to ensure that every byte that should be inspected is represented. This makes it clearer that I'm on the right road. A garbled version of 'Amstrad 64k Microcomputer' can be discerned, in a weird grayscale and with the right-hand column missing and skewed output as a result. Thomas Harte 2017-08-01 07:56:44 -04:00
• 933d69a256 Fixed slightly: the CPC wiki has a typo. It's 12 and 13 that move up to 14 and 15. Thomas Harte 2017-08-01 07:51:13 -04:00
• 3b1db14817 Made a quick attempt at properly updating the refresh address. Thomas Harte 2017-08-01 07:36:03 -04:00
• 10a5581aea Made first attempt at offering some sort of pictographic of actual RAM contents. Thomas Harte 2017-08-01 07:34:12 -04:00
• 3ae699964f Ensured an actual pixel stream is supplied for pixel regions. Though it's just a long stream of white pixels for now. So visual output is unchanged. Thomas Harte 2017-08-01 07:24:29 -04:00
• 9d953421d8 After a quick check, added a couple of other _delegate initialisations. I should probably find a way to template this. Thomas Harte 2017-08-01 07:07:43 -04:00
• 763e3b65d1 Ensured a proper initial value for delegate_. Thomas Harte 2017-07-31 22:46:06 -04:00
• 42dd27c9b1 Shunted method bodies inline, given that there's no need for a declaration/definition distinction. Thomas Harte 2017-07-31 22:39:25 -04:00
• 2b168f7383 Disabled the address sanitiser as an every-time run again, as it just pushes my computer a bit too far. Thomas Harte 2017-07-31 22:32:56 -04:00
• 0536f089e1 Eliminated old-[personal-]fashioned line break. Thomas Harte 2017-07-31 22:32:26 -04:00
• 3df13cddd4 As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details. Thomas Harte 2017-07-31 22:32:04 -04:00
• e3f677fa37 I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs. Thomas Harte 2017-07-31 22:21:46 -04:00
• c2253c1e0f Fixed multiplier: the dot clock I've used to instantiate the CRT is the pixel clock, not the character clock. Thomas Harte 2017-07-31 22:17:46 -04:00
• 5c68b6cc21 Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor. Thomas Harte 2017-07-31 22:16:08 -04:00
• ffaa627820 Fixed frame restart when there is no adjustment period. Thomas Harte 2017-07-31 22:13:45 -04:00
• f742fd5d4a Made basic attempt to get something on screen: white where the display is enabled, black for the border. Thomas Harte 2017-07-31 22:13:20 -04:00
• 69b99fe127 Transferred ownership of the CRT to the CRTC bus handler, to give it easy access. Thomas Harte 2017-07-31 22:04:52 -04:00
• 5a396f6787 Added an explicit cast. Thomas Harte 2017-07-31 22:04:31 -04:00
• cb0dc7b434 I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing. Thomas Harte 2017-07-31 22:01:54 -04:00
• e28829bd1b Corrected CRTC timing, gave it someone to talk to and a means with which to talk. Thomas Harte 2017-07-31 20:14:46 -04:00
• 68ceeab610 Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation. Thomas Harte 2017-07-31 19:56:59 -04:00
• 68dca9d047 Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support. Thomas Harte 2017-07-31 19:37:28 -04:00
• d88ca151f4 Added a first attempt at output port decoding. Just logging for now. Thomas Harte 2017-07-31 19:25:10 -04:00
• 3c90218c3d With a very basic stab at something a bit like the memory map (sans paging), execution begins. Thomas Harte 2017-07-31 19:15:43 -04:00
• afd409c883 Ensured that ROM images are loaded and passed to the Amstrad CPC. Thomas Harte 2017-07-31 18:44:49 -04:00
• 26b6c03a2a Re-enabled the address sanitiser as a development tool. Thomas Harte 2017-07-31 07:30:07 -04:00
• 9c04d851e4 Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate. Thomas Harte 2017-07-31 07:29:50 -04:00
• 1d6fe11906 Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window. Thomas Harte 2017-07-31 07:16:51 -04:00
• c0f1313830 Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT. Thomas Harte 2017-07-30 22:05:29 -04:00
• fb51fadf00 Merge branch 'master' into CPC Thomas Harte 2017-07-30 21:29:31 -04:00
• 55fd9122d0 Slightly relaxed vertical sync testing. 2017-07-30 Thomas Harte 2017-07-30 21:19:42 -04:00
• 5b5720fac0 Added to the static analyser the most basic through-path for Amstrad CPC content. Thomas Harte 2017-07-30 21:15:20 -04:00
• d25d7d7d40 Added the Amstrad CPC as a named target and declared support for its CDT file format. Thomas Harte 2017-07-29 21:56:33 -04:00
• ba4f2d8917 Merge branch 'master' into VerticalSync Thomas Harte 2017-07-29 21:45:22 -04:00
• a2aec39633 Merge pull request #167 from TomHarte/VerticalSync Thomas Harte 2017-07-29 21:44:47 -04:00
• 0bf4fdc9af Simplified slightly. Thomas Harte 2017-07-29 21:37:59 -04:00
• ed8c73eb14 Ensured lengthy constant sync can't appear to be two sync pulses, regardless of other interruption. Thomas Harte 2017-07-29 18:25:04 -04:00
• 3528a7f78b Made an attempt at triggering vertical sync the expected number of time after it begins, regardless of total length. Thomas Harte 2017-07-29 17:33:52 -04:00
• 54bcc40192 With an eye towards being more accurate as to vertical sync recognition: acknowledged that the detection period varies between PAL and NTSC. Thomas Harte 2017-07-29 14:53:53 -04:00
• 4b5e9ffb83 Ensured is_at_end_ is initially cleared by default. Thomas Harte 2017-07-27 22:22:43 -04:00
• a7f5f035a6 Merge pull request #166 from TomHarte/NoRefs Thomas Harte 2017-07-27 22:07:05 -04:00
• 4abd62e62b Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. Thomas Harte 2017-07-27 22:05:29 -04:00
• 1fb158b297 Merge pull request #165 from TomHarte/HalfCycleTyper Thomas Harte 2017-07-27 21:56:02 -04:00
• 968d2bb8ba Brought Typer into the new run_for orthodoxy, making it easier to clock consistently regardless of unit. Which necessitated adding a negative operator for WrappedInts. Thomas Harte 2017-07-27 21:53:45 -04:00
• 92a3dfe44a Merge pull request #164 from TomHarte/NoInt Thomas Harte 2017-07-27 21:41:04 -04:00
• 9ef232157b Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles. Thomas Harte 2017-07-27 21:38:50 -04:00
• b9f4f7a530 Merge pull request #163 from TomHarte/WaitSampling Thomas Harte 2017-07-27 21:19:29 -04:00
• 761afad118 Corrected timestamp return, and its testing by the 6502 timing tests. Thomas Harte 2017-07-27 21:19:16 -04:00
• 8848ebbd4f Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81. Thomas Harte 2017-07-27 21:10:14 -04:00
• 37950143fc Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests. Thomas Harte 2017-07-27 20:17:13 -04:00
• 25fd95044c Merge pull request #154 from TomHarte/Memptr Thomas Harte 2017-07-27 08:10:22 -04:00
• 1da24d10fd Corrected a couple of build errors. Thomas Harte 2017-07-27 08:05:14 -04:00
• 60e374dca3 Merge branch 'master' into Memptr Thomas Harte 2017-07-27 07:54:25 -04:00