2005-02-05 02:24:26 +00:00
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//===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
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2005-01-22 23:41:55 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-01-22 23:41:55 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//3.3:
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//Memory
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//Branch
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//Operate
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//Floating-point
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//PALcode
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2005-10-20 00:28:31 +00:00
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def u8imm : Operand<i64>;
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def s14imm : Operand<i64>;
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def s16imm : Operand<i64>;
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def s21imm : Operand<i64>;
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2005-07-22 20:50:29 +00:00
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def s64imm : Operand<i64>;
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2006-10-31 16:49:55 +00:00
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def u64imm : Operand<i64>;
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2005-07-22 20:50:29 +00:00
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2005-01-22 23:41:55 +00:00
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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2005-11-09 19:17:08 +00:00
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// Alpha instruction baseline
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2006-03-09 17:16:45 +00:00
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class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
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2005-01-22 23:41:55 +00:00
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field bits<32> Inst;
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let Namespace = "Alpha";
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let AsmString = asmstr;
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let Inst{31-26} = op;
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2006-03-09 17:16:45 +00:00
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let Itinerary = itin;
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2005-01-22 23:41:55 +00:00
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}
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2005-11-09 19:17:08 +00:00
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2005-01-22 23:41:55 +00:00
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//3.3.1
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2008-01-06 06:44:58 +00:00
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class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
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2006-03-09 17:16:45 +00:00
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: InstAlpha<opcode, asmstr, itin> {
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2005-12-24 03:41:56 +00:00
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let Pattern = pattern;
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2008-12-03 18:15:48 +00:00
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let canFoldAsLoad = load;
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2006-01-26 03:22:07 +00:00
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let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
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2005-12-24 03:41:56 +00:00
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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2006-03-09 17:16:45 +00:00
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class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2005-11-11 16:47:30 +00:00
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bits<5> Ra;
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2010-03-18 20:55:18 +00:00
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let OutOperandList = (outs GPRC:$RA);
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let InOperandList = (ins);
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2005-11-11 16:47:30 +00:00
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let Inst{25-21} = Ra;
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2006-01-16 21:22:38 +00:00
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let Inst{20-16} = 0;
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2005-11-11 16:47:30 +00:00
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let Inst{15-0} = fc;
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}
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2008-02-16 01:24:58 +00:00
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class MfcPForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2010-03-18 20:55:18 +00:00
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let OutOperandList = (outs);
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let InOperandList = (ins);
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2008-02-16 01:24:58 +00:00
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let Inst{25-21} = 0;
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let Inst{20-16} = 0;
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let Inst{15-0} = fc;
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}
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2005-07-22 20:50:29 +00:00
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2006-03-09 17:16:45 +00:00
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class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2005-07-22 20:50:29 +00:00
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bits<5> Ra;
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bits<5> Rb;
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2006-06-12 18:09:24 +00:00
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bits<14> disp;
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2010-03-18 20:55:18 +00:00
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let OutOperandList = (outs);
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let InOperandList = OL;
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2006-06-12 18:09:24 +00:00
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-14} = TB;
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let Inst{13-0} = disp;
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}
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class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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let Pattern=pattern;
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bits<5> Ra;
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bits<5> Rb;
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2005-07-22 20:50:29 +00:00
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bits<14> disp;
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2010-03-18 20:55:18 +00:00
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let OutOperandList = (outs);
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let InOperandList = OL;
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2006-03-09 17:16:45 +00:00
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2005-07-22 20:50:29 +00:00
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-14} = TB;
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let Inst{13-0} = disp;
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}
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2005-01-22 23:41:55 +00:00
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//3.3.2
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2005-12-25 17:36:48 +00:00
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def target : Operand<OtherVT> {}
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2006-01-01 22:16:14 +00:00
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2007-07-21 00:34:19 +00:00
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
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2006-10-31 16:49:55 +00:00
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class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2010-03-18 20:55:18 +00:00
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let OutOperandList = (outs);
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let InOperandList = OL;
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2006-10-31 16:49:55 +00:00
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bits<64> Opc; //dummy
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2006-01-01 22:16:14 +00:00
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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2006-10-31 16:49:55 +00:00
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}
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2005-07-22 20:50:29 +00:00
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let isBranch = 1, isTerminator = 1 in
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2006-10-31 16:49:55 +00:00
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class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
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2006-03-09 17:16:45 +00:00
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: InstAlpha<opcode, asmstr, itin> {
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2006-01-01 22:16:14 +00:00
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let Pattern = pattern;
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2010-03-18 20:55:18 +00:00
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let OutOperandList = (outs);
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let InOperandList = (ins target:$DISP);
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2005-01-22 23:41:55 +00:00
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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//3.3.3
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2006-03-09 17:16:45 +00:00
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class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2005-10-20 00:28:31 +00:00
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let Pattern = pattern;
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let OutOperandList = (outs GPRC:$RC);
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let InOperandList = (ins GPRC:$RA, GPRC:$RB);
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2005-10-20 00:28:31 +00:00
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2005-07-22 20:50:29 +00:00
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bits<5> Rc;
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bits<5> Ra;
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bits<5> Rb;
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bits<7> Function = fun;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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2006-03-09 17:16:45 +00:00
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class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2005-10-20 19:39:24 +00:00
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let Pattern = pattern;
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let OutOperandList = (outs GPRC:$RC);
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let InOperandList = (ins GPRC:$RB);
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2005-10-20 19:39:24 +00:00
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bits<5> Rc;
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bits<5> Rb;
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bits<7> Function = fun;
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2005-10-22 22:06:58 +00:00
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let Inst{25-21} = 31;
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2005-10-20 19:39:24 +00:00
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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2006-03-09 17:16:45 +00:00
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class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2005-12-05 23:19:44 +00:00
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let Pattern = pattern;
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let OutOperandList = (outs GPRC:$RDEST);
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let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
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2007-04-17 04:07:59 +00:00
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let Constraints = "$RFALSE = $RDEST";
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let DisableEncoding = "$RFALSE";
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2005-12-05 23:19:44 +00:00
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bits<5> Rc;
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bits<5> Ra;
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2007-04-17 04:07:59 +00:00
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bits<5> Rb;
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2005-12-05 23:19:44 +00:00
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bits<7> Function = fun;
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2010-06-21 18:48:55 +00:00
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// let Constraints = "$RFALSE = $RDEST";
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2005-12-05 23:19:44 +00:00
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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2005-01-22 23:41:55 +00:00
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2006-03-09 17:16:45 +00:00
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class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2005-10-20 00:28:31 +00:00
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let Pattern = pattern;
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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let OutOperandList = (outs GPRC:$RC);
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let InOperandList = (ins GPRC:$RA, u8imm:$L);
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2005-10-20 00:28:31 +00:00
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2005-07-22 20:50:29 +00:00
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bits<5> Rc;
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bits<5> Ra;
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bits<8> LIT;
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bits<7> Function = fun;
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let Inst{25-21} = Ra;
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let Inst{20-13} = LIT;
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let Inst{12} = 1;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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2006-03-09 17:16:45 +00:00
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class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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2006-02-01 19:37:33 +00:00
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let Pattern = pattern;
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
let OutOperandList = (outs GPRC:$RDEST);
|
|
|
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let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
|
2007-04-17 04:07:59 +00:00
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let Constraints = "$RFALSE = $RDEST";
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let DisableEncoding = "$RFALSE";
|
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2005-10-20 23:58:36 +00:00
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bits<5> Rc;
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bits<5> Ra;
|
2007-04-17 04:07:59 +00:00
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bits<8> LIT;
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2005-01-24 19:44:07 +00:00
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bits<7> Function = fun;
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2005-01-22 23:41:55 +00:00
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2010-06-21 18:48:55 +00:00
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|
// let Constraints = "$RFALSE = $RDEST";
|
2005-01-22 23:41:55 +00:00
|
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|
let Inst{25-21} = Ra;
|
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let Inst{20-13} = LIT;
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let Inst{12} = 1;
|
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let Inst{11-5} = Function;
|
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|
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let Inst{4-0} = Rc;
|
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|
|
}
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//3.3.4
|
2006-03-09 17:16:45 +00:00
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|
class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
|
|
|
|
: InstAlpha<opcode, asmstr, itin> {
|
2005-11-09 19:17:08 +00:00
|
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|
let Pattern = pattern;
|
2005-07-28 18:14:47 +00:00
|
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|
2005-01-22 23:41:55 +00:00
|
|
|
bits<5> Fc;
|
2005-07-28 18:14:47 +00:00
|
|
|
bits<5> Fa;
|
|
|
|
bits<5> Fb;
|
|
|
|
bits<11> Function = fun;
|
2005-01-22 23:41:55 +00:00
|
|
|
|
|
|
|
let Inst{25-21} = Fa;
|
|
|
|
let Inst{20-16} = Fb;
|
|
|
|
let Inst{15-5} = Function;
|
|
|
|
let Inst{4-0} = Fc;
|
|
|
|
}
|
|
|
|
|
|
|
|
//3.3.5
|
2006-03-09 17:16:45 +00:00
|
|
|
class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
|
|
|
|
: InstAlpha<opcode, asmstr, itin> {
|
2010-03-18 20:55:18 +00:00
|
|
|
let OutOperandList = (outs);
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
let InOperandList = OL;
|
2005-01-22 23:41:55 +00:00
|
|
|
bits<26> Function;
|
|
|
|
|
|
|
|
let Inst{25-0} = Function;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Pseudo instructions.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin>
|
2006-03-09 17:16:45 +00:00
|
|
|
: InstAlpha<0, nm, itin> {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
|
|
|
let OutOperandList = OOL;
|
|
|
|
let InOperandList = IOL;
|
2005-11-22 04:20:06 +00:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-01-22 23:41:55 +00:00
|
|
|
}
|